201104757 六、發明說明： 【發明所屬之技術領域】 本申請案之技術係關於閘控二極體及其在電路中之使用 及相關方法，該等電路包括保護電路、靜電放電（ESD)保 護電路’及高速或切換電路。 【先前技術】 靜電放電（ESD)為積體電路（IC)中之主要可靠性問題。 ESD為可在電路中誘發大電流的電壓暫態突波（正突波或負 突波）。為了保護電路免受ESD突波的損害，保護方案試圖 為正ESD突波與負ESD突波兩者提供放電路徑。習知二極 體可用於ESD保護電路中，以箝制正及負ESD突波的電 壓，從而使電流分流並防止過量電壓施加至受保護電路。 就此而言’圖1說明習知ESD保護電路。如圖}中所說明， 提供電壓軌（Vdd)l〇及接地軌（Gnd)12以對受保護電路14供 電。受保護電路14可為任何類型之電路，且以任何所要形 式提供。在此實例中，呈信號接腳16形式的端子提供至受 保護電路14的信號路徑，以用於將資訊及/或控制提供至 受保護電路14。舉例而言，受保護電路14可包括於1(：中， 其中"is 5虎接腳16為IC晶片上之外部可用接腳。 習知ESD保護電路18可耦接於電壓執1 〇與接地軌丨2之 間，以保護受保護電路14免受ESD突波的影響。圖}中之 例示性ESD保護電路18包括兩個習知二極體：一正ESD突 波二極體20及一負ESD突波二極體22。正ESD突波二極體 20與負ESD突波二極體22經串聯耦接。正ESD突波二極體 147074.doc 201104757 20將信號接腳16上之正電壓箝制至高於電壓執ι〇的二極體 電麼降（diode drop)。負ESD突波二極體22將信號接腳16上 之負電壓箝制至低於接地軌12的二極體電壓降。正ESD突 波二極體20之陰極（k)耦接至電壓執1〇。正ESD二極體20之 陽極（a)在信號接腳16與受保護電路14之間的信號路徑上之 節點24處耦接至信號接腳16。負ESD突波二極體22之陰極 (k)亦耦接至自信號接腳16至受保護電路14之信號路徑上的 節點24。負ESD突波二極體22之陽極（a)耦接至接地執12。 對於信號接腳16上之正ESD突波，正ESD突波二極體20 將變為經正向偏壓，且將信號接腳丨6上之電壓箝制至高於 電Μ軌10的二極體電壓降’從而保護受保護電路14。來自 此ESD突波之能量將經由處於正向偏壓模式之正ESD突波 一極體20傳導’且分散至電壓軌1〇中。適當之ESD保護結 構可貫施（未圖示）於電壓軌1〇中，以最終將正ESD突波耗 散至接地軌12。對於信號接腳16上之負ESD突波，類似地 耗政忒突波。信號接腳i 6上之負ESD突波將使負ESD突波 二極體22置於正向偏壓模式中，因此相對於受保護電路14 提供低阻抗路徑。來自負ESD突波之能量將耗散至接地執 12中。 因為歸因於較咼電晶體計數而正逐步以晶載系統（s〇c) 組態來提供電路，所以在S0C技術中提供ESD保護變得日 丄重要。S0C技術可使用提供相對薄之氧化物閘極介電質 的場效電晶體（FET卜此等相對薄之介電質由於來自㈣ 突波事件之過量電壓而易受到破壞性擊穿及損害。另外， 147074.doc 201104757 習知二極體（諸如，提供於圖1中之ESD突波二極體20、22) 不可為SOC技術中之ESD保護提供充分傳導。 為了解決ESD保護之此等缺點（且詳言之，對於s〇c技 術）’已在ESD保護電路中提供淺溝槽隔離（sti)二極體。 閘控二極體亦正用於ESD保護電路中。已展示，歸因於閘 控一極體载流子之暫態路徑’使用閘控二極體具有優良之 每單位長度的傳導率以及接通速度。ESD保護電路之接通 速度對於符合充電器件模型化（CDm)規範為重要的，其中 在ESD事件期間，大量電流（例如，若干安培）可在極小時 間段内（例如，小於一奈秒）流過。然而，即使閘控二極體 具有此等優點，STI二極體仍主要用於針對高速電路的 ESD保護電路中。閘控二極體可以不可接受之方式降低效 旎。閘控二極體與STI二極體相比每單位擴散或作用長度 具有較大周邊電容。此情形藉由實例在圖2之模型化圖表 26中予以說明，其中相對於輸入電壓（v)繪製對應於圖j之 閘控二極體對28的輸入電容（C)與STI二極體對3〇的輸入電 容（C)。此實例假設一 65奈米（nm)製程。如圖所屐示，對 於二極體之給定電壓（V)、長度及寬度（分別為大致8 〇微米 (μηι)及0.45微米）’閘控二極體對28之經正規化至STi二極 體對30之最大電容的輸入電容（c)高於STI二極體對儿的輸 入電容（c)。舉例而言，在軌電壓（Vdd)下，閘控二極體對 28之正規化電容（〇接近i s，而STI二極體對3〇之正規化電 容（C)大致為ι·〇。在此實例中，此情形等同於閘控二極體 對28相比STI二極體對30具有大致百分之八十（8〇%)的電容 147074.doc 201104757 增加。 當將閘控二極體添加至受保護電路時，間控二極體之增 加之周邊電容增加負載電容。增加負载電容可負面地影塑 受保護電路。舉例而言’增加之負載電容可降低受保護電 路之切換時間及頻率效能，此係因為在R-C電路配置中， 充電時間將歸因於ESD保護電路輕接至受保護電路而增 加。另外，由於插入ESD保護電路而提供的增加之電容可 使射頻（RF)組件（諸如，低雜訊放大器（LNA))的敏感性降 低。然而，相比使用閘控二極體，在ESD保護電路中使用 具有較低電谷之STI一極體亦具有取捨（trade 〇ff)。在esd 保護電路中使用STI二極體可導致受保護電路對正突波與 負突波兩者之低CDM電壓容限’且尤其對於使用薄氧化物 閘極氧化物介電質器件之受保護電路及相關製程而言係如 此’該等薄氧化物閘極氧化物介電質器件耦接至可在大 SOC晶片中找到之襯墊。 為保持效能’晶片製造商及消費者必須接受由於在ESD 保護電路中使用STI二極體而提供的較低CDM電壓容限， 其導致與ESD相關之較大曝露及故障。因此，需要提供一 種ESD保護電路，其展現優良傳導率及接通時間以及低電 容，以便不會不利地影響受保護電路的效能。 【發明内容】 在[實施方式]中所揭示之實施例包括閘控二極體之實 例、製造該等閘控二極體之例示性方法，及相關電路及方 法。該等閘控二極體實例皆具有經阻隔以減小該閘控二極 147074.doc 201104757 體之電令的至少—個淡換雜:¾極（LDD)植體。以此方式’ -亥閘控—極體可用於效能對於負載電容可能敏感的電路及 其他電路應用t，但亦需要或要求一閘控二極體的效能特 _ 一極體之益處包括（但$限於）快速接通時間及 高傳導率。 在本文中所揭不之實施例中，該閘控二極體包括一具有 井區域的半導體基板。該井區域包括-具有-雜質的半 導體材料。雜質包括—經卩型摻雜之雜質或經则換雜之雜 質。在3井區域上提供—絕緣層…閘電極形成於該絕緣 層上方。在該閘電極之相對側上將一陽極區域及一陰極區 域植入於β井區域中。視該閘控二極體之設計而定，該陽 極區域或該陰極區域具有―雜質，該雜質具有與—井區域 之極性相反的極性’以形成一ρ_Ν接面。在一實例中，對 於含於-Ν型井區域内之一二極體，該陽極區域具有一雜 質’該雜質具有與來自該_井區域之雜f之極性相反的 極性’以在該陽極與該井區域之間形成一 p_N接面。在另 一實例中’對於含於-P型井區域内之_二極體，該陰極 區域具有一雜質，該雜質具有與來自該p型井區域之雜質 之極性相反的極性，以在該陰極與該井區域之間形成一p_ N接面。玄井區域具有在該陽極區域、該陰極區域或該陽 極區域及該陰極區域兩者之間經阻隔的至少一個植 具有至少一個經阻隔之LDD植體的該閘控二極體可包括 於任何電路、積體電路或電路應用中…實例包括一靜電 147074.doc 201104757 放電（ESD)保護電路。一ESD保護電路藉由該閘控二極體 之快速接通時間及高傳導率特性來增強。然而，若該ESD 保護電路使用具有至少一個經阻隔之LDD植體的該等閘控 二極體中之一或多者，則該ESD保護電路之電容亦被減 小。此情形可允許使用該ESD保護電路保護效能對於負載 電容敏感的電路，同時仍達成閘控二極體的該等ESD特 性。否則，在不以一種不可接受之方式影響該受保護電路 之效能的情況下，在該ESD保護電路中使用閘控二極體為 不可能的。受保護電路之其他實例包括高速差動輸入/輸 出電路及射頻（RF)電路，射頻（rf)電路包括（但不限於）低 雜訊放大器（LNA)，該等受保護電路之效能可能對負載電 容敏感且因此可受益於本文中所揭示之該等閘控二極體。 【實施方式】 現參看圖式，描述本發明之若干例示性實施例。詞語 「例示性」在本文中用以意謂「充當一實例、個例或圖 例」。本文中描述為「例示性」之任一實施例未必解釋為 車父其他實施例而言為較佳或有利的。 在[實施方式]中揭示之實施例包括閘控二極體之實例、 製造該等閘控二極體之例示性方法，及相關電路及方法。 §亥等閘控二極體實例皆具有經阻隔以減小閘控二極體之電 容的至少一個淡摻雜汲極（LDD)植體。以此方式，閘控二 極體可用於效能對於負載電容可能敏感的電路及其他電路 應用中’但亦需要或要求閘控二極體的效能特性。閘控二極 體之益處包括（但不限於）快速接通時間及高傳導率。 147074.doc 201104757 。本文中所揭不之實施例中，閘控二極體包括一具有一 井品域的半導體基板。井11域包括-具有雜質的半導體材 。雜質。括經P型掺雜之雜質或經N型摻雜之雜質。在該 井區域上提供一絕緣層…閉電極形成於該絕緣層上方。 在Ά電極之相對側上將陽極區域及陰極區域植人於井區域 中視閘控—極體之設計而定，陽極區域或陰極區域具有 雜質β亥雜質具有與井區域之極性相反的極性，以形成 ΡΝ接面。在一實例中，對於含於ν型井區域内之二極 體，陽極區域具有—雜質，該雜質具有與來自_井區域 之雜質之極性相反的極性，以在陽極與井區域之間形成 Ν接面。在另一實例中，對於含於ρ型井區域内之二極體， 陰極區域具有一雜質，該雜質具有與來自ρ型井區域之雜 質之極性相反的極性，以在陰極與井區域之間形成ρ_Ν接 面。井區域具有在陽極區域、陰極區域或陽極區域及陰極 區域兩者之間經阻隔的至少一個Ldd植體。 在論述具有一或多個經阻隔之淡摻雜汲極（LDD)植體之 閘控二極體的特定實例之前，首先解釋具有UD植體之閘 控二極體的實例。圖3說明具有LDD植體的閘控二極體 32。閘控二極體32係基於金氧半導體（m〇S)設計，該設計 亦用於MOS場效電晶體（MOSFET)。閘控二極體32表明優 良之正向偏壓傳導率（例如，1〇〇 mS/pmx條帶長度）以及快 速接通時間（例如，大約一百（100)皮秒或更小）。如所說 明’閘控二極體32包括一基底半導體基板34，其用於沈積 其他材料以形成閘控二極體32。半導體基板34可由矽（Si) 147074.doc •10· 201104757 晶圓形成’此係因為矽晶圓相對廉價。或者，半導體基板 34 了由所要之任何其他半導體材料形成。所說明之半導體 基板34為N型閘控二極體，其具有在p型基板38中形成一通 道的P型井半導體材料36。然而，半導體基板34亦可為一 具有與N型閘控二極體贈送的電壓及操作之p型閘控二極 體，該P型閘控二極體具有一形成於P型基板中的N型井半 導體材料。其他變體可包括圖3之由深N型井包圍的二極體 結構’該深N型井植入於p型基板38中。 若干半導體子區域提供於p型井半導體材料36中該等 半導體子區域經修整以形成閘控二極體32的作用器件區 域。該等子區域包含一經]^+摻雜之區域4〇、一 植 體42、一經P+摻雜之區域44，及一P型LDD植體46。經N+ 摻雜之區域40形成陽極區域，且經p+摻雜之區域44形成陰 極區域。此等符號指示引入至p型井半導體材料％中的有 關雜質之類型及量。經N+摻雜之區域4〇可耦接至電導體， 以提供閘控二極體32的陰極（k)或源極（s)節點端子牦。經 P+摻雜之區域44亦可耦接至電導體，以提供閘控二極體32 的陽極（a)或汲極（D)節點端子5〇。閘控二極體32亦包括— 閘電極（G)52，其藉由絕緣層56而與p型井半導體材料刊、 陰極端子48及陽極端子50隔離。絕緣層兄通常稱為氧化物 層，但其他絕緣材料為可能的。絕緣層56可具有任何所要 厚度，但通常為極薄的，且作為實例可具有在大致Η埃 (A)與8〇 A之間的厚度。如所熟知的，閘電極52可由習知 傳導材料形成，但在此實例中以多晶矽（「p〇lysilie〇n」） 147074.doc 201104757 之形式來提供。 間隔物區域58A、58B亦由於置放於閘控二極體32上方 之殘餘絕緣材料而提供於間極.端子5 4的每一側上，該等間 隔物區域5 8 A、5 8B隨後經蝕刻。間隔物區域5 8 A、5 8B允 許N型植體40及P型植體44在間隔物形成之後形成於p型井 半導體材料36中。在間隔物沈積之前形成n型LDD植體42 及P型LDD植體46。在MOSFET中，包括LDD植體以增加 MOSFET之操作電壓及長期可靠性。具體言之，LDD植體 減小汲極之靜電橫截面，使得汲極與源極之間的靜電耦合 為小的。否則，當MOSFET之閘極至源極電位處於斷開狀 態時，汲極至源極之靜電耦合場將經由汲極誘發能障降低 (drain induced barrier l〇wering，DIBL)而使斷開狀態或洩 漏電流增加《由於MOSFET可為雙向的且因為製程約束， 因此將LDD應用至MOSFET閘極的兩側，因此，藉由在 MOSFET中提供N型植體42及P型LDD植體46，存在小很多 之靜電橫截面，使得源極或汲極端子處之電場展開，且並 不強大以便提供具有低洩漏電流之M〇SFET。又，經由 LDD植體之應用而在汲極處引起的電場減小改良熱電子可 靠性。由於閘控二極體32係基於MOSFE 丁設計及遮罩，因 此此等N型LDD植體42及P型LDD植體46包括於閘控二極體 32 中。 二— 因此，總之，閘控二極體32為如圖4中所說明之三端子 益件。該三個端子為陰極端子48、陽極端子5〇及閘極端子 54。P-N接面存在於p型井半導體材料％與經n+摻雜2區 147074.doc 12 201104757 域40之間。當一正電壓差存在於陽極端子50與陰極端子48 之間時’電流可相對容易地自陽極端子5〇流動至陰極端子 48 ’陰極端子48耦接至經N+摻雜之區域40。閘極端子54附 接至擴散區域之極性與井區域之極性相同的端子。在圖3 之狀況下，由於陽極端子50耦接至極性與p型井半導體材 料36相同的經P+摻雜之區域44 ,因此閘極端子54將耦接至 陽極端子50。實行該耦接配置以最小化陰極端子48上之電 容性負載’對於此極性的二極體而言，陰極端子48可麵接 至輸入/輸出（I/O)襯墊，而陽極耦接至第二電壓執或接 地。閘極在二極體作為保護元件之操作中無電力用途，且 用作製造載具（fabrication vehicle)以在無介入STI區域的情 況下分離經N+摻雜之區域40與經p +摻雜的區域44。 閘控二極體32具有若干個寄生電容來源，該等寄生電容 全部相加在一起以產生閘控二極體32的總電容◦如之前所 提及，對於圖3之二極體極性，耦接至1/〇之節點為陰極端 子48,其相對於耦接至陽極端子5〇之電源供應器應具有儘 可能小的電容。對於一般組態而言，閘極端子54係接至陽 極端子50。對於耦接至信號襯墊之陰極端子48，歸因於由 與N型LDD植體42重疊之閘電極52引起的周邊電容（下文中 稱為「閘極電容」）’第一寄生電容存在。此等材料之間 的絕緣層56充當介電質，以形成平行板電容。舉例而言， 跨越絕緣層56在閘電極52與N型LDD植體42之間提供在圖3 中標記為「c g-nldd」的寄生電容分量，閘電極52及^^型 LDD植體42與絕緣層56重疊。標記為r c g_Pldd」之寄生 147074.doc 13· 201104757 電容亦可類似地形成於閘電極52與P型LDD植體46之間， 閘電極52及P型LDD植體46與絕緣層56重疊。電容以與絕 緣層56之寬度成反比的方式增加》因為STI二極體不具有 閘電極，所以閘控二極體32之陰極與STI二極體之陰極相 比具有較大寄生電容。較高周邊電容等同於較高總體電 容，當閘控二極體32用於ESD保護電路中時，較高總體電 容可不利地影響受保護電路的效能。 標§己為「C NLDD-P-well」之另一寄生電容形成於N型 LDD植體42之側壁與p型井半導體材料36之間。絕緣層％ 與N型LDD植體42之間之P型井半導體材料36之較高摻雜濃 度亦促成此寄生電容的增加。此等因素皆促成閘控二極體 3 2之陰極之寄生電容的總體增加。 在特定模型化中已發現，閘控二極體32之總寄生電容的 大約三分之一來自閘極重疊電容。此係藉由實例說明於圖 5之模型化圊表60中。在圖5之模型化圖表6〇中，說明電容 之輸入閘極重疊分量占圖丨（使用兩個互補閘控二極體）之襯 墊輸入16之總輸入電容的百分比，其中該電容參考信號接 地12及10。陽極耦接至第二電壓軌或接地的閘控二極體^ 及陰極耦接至Vdd (1.2 V)的互補P+/N型井二極體係以相對 於電壓（V)的線62繪製。如先前所論述，閘極電容係因閘 電極52之存在而引起的電容。閘t極52可跨越絕緣層56 在閘控二極體32之其他材料（包括LDD植體42、46及其他 區域)之間引起周邊寄生電容圖所展示，在輸入電壓 ⑺範圍上，閘極電容之百分比（其為閘控二極體η之總 147074.doc -14- 201104757 電容的百分比)的範圍在大約百分之三十二(32%)與百分之 三十四（34%)之間。 在本文中所揭示之實施例令，藉由阻隔N型LDD植體、p 型LD_體或兩者與閉控二極體遮罩來減小問控二極體的 寄生電容”且隔意謂使LDD植體脫離閘控二極體η的形 成。此係藉由實例說明於圖6中。其中，展示例示性閘控 二極體32’ 1控二極體32,係提供於半導體封裝_，該半 導體封裝係整合至半導體晶粒中且可安裝於印刷電路板 (PCB)f β除在圖6tN型LDD植體42於閘控二極體中經 阻隔外閘控一極體3 2'具有與圖3之間控二極體3 2之特性 相同的特性1為__植體42不再存在，&以阻隔n 型LDD植體42減小本來形成於_ LDD植體42之側壁與？型 井半導體#料36之間的寄生電容（在圖3中展示為「c N⑽_ P_WeU」）。又，消除了閘電極52與N型LDD植體42重疊的 強電容。舉例而言，圖6中之閘控二極體32，的總寄生電容 可在「0.6 fF/μηιχ條帶長度」與「丨2 ^/μιηχ條帶長度」之 間。小的邊緣寄生電容仍將存在於閘電極52與經Ν+摻雜的 區域40之間，但由於經Ν+摻雜之區域4〇與閘電極“之間的 距離增加，該邊緣寄生電容將小很多。 在閘控二極體32'為MOSFET時，阻隔Ν型LDD植體42將 不會如先前在上文所描述因為存在於MOSFET中之熱電子 及沒極誘發能障降低的問題而不利地影響閘控二極體32,。 因為不存在表面傳導’所以此等問題不影響閘控二極體 32·。阻隔Ν型LDD植體42亦將不會不利地影響閘控二極體 147074.doc 15 201104757 32'的接通時間或傳導率。另外，在n型LDD植體42經阻隔 時’閘控二極體32,之故障電流位準可為較高的，因此增加 使用閘控二極體32,之ESD保護電路的電流分流效能。此情 形係因為閘控二極體32,之故障電流位準部分地視加熱效應 而定。若提供LDD植體，則歸因於本徵載流子濃度超過 LDD之摻雜位準所在的較低溫度，加熱效應對閘控二極體 32'具有較大影響。與ldd區域相比較，經重摻雜之N+區 域具有較高摻雜位準，且因此具有較高本徵溫度。在高於 本徵溫度之情況下’溫度係數自負值改變至大的正值，從 而引起失控之加熱。 圖7說明互補p型閘控二極體32,，的實例，該互補p型閘控 二極體321'藉由阻隔p型lDD植體而具有減小的寄生電容。 在此貫例中，阻隔圖3之閘控二極體32中與n型LDD植體42 相對的P型LDD植體46 »此情形說明於圖7之閘控二極體 32中。在此實例中，以N型井半導體材料64形成於P型基 板66中之形式來提供半導體基板34，'，從而形成P型閘控二 極體。P-N接面形成於N型井半導體材料64與經p+摻雜之 區域44之間。此情形與圖6中之N型閘控二極體32,相反。 經填入之淺溝槽隔離（STI)溝槽68A、68B亦分別包括在經 N+摻雜之區域4〇、陰極端子判與半導體基板34 "之間及經 P+摻雜之區域44、陽極端子5〇與半導體基板34，，之間。經 填入之STI溝槽68A、68B提供隔離，以防止或減小陰極端 子48及陽極端子5〇與半導體基板34"之間的電流洩漏。 在圖7之閘控二極體32，，中阻隔psLDD植體46，而使n型 147074.doc 201104757 LDD植體42未被阻隔。阻隔？型1^1)植體46減小本來在未 阻隔P型LDD植體46之情況下，形成於p型LDD植體46之側 壁與N型井半導體材料64之間的寄生電容。舉例而言，圖7 中之閘控二極體32，，的總寄生電容可在「〇6 ^/μιηχ條帶長 度」與「1.2 fF/μιηχ條帶長度」之間。一些寄生電容仍將 存在於閘電極52與經Ρ+摻雜之區域44之間，但歸因於經ρ+ 摻雜之區域40與閘電極52之間的距離增加，該寄生電容將 小很多。 此外’在閘控二極體32，，為（例如）M〇sfet時，阻隔ρ型 LDD植體46將不會如先前在上文所描述因賴電子及没極 誘發能障降低的問題而不利地影響閘控二極體32,，。因為 二極體依賴於基於塊體傳導介層孔接面（bulk c〇nducd〇n via junction)的載流子注入，而不依賴於閘極誘發表面反 轉層，且因為DIBL不影響茂漏電流，所以此等問題不影 響閘控二極體32"。阻隔p型LDD植體邨亦將不會不利地影 響閘控二極體32"的接通時間或傳導率。另外，在p型ldd 植體46經阻隔時，閘控二極體32,,之故障電流位準可為較 高的，因此增加使用閘控二極體32"之ESD保護電路的電 训·刀流效忐。此情形係因為閘控二極體32，，之故障電流位 準部分地視加熱效應而定。若提供乙]〇1)植體，則歸因於由 添加LDD植體所提供之本徵載流子濃度，加熱效應對間控 二極體32"具有較大影響。 士在圖7中之閘控一極體32，，中所說明，阻隔n型植 -為不必要的。然而，若在整個閘控二極體32"上進行 147074.doc -17· 201104757 阻隔而非試圖沿閘電極52之中間來分割遮蔽，則可良好地 促進對閘控二極體32，，的遮蔽。就此而言，圖8說明P型閘 控二極體32"，的又一實例。在此實例中，P型閘控二極體 32'"具有藉由阻隔n型LDD植體與P型LDD植體兩者而減小 的寄生電容《在此實例中，在閘控二極體32，，，中阻隔N型 LDD植體42與P型LDD植體46兩者。此情形說明於圖8中之 閘控二極體32’’’中。在此實例中，如在圖7之閘控二極體 32"中所提供，以n型井半導體材料64形成於P型基板66中 之形式來提供半導體基板34’" ’從而形成P型閘控二極 體。經填入之淺溝槽隔離（STI)溝槽68A、68B亦包括在經 N+摻雜之區域40、陰極端子48與半導體基板34…之間及經 P +摻雜之區域44、陽極端子50與半導體基板34"，之間。經 填入之STI溝槽68 A、68B提供隔離，以防止或減小陰極端 子48及陽極端子50與半導體基板34"，之間的電流洩漏。 在圖8之閘控二極體32"，中阻隔N型LDD植體42與P型 LDD植體46兩者。阻隔N型LDD植體42及P型LDD植體46減 小本來在未阻隔N型LDD植體42及P型LDD植體46之情況 下，形成於N型LDD植體42及P型LDD植體46之側壁與>^型 井半導體材料64之間的寄生電容。舉例而言，圖8中之閘 控二極體32…的總寄生電容可在「〇_6 fF/Vmx條帶長度」 與「1.2 fF/μηιχ條帶長度」之間。一些寄生電容仍將存在 於閘電極52與經N+摻雜之區域40及經p+摻雜之區域44之 間，但歸因於經N+摻雜之區域4〇及經p +摻雜之區域44與 閘電極52之間的距離增加，該寄生電容將小很多。另外， 147074.doc •18- 201104757 如先前在上文所描述，在閘控二極體32"，為（例W)m〇sfet 時’阻隔N型LDD植體42及P型LDD植體46將不會不利地影 響閘控二極體32’|·。 具有至少一個經阻隔之LDD植體的閘控二極體（諸如， 上文所論述之閘控二極體32、32,、32，，及32"，）可包括於任 何電路、積體電路或電路應用中。一實例包括一靜電放電 (ESD)保護電路^ ESD保護電路可類似於圖1中所說明之 ESD保護電路1 8而經組態，其中習知ESD突波二極體2〇、 22中的一或多者由具有至少一個經阻隔之ldd植體的一或 多個閘控二極體替換。在ESD保護電路中使用具有至少一 個經阻隔之LDD植體的一或多個閘控二極體歸因於閘控二 極體之快速接通時間而增強電壓箝制時間，以及由於閘控 二極體之高傳導率性質而增強使過量電流分流。又，使用 具有至少一個經阻隔之LDD植體的一或多個閘控二極體減 小ESD保護電路的貞載電容。此情形可允許制細保護 電路保護效能對於負載電容敏感的電路，同時仍達成閘控 二極體的ESD特性。減小負載電容在適當（包括以所要效 能、速度及/或敏感性）操作之受保護電路中可為重要的。 具有至少一個經阻隔之LDD植體的閘控二極體可用於任 何器件或電路中，且可特別用於效能對於負載電容可能敏 感的電路。在匕等器件及電路之實侈包括高速差動輸入/輸 出電路及射頻（RF)電路，射頻（RF)電路包括（但不限於）低 雜訊放大器（LNA)。圖9說明作為用於提供一保護電路之一 可能器件及/或積體電路的收發器7〇，該保護電路使用具 147074.doc -19· 201104757 有至少一個經阻隔之LDD植體的一或多個閘控二極體保護 低雜訊放大器（LNA)。用於保護電路中之該（該等）閘控二 極體可為先前所描述之閘控二極體32，、32，，、32，，'中的一 或多者。收發器70可以絕緣底半導體（semiconduct〇r_〇n_ insulator，SOI)及/或SOC技術來實施。收發器70可用於任 何器件中，該器件包括（作為實例）行動電話或終端機、個 人數位助理（PDA)、無線區域網路（LAN)或其他類似無線 通信器件。 如圖9中所說明，收發器70可包括一接收器前端72、一 射頻（RF)傳輸器74、一天線76、一開關78及一處理器8〇。 接收盗前端72接收來自一或多個遠端傳輸器（未圖示）之承 載射頻信號的資訊。低雜訊放大器（LNA)82放大由天線76 接收到的傳入信號。將保護電路84添加至接收器前端72， 以保護LNA 82及下游電路不受突波（包括ESD突波）的影 響。然而，將負載電容添加至LNA 82可降低[ΝΑ 82的敏 感性。就此而言，保護電路84可併有具有至少一個經阻隔 之LDD植體的至少一個閘控二極體。以此方式，經由在保 凌電路84中使用閘控二極體來減小來自保護電路84之所添 加負載電容，同時仍提供優良的接通時間及高傳導率處置 能力。用於ESD保護電路84中之閘控二極體可為先前所描 述之閘控二極體32,、32，’、321，，中的一或多者。另外，保 蒦電路84可為ESD保護電路，且可類似於圖j甲所說明之 ESD保濩配置及ESD保護電路18或任何其他所要配置或電 路而經組態。舉例而言，可提供閘控二極體以箝制過量正 147074.doc 201104757 電壓、過量負電壓或兩者’從而使由此產生之過量電流分 流。 離開LNA 82之經放大的信號可提供至rf子系統86，可 接著使用類比數位（A/D)轉換器88數位化該經放大之信 號。經數位化之信號可自類比數位（A/D)轉換器88提供至 非同步/同步積體電路（ASIC)或其他處理器80，以根據應 用程式進行處理。舉例而言，ASIC或處理器8〇可處理經數 位化之所接收信號，以提取在所接收信號中傳送的資訊或 二貝料位元。此處理可包括解調變、解碼及錯誤校正操作。 ASIC或處理器80可以一或多個數位信號處理器（DSp)來實 施。 在傳輸侧，ASIC或處理器8〇可接收由於所接收之信號 而產生之經數位化的資料，ASIC或處理器8〇編碼經數位化 之資料以供傳輸。在編碼資料之後，ASIC或處理器8〇將經 編碼之資料輸出至RF傳輸器74。調變器9〇接收來自ASIC 或處理器80之資料，且在此實施例中，根據一或多個調變 方案操作以將—經調變之信號提供至功率放大器電路92。 功率放大器92將來自調變器90之經調變的信號放大至適於 自天線76傳輸的位準。 圖1〇說明可用作圖9之收發器70中之保護電路84的例示 性ESD保護電路。圖說明經組態以保護LNA 82之輸入的 保護電路84。如所說明，保護電路84包括耦接至接合襯墊 96的兩個閘控二極體93、94，及耦接至1〇〇及Vss 1〇2的 暫態箝制部分98。閘控二極體93、94各自具有至少一個經 147074.doc -21 - 201104757 阻隔的LDD植體，且作為實例，可根據上文所論述之閘控 二極體中的任一者來提供。受保護iLNA 82包括放大1^通 道型薄氧化物場效電晶體（NFET)104，及在NFET 1〇4之源 極（S)與Vss 102之間的源極退化電感器〗〇6。若在cdm事件 期間一正電流相對於Vss 1 〇2注入至接合襯塾96中，則電流 將自接合襯墊96流經閘控二極體93至Vdd 1 00，且接著自 vdd 1〇〇流經暫態箝制部分98至乂55 10^暫態箝制部分98 包含自Vdd 1〇〇耦接至vss 102之NFET 108;電阻器電容器 (RC)暫態偵測器或rC電路110 ;及一反相器112，其充當 RC暫態偵測器110與NFET 108之間的緩衝器。在高速暫態 電壓呈現為Vdd 100至Vss 102期間，RC暫態偵測器11〇使 NFET 108接通’藉此允許NFET 108在具有小電壓降的情 況下使大電流分流。在正常操作期間，藉由RC暫態偵測 器110使NFET 108偏壓截止。 作為一實例，接合襯墊96與Vss 1〇2之間的電壓降應足夠 低，以使NFET 104上之閘極（G)至源極（S)電壓在1奈秒（ns) 的脈衝寬度内低於閘極氧化物斷裂電壓（rupture voltage)， 1奈秒大致對應於一 CDM脈衝寬度。對於2〇 A厚之氧化物 而言，NFET 104之閘極（G)至源極⑻的斷裂電壓在1 ns脈 衝的情況下為大致6.9 V。源極退化電感器W6對NFET 104 上之閘極（G)至源極（S)的電壓降影響較小。因此，對於正 襯墊至Vss 102之電流’閘控二極體93及NFET 108在CDM 電流幅度為若干安培的情況下具有小於6.9 V的累積電壓 降。 H7074.doc •22· 201104757 根據本文中所揭示之實施例的閘控二極體或積體電路可 包括或整合於半導體晶粒中，及/或任何其他器件（包括電 子器件）中。此類器件之實例包括（但不限於）一機上盒、一 娛樂單元、一導航器件、一通信器件、一個人數位助理 (PDA)、一固定位置資料單元 '一行動位置資料單元一 行動電話、一蜂巢式電話、一電腦、一可攜式電腦、一桌 上型電腦、一監視器、一電腦監視器、一電視機、一調諧 器、一無線電、一衛星無線電、一音樂播放器、一數位音 樂播放器、一可攜式音樂播放器、一視訊播放器、一數位 視訊播放器、一數位影音光碟（DVD)播放器，及一可攜式 數位視訊播放器。 可對以上閘控二極體結構進行各種修改，詳言之，視所 使用之各種層的組合物及触刻而定，可改變置放或沈積某 些層所依據之次序。亦應認識到，以上實施例中之閘控二 極體中之層的次序及形成彼等層的材料僅為例示性的。此 外，雖然在所說明之實施例中將支撐結構大體上描繪為圓 形或具有圓形轉角，但在替代實施例中支撐結構可具有不 同形狀。此外，在一些實施例中，可置放或沈積並處理其 他層（未圖示）以形成閘控二極體器件之部分或形成基板上 的其他結構。在其他實施例中，如對於熟習此項技術者將 為已知的，此等層可使用替代性沈積、圖案化以及蝕刻材 料及製程來形成，可以不同次序來置放或沈積，或由不同 材料纟且成。 亦請注意，本文中在例示性實施例中之任一者中描述的 147074.doc •23- 201104757 細作任務經描述以提供實例及論述。所描述之操作可 同於所朗之财的❹⑽财來執行。此外，在單 操作任務中描述之操作可實際上在若干不同任務中來執 订另外，可組合在例示性實施例中所論述之一或多個操 作任務。-般熟習此項技術者亦應理解，可使用多種不同 技藝及技術中之任一者來表示資訊及信號。舉例而言可 藉由電壓、電流、電磁波、磁場或磁粒子、光場或光粒子 或其任何組合來表示可貫穿以上描述而參考之資料指 令、命令、資訊、信號、位元、符號及碼片。 提供本發明之先前描述以使得任何熟習此項技術者能夠 製造或使用本發明。對於熟習此項技術者而言，對本發明 之各種修改將易為顯而易見的，且可在不偏離本發明之精 神或範疇的情況下將本文中所界定之一般原理應用於其他 盔體。因此，本發明不意欲受限於本文中所描述之實例及 设计’而是符合與本文中所揭示之原理及新穎特徵一致的 最廣泛範疇。 【圖式簡單說明】 圖1為先前技術中之習知靜電放電（ESD)保護電路的實 例； 圖2為一對輸入二極體之間的輸入電容之例示性比較的 圖表’該對輸入二極體體現為閘控二極體及體現為淺溝槽 隔離（STI)二極體； 圖3為包括淡掺雜没極（LDD)植體之例示性閘控二極體； 圖4為表示圖3之閘控二極體的例示性圖解符號； 147074.doc • 24· 201104757 圖5為閘控二極體之圖3之閘極與陰極重疊電容作為閑控 二極體之總電容之百分比的例示性比較之圖表； 圖6為一例示性閘控二極體，其阻隔n型LDD植體以減小 N+P型井閘控二極體之電容； 圖7為一閘控二極體之替代例示性實施例，該閘控二極 體阻隔P型LDD植體以減小P+N型井閘控二極體之電容； 圖8為一閘控二極體之替代例示性實施例，該閘控二極 體阻隔N型LDD植體與P型LDD植體兩者以減小閘控二極體 之電容； 圖9為包括一保護電路之例示性射頻（RF)收發器，該保 護電路具有阻隔至少一個LDD植體的至少一個閘控二極 體；及 圖1 〇為藉由一 ESD保護電路保護之例示性低雜訊放大 器’該ESD保護電路使用具有至少一個經阻隔之ldd植體 的閘控二極體。 【主要元件符號說明】 10 電壓轨（vdd)/信號接地 12 接地軌（GND)/信號接地 14 受保護電路 16 信號接腳 18 習知ESD保護電路 20 正ESD突波二極體 22 負ESD突波二極體 24 節點 147074.doc •25· 201104757 26 模型化圖表 28 閘控二極體對 30 STI二極體對 32 閘控二極體 32’ 閘控二極體 32" 互補P型閘控二極體 32'" P型閘控二極體 34 基底半導體基板 34" 半導體基板 34’" 半導體基板 36 P型井半導體材料 38 P型基板 40 經N+摻雜之區域 42 N型LDD植體 44 經P+摻雜之區域 46 P型LDD植體 48 陰極（k)或源極（S)節點端子 50 陽極（a)或汲極（D)節點端子 52 閘電極（G) 54 閘極端子 56 絕緣層 58A 間隔物區域 58B 間隔物區域 60 模型化圖表 147074.doc -26- 201104757 62 線 64 N型井半導體材料 66 P型基板 68A 淺溝槽隔離（STI)溝槽 68B 淺溝槽隔離（STI)溝槽 70 收發器 72 接收器前端 74 射頻（RF)傳輸器 76 天線 78 開關 80 處理器 82 低雜訊放大器（LNA) 84 保護電路 86 RF子系統 88 類比數位（A/D)轉換器 90 調變器 92 功率放大器電路 93 閘控二極體 94 閘控二極體 96 接合襯墊 98 暫態箝制部分 100 軌電壓（Vdd) 102 Vss 104 放大N通道型薄氧化物場效電晶體（NFET) 147074.doc •27· 201104757 106 源極退化電感器 108 N通道場效電晶體（NFET) 110 電阻器電容器（RC)暫態偵測器或RC電路 112 反相器 a 陽極 G 閘極 K 陰極 S 源極 147074.doc -28 -201104757 VI. Description of the Invention: [Technical Field] The technology of the present application relates to a gate-controlled diode and its use in a circuit, including a protection circuit, an electrostatic discharge (ESD) protection circuit 'And high speed or switching circuits. [Prior Art] Electrostatic discharge (ESD) is a major reliability problem in an integrated circuit (IC). ESD is a voltage transient surge (positive or negative) that induces large currents in the circuit. To protect the circuit from ESD surges, the protection scheme attempts to provide a discharge path for both positive ESD and negative ESD surges. Conventional diodes can be used in ESD protection circuits to clamp the voltages of positive and negative ESD surges, thereby shunting the current and preventing excessive voltage from being applied to the protected circuit. In this regard, Figure 1 illustrates a conventional ESD protection circuit. As illustrated in Figure 7, a voltage rail (Vdd) and a ground rail (Gnd) 12 are provided to power the protected circuit 14. Protected circuit 14 can be any type of circuit and is provided in any desired form. In this example, a terminal in the form of signal pin 16 provides a signal path to protected circuit 14 for providing information and/or control to protected circuit 14. For example, the protected circuit 14 can be included in 1 (where, the "is 5 tiger pin 16 is an externally available pin on the IC chip. The conventional ESD protection circuit 18 can be coupled to a voltage switch 1 Between the grounding rails 2 to protect the protected circuit 14 from ESD surges. The exemplary ESD protection circuit 18 in Figure 5 includes two conventional diodes: a positive ESD surge diode 20 and A negative ESD surge diode 22. The positive ESD surge diode 20 and the negative ESD surge diode 22 are coupled in series. The positive ESD surge diode 147074. Doc 201104757 20 clamps the positive voltage on signal pin 16 to a diode drop above the voltage. The negative ESD surge diode 22 clamps the negative voltage on signal pin 16 to a lower voltage drop than ground diode 12. The cathode (k) of the positive ESD surge diode 20 is coupled to the voltage transistor. The anode (a) of the positive ESD diode 20 is coupled to the signal pin 16 at a node 24 on the signal path between the signal pin 16 and the protected circuit 14. The cathode (k) of the negative ESD surge diode 22 is also coupled to node 24 on the signal path from signal pin 16 to protected circuit 14. The anode (a) of the negative ESD surge diode 22 is coupled to the ground handle 12. For a positive ESD surge on signal pin 16, positive ESD surge diode 20 will become forward biased and clamp the voltage on signal pin 6 to the diode above electrical rail 10 The voltage drop ' thereby protects the protected circuit 14. The energy from this ESD surge will be conducted through the positive ESD surge one in the forward bias mode and dispersed into the voltage rail 1〇. A suitable ESD protection structure can be applied (not shown) to the voltage rail 1〇 to eventually dissipate the positive ESD surge to the ground rail 12. For the negative ESD glitch on signal pin 16, similarly, the power rush is used. The negative ESD surge on signal pin i 6 will place negative ESD surge diode 22 in forward bias mode, thus providing a low impedance path relative to protected circuit 14. The energy from the negative ESD surge will be dissipated into the grounding stub 12 . Providing ESD protection in the SOC technology has become increasingly important as circuits are being provided in a crystalline system (s〇c) configuration due to the more germanium transistor count. The S0C technology can use field effect transistors that provide relatively thin oxide gate dielectrics (FETs such as relatively thin dielectrics are susceptible to destructive breakdown and damage due to excessive voltage from (4) surge events. In addition, 147074. Doc 201104757 Conventional diodes (such as the ESD surge diodes 20, 22 provided in Figure 1) do not provide sufficient conduction for ESD protection in SOC technology. To address these shortcomings of ESD protection (and in detail, for s〇c technology), shallow trench isolation (sti) diodes have been provided in ESD protection circuits. Gate-controlled diodes are also being used in ESD protection circuits. It has been shown that the use of gated diodes due to the transient path of gated one-pole carriers has excellent conductivity per unit length and turn-on speed. The turn-on speed of the ESD protection circuit is important to comply with the Charged Device Modeling (CDm) specification, where a large amount of current (eg, several amps) can flow during a very small period of time (eg, less than one nanosecond) during an ESD event. Over. However, even though gated diodes have these advantages, STI diodes are still mainly used in ESD protection circuits for high speed circuits. The gated diode can be less effective in an unacceptable manner. The gated diode has a larger peripheral capacitance per unit of diffusion or active length compared to the STI diode. This situation is illustrated by way of example in the modeled diagram 26 of Figure 2, in which the input capacitance (C) and STI diode pairs corresponding to the gated diode pair 28 of Figure j are plotted against the input voltage (v). 3〇 input capacitance (C). This example assumes a 65 nanometer (nm) process. As shown in the figure, the given voltage (V), length and width of the diode (approximately 8 〇 micron (μηι) and 0. The input capacitance (c) of the 45 μm) gate-controlled diode pair 28 normalized to the maximum capacitance of the STi diode pair 30 is higher than the input capacitance (c) of the STI diode pair. For example, at rail voltage (Vdd), the normalized capacitance of the gated diode pair 28 (〇 is close to is, and the normalized capacitance (C) of the STI diode pair 3 大致 is approximately ι·〇. In this example, this situation is equivalent to a gated diode pair 28 having approximately eighty percent (8%) capacitance 147074 compared to the STI diode pair 30. Doc 201104757 added. When the gated diode is added to the protected circuit, the increased peripheral capacitance of the control diode increases the load capacitance. Increasing the load capacitance can negatively affect the protected circuit. For example, an increased load capacitance can reduce the switching time and frequency performance of the protected circuit because in the R-C circuit configuration, the charging time will be increased due to the ESD protection circuit being lightly connected to the protected circuit. In addition, the increased capacitance provided by the insertion of the ESD protection circuit can reduce the sensitivity of radio frequency (RF) components such as low noise amplifiers (LNAs). However, the use of STI-poles with lower valleys in ESD protection circuits also has trade-offs (trade ff) compared to the use of gated diodes. The use of STI diodes in esd protection circuits can result in low CDM voltage tolerance for protected circuits for both positive and negative surges' and is especially protected for thin oxide gate oxide dielectric devices. In terms of circuits and related processes, such thin oxide gate oxide dielectric devices are coupled to pads that can be found in large SOC wafers. To maintain performance, wafer manufacturers and consumers must accept lower CDM voltage tolerances due to the use of STI diodes in ESD protection circuits, which results in greater exposure and failure associated with ESD. Accordingly, it is desirable to provide an ESD protection circuit that exhibits excellent conductivity and turn-on time as well as low capacitance so as not to adversely affect the performance of the protected circuit. SUMMARY OF THE INVENTION The embodiments disclosed in [Embodiment] include an example of a gated diode, an exemplary method of fabricating the gated diode, and related circuits and methods. Examples of these gated diodes are blocked to reduce the gated diode 147074. Doc 201104757 At least one light-changing of the body's electric order: 3⁄4 pole (LDD) implants. In this way, the function of the gate can be used for circuits and other circuits that may be sensitive to load capacitance, but it also requires or requires the effectiveness of a gated diode. $ limited to) fast turn-on time and high conductivity. In an embodiment not disclosed herein, the gated diode includes a semiconductor substrate having a well region. The well region includes a semiconductor material having - impurities. Impurities include - impurities doped with ytterbium type or impurities that are replaced by yttrium. An insulating layer is provided on the area of the 3 wells. A gate electrode is formed over the insulating layer. An anode region and a cathode region are implanted in the beta well region on opposite sides of the gate electrode. Depending on the design of the gated diode, the anode region or the cathode region has an impurity which has a polarity opposite to that of the well region to form a ρ_ junction. In one example, for one of the diodes contained in the - Ν type well region, the anode region has an impurity 'the impurity has a polarity opposite to the polarity of the impurity f from the _ well region' at the anode A p_N junction is formed between the well regions. In another example, 'for a diode contained in a -P type well region, the cathode region has an impurity having a polarity opposite to the polarity of the impurity from the p-type well region to be at the cathode A p_N junction is formed between the well region. The gated region having at least one implanted at least one hindered LDD implant that is blocked between the anode region, the cathode region, or both the anode region and the cathode region can be included in any In circuit, integrated circuit or circuit applications... examples include an electrostatic 147074. Doc 201104757 Discharge (ESD) protection circuit. An ESD protection circuit is enhanced by the fast turn-on time and high conductivity characteristics of the gated diode. However, if the ESD protection circuit uses one or more of the gated diodes having at least one blocked LDD implant, the capacitance of the ESD protection circuit is also reduced. This situation allows the ESD protection circuit to be used to protect circuits that are sensitive to load capacitance while still achieving these ESD characteristics of the gated diode. Otherwise, it is not possible to use a gated diode in the ESD protection circuit without affecting the performance of the protected circuit in an unacceptable manner. Other examples of protected circuits include high speed differential input/output circuits and radio frequency (RF) circuits including, but not limited to, low noise amplifiers (LNAs) whose performance may be on the load The capacitance is sensitive and thus can benefit from the gated diodes disclosed herein. [Embodiment] Several illustrative embodiments of the invention are described with reference to the drawings. The word "exemplary" is used herein to mean "serving as an instance, instance, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous to other embodiments of the parent. The embodiments disclosed in [Embodiment] include examples of gated diodes, exemplary methods of fabricating such gated diodes, and related circuits and methods. § HI and other gated diode examples have at least one lightly doped drain (LDD) implant that is blocked to reduce the capacitance of the gated diode. In this way, the gated diode can be used in circuits and other circuit applications where performance may be sensitive to load capacitance, but the performance characteristics of the gated diode are also required or required. Benefits of gated diodes include, but are not limited to, fast turn-on time and high conductivity. 147074. Doc 201104757. In the embodiments disclosed herein, the gated diode includes a semiconductor substrate having a well domain. The well 11 domain includes a semiconductor material having impurities. Impurities. P-type doped impurities or N-doped impurities are included. An insulating layer is provided on the well region... a closed electrode is formed over the insulating layer. On the opposite side of the ytterbium electrode, the anode region and the cathode region are implanted in the well region depending on the design of the gate-electrode body, and the anode region or the cathode region has the opposite polarity of the impurity of the well region. Forming a splicing surface. In one example, for a diode contained in a zone of the ν-type well, the anode region has an impurity having a polarity opposite to that of the impurity from the well region to form a 在 between the anode and the well region. Junction. In another example, for a diode contained in a p-type well region, the cathode region has an impurity having a polarity opposite to that of the impurity from the p-type well region to be between the cathode and the well region Form a ρ_Ν junction. The well region has at least one Ldd implant that is blocked between the anode region, the cathode region, or both the anode region and the cathode region. Before discussing a specific example of a gated diode having one or more barrier lightly doped drain (LDD) implants, an example of a gated diode having a UD implant is first explained. Figure 3 illustrates a gated diode 32 having an LDD implant. The gated diode 32 is based on a metal oxide semiconductor (m〇S) design, which is also used in MOS field effect transistors (MOSFETs). The gated diode 32 indicates excellent forward bias conductance (e.g., 1 〇〇 mS/pmx strip length) and fast turn-on time (e.g., approximately one hundred (100) picoseconds or less). As indicated, the gated diode 32 includes a base semiconductor substrate 34 for depositing other materials to form the gated diode 32. The semiconductor substrate 34 can be made of bismuth (Si) 147074. Doc •10· 201104757 Wafer formation 'This is because 矽 wafers are relatively inexpensive. Alternatively, the semiconductor substrate 34 is formed of any other semiconductor material as desired. The illustrated semiconductor substrate 34 is an N-type gated diode having a P-type well semiconductor material 36 that forms a via in the p-type substrate 38. However, the semiconductor substrate 34 can also be a p-type gated diode having a voltage and operation given by the N-type gated diode having a N formed in the P-type substrate. Well-well semiconductor materials. Other variations may include the diode structure of Figure 3 surrounded by a deep N-well, which is implanted in a p-type substrate 38. A plurality of semiconductor sub-regions are provided in the p-type well semiconductor material 36 that are trimmed to form the active device region of the gated diode 32. The sub-regions include a region + doped region 4, an implant 42, a P+ doped region 44, and a P-type LDD implant 46. The N+ doped region 40 forms an anode region and the p+ doped region 44 forms a cathode region. These symbols indicate the type and amount of impurities involved in the % of p-type well semiconductor material. The N+ doped region 4〇 can be coupled to an electrical conductor to provide a cathode (k) or source (s) node terminal 闸 of the gated diode 32. The P+ doped region 44 can also be coupled to an electrical conductor to provide an anode (a) or drain (D) node terminal 5〇 of the gated diode 32. The gated diode 32 also includes a gate electrode (G) 52 that is isolated from the p-well semiconductor material material, the cathode terminal 48, and the anode terminal 50 by an insulating layer 56. Insulators are often referred to as oxide layers, but other insulating materials are possible. The insulating layer 56 can have any desired thickness, but is typically very thin, and can have a thickness between approximately Η (A) and 8 〇 A as an example. As is well known, the gate electrode 52 can be formed of a conventional conductive material, but in this example polycrystalline germanium ("p〇lysilie〇n") 147074. The form of doc 201104757 is provided. The spacer regions 58A, 58B are also provided to the interpole due to residual insulating material placed over the gated diode 32. On each side of terminal 504, the spacer regions 5 8 A, 5 8B are subsequently etched. The spacer regions 5 8 A, 5 8B allow the N-type implant 40 and the P-type implant 44 to be formed in the p-type well semiconductor material 36 after spacer formation. An n-type LDD implant 42 and a P-type LDD implant 46 are formed prior to spacer deposition. In MOSFETs, LDD implants are included to increase the operating voltage and long-term reliability of the MOSFET. Specifically, the LDD implant reduces the electrostatic cross section of the bungee such that the electrostatic coupling between the drain and the source is small. Otherwise, when the gate-to-source potential of the MOSFET is off, the drain-to-source electrostatic coupling field will be disconnected via drain induced barrier l〇wering (DIBL) or Increased Leakage Current "Because the MOSFET can be bidirectional and because of process constraints, LDD is applied to both sides of the MOSFET gate. Therefore, there are small N-type implants 42 and P-type LDD implants 46 provided in the MOSFET. Many electrostatic cross sections cause the electric field at the source or 汲 terminal to expand and are not strong enough to provide an M〇SFET with low leakage current. Moreover, the electric field induced at the drain by the application of the LDD implant reduces the improved thermoelectronic reliability. Since the gated diode 32 is based on a MOSFE design and a mask, such N-type LDD implants 42 and P-type LDD implants 46 are included in the gated diode 32. Secondly, in summary, the gated diode 32 is a three terminal benefit as illustrated in FIG. The three terminals are a cathode terminal 48, an anode terminal 5A, and a gate terminal 54. The P-N junction exists in the p-type well semiconductor material % and the n+ doped 2 region 147074. Doc 12 201104757 Between domains 40. When a positive voltage difference exists between the anode terminal 50 and the cathode terminal 48, the current can flow relatively easily from the anode terminal 5 to the cathode terminal 48. The cathode terminal 48 is coupled to the N+ doped region 40. The gate terminal 54 is attached to a terminal having the same polarity as that of the well region. In the situation of Figure 3, the gate terminal 54 will be coupled to the anode terminal 50 since the anode terminal 50 is coupled to the same P+ doped region 44 of the same polarity as the p-well semiconductor material 36. The coupling configuration is implemented to minimize the capacitive load on the cathode terminal 48. For a diode of this polarity, the cathode terminal 48 can be interfaced to an input/output (I/O) pad and the anode coupled to The second voltage is applied or grounded. The gate has no power use in the operation of the diode as a protective element and is used as a fabrication vehicle to separate the N+ doped region 40 and the p+ doped region without intervening STI regions. Area 44. The gated diode 32 has a plurality of sources of parasitic capacitance that are all added together to produce the total capacitance of the gated diode 32. As previously mentioned, for the polarity of the diode of Figure 3, the coupling The node connected to 1/〇 is the cathode terminal 48, which should have as little capacitance as possible with respect to the power supply coupled to the anode terminal 5〇. For the general configuration, the gate terminal 54 is coupled to the anode terminal 50. For the cathode terminal 48 coupled to the signal pad, the first parasitic capacitance exists due to the peripheral capacitance (hereinafter referred to as "gate capacitance") caused by the gate electrode 52 overlapping with the N-type LDD implant 42. The insulating layer 56 between the materials acts as a dielectric to form a parallel plate capacitor. For example, a parasitic capacitance component labeled "c g-nldd" in FIG. 3 is provided between the gate electrode 52 and the N-type LDD implant 42 across the insulating layer 56, the gate electrode 52 and the LDD implant 42 It overlaps with the insulating layer 56. Parasitic marked as r c g_Pldd 147074. Doc 13· 201104757 A capacitor can also be similarly formed between the gate electrode 52 and the P-type LDD implant 46, and the gate electrode 52 and the P-type LDD implant 46 overlap the insulating layer 56. The capacitance is increased in inverse proportion to the width of the insulating layer 56. Since the STI diode does not have a gate electrode, the cathode of the gated diode 32 has a larger parasitic capacitance than the cathode of the STI diode. The higher peripheral capacitance is equivalent to the higher overall capacitance, and when the gated diode 32 is used in an ESD protection circuit, the higher overall capacitance can adversely affect the performance of the protected circuit. Another parasitic capacitance of the "C NLDD-P-well" is formed between the sidewall of the N-type LDD implant 42 and the p-type well semiconductor material 36. The higher doping concentration of the P-type well semiconductor material 36 between the insulating layer % and the N-type LDD implant 42 also contributes to an increase in this parasitic capacitance. These factors contribute to the overall increase in the parasitic capacitance of the cathode of the gated diode 32. It has been found in a particular modelling that approximately one-third of the total parasitic capacitance of the gated diode 32 is derived from the gate overlap capacitance. This is illustrated by way of example in the modeled table 60 of FIG. In the modeled diagram 6〇 of Figure 5, the percentage of the total input capacitance of the pad input 16 of the input gate of the capacitor (using two complementary gated diodes) is illustrated, where the capacitance reference signal Ground 12 and 10. The anode is coupled to the second voltage rail or the grounded gate diode and the cathode is coupled to Vdd (1. The complementary P+/N well dipole system of 2 V) is plotted as line 62 with respect to voltage (V). As previously discussed, the gate capacitance is the capacitance due to the presence of the gate electrode 52. The gate t-pole 52 can across the insulating layer 56 to cause a peripheral parasitic capacitance diagram between other materials of the gated diode 32 (including the LDD implants 42, 46 and other regions), in the range of the input voltage (7), the gate The percentage of capacitance (which is the total 147074 of the gated diode η. Doc -14- 201104757 The percentage of capacitance) ranges between approximately 32% (32%) and 34% (34%). Embodiments disclosed herein reduce the parasitic capacitance of the control diode by blocking N-type LDD implants, p-type LD_ bodies, or both with closed-loop diode masks. The LDD implant is removed from the formation of the gated diode η. This is illustrated by way of example in Figure 6. The exemplary gated diode 32' 1 control diode 32 is shown in a semiconductor package. _, the semiconductor package is integrated into the semiconductor die and can be mounted on a printed circuit board (PCB) f β except that the Lt implant 42 of FIG. 6 is blocked in the gated diode and the gate 1 2 is blocked. 'The characteristic 1 having the same characteristics as the control diode 3 2 between FIG. 3 is that the implant 42 is no longer present, and the reduction of the n-type LDD implant 42 is originally formed in the _LDD implant 42. The parasitic capacitance between the sidewall and the well-type semiconductor #36 (shown as "c N(10)_ P_WeU" in Figure 3). Further, the strong capacitance in which the gate electrode 52 overlaps with the N-type LDD implant 42 is eliminated. For example, the total parasitic capacitance of the gated diode 32 in Figure 6 can be "0. 6 fF/μηιχ strip length" and "丨2 ^/μιη strip length". A small edge parasitic capacitance will still be present between the gate electrode 52 and the germanium + doped region 40, but since the distance between the germanium + doped region 4 〇 and the gate electrode increases, the edge parasitic capacitance will When the gated diode 32' is a MOSFET, the barrier LD-type LDD implant 42 will not be as described above because of the problem of thermal electrons and immersion-induced energy barrier reduction in the MOSFET. Favorably affects the gated diode 32. Because there is no surface conduction', these problems do not affect the gated diode 32. The barrier type LDD implant 42 will not adversely affect the gated diode 147074. Doc 15 201104757 32' turn-on time or conductivity. In addition, when the n-type LDD implant 42 is blocked, the fault current level of the gate-controlled diode 32 can be high, thus increasing the current shunting efficiency of the ESD protection circuit using the gated diode 32. This situation is due to the fact that the fault current level of the gated diode 32 is partially dependent on the heating effect. If an LDD implant is provided, the heating effect has a greater effect on the gated diode 32' due to the lower temperature at which the intrinsic carrier concentration exceeds the doping level of LDD. The heavily doped N+ region has a higher doping level than the ldd region and therefore has a higher intrinsic temperature. At temperatures above the intrinsic temperature, the temperature coefficient changes from a negative value to a large positive value, causing uncontrolled heating. Figure 7 illustrates an example of a complementary p-type gated diode 32' having reduced parasitic capacitance by blocking p-type lDD implants. In this example, the P-type LDD implant 46 in the gated diode 32 of Figure 3 opposite the n-type LDD implant 42 is shown in this example in the gated diode 32 of Figure 7. In this example, the semiconductor substrate 34,' is provided in the form of an N-type well semiconductor material 64 formed in the P-type substrate 66, thereby forming a P-type gated diode. A P-N junction is formed between the N-well semiconductor material 64 and the p+ doped region 44. This situation is the opposite of the N-type gated diode 32 of FIG. Filled shallow trench isolation (STI) trenches 68A, 68B are also included in the N+ doped region 4, the cathode terminal between the semiconductor substrate 34 " and the P+ doped region 44, anode The terminal 5 is connected to the semiconductor substrate 34, . The filled STI trenches 68A, 68B provide isolation to prevent or reduce current leakage between the cathode terminal 48 and the anode terminal 5 and the semiconductor substrate 34". In the gated diode 32 of Figure 7, the psLDD implant 46 is blocked, and the n-type 147074 is made. Doc 201104757 LDD implant 42 is not blocked. Blocking? The type 1^1) implant 46 reduces the parasitic capacitance formed between the side wall of the p-type LDD implant 46 and the N-type well semiconductor material 64 without the P-type LDD implant 46 being blocked. For example, the total parasitic capacitance of the gated diode 32 in Figure 7 can be "〇6^/μιηχ strip length" and "1. 2 fF / μιη χ strip length". Some parasitic capacitance will still be present between the gate electrode 52 and the germanium + doped region 44, but due to the increased distance between the ρ+ doped region 40 and the gate electrode 52, the parasitic capacitance will be much smaller. . In addition, when the gated diode 32, for example, M〇sfet, the barrier to the p-type LDD implant 46 will not be as described above because of the problem of reduced electron and immersion induced energy barriers. The gate-controlled diode 32 is adversely affected. Because the diode is dependent on the carrier injection based on the bulk conduction via, it does not depend on the gate induced surface inversion layer, and because DIBL does not affect the leakage. Current, so these issues do not affect the gated diode 32". Blocking the p-type LDD implant village will also not adversely affect the turn-on time or conductivity of the gated diode 32". In addition, when the p-type ldd implant 46 is blocked, the gate current of the gated diode 32 can be higher, so the electric training of the ESD protection circuit using the gated diode 32" The knife is fluent. This situation is due to the fact that the fault current level of the gated diode 32 is partially dependent on the heating effect. If B) 〇 1) implants are provided, the heating effect has a greater effect on the inter-controlled diode 32" due to the intrinsic carrier concentration provided by the addition of LDD implants. In the gated body 32 of Figure 7, it is shown that blocking n-type implants - is unnecessary. However, if the entire gated diode 32" is carried out 147074. Doc -17 - 201104757 Blocking, rather than attempting to divide the shadow along the middle of the gate electrode 52, can well facilitate the shielding of the gated diodes 32,. In this regard, Figure 8 illustrates yet another example of a P-type gated diode 32". In this example, the P-type gated diode 32'" has a parasitic capacitance that is reduced by blocking both the n-type LDD implant and the P-type LDD implant. In this example, the gated diode The body 32,,, and the middle block both the N-type LDD implant 42 and the P-type LDD implant 46. This situation is illustrated in the gated diode 32''' of FIG. In this example, as provided in the gated diode 32" of FIG. 7, the semiconductor substrate 34'" is provided in the form of an n-type well semiconductor material 64 formed in the P-type substrate 66 to form a P-type. Gated control diode. The filled shallow trench isolation (STI) trenches 68A, 68B are also included in the N+ doped region 40, the cathode terminal 48 and the semiconductor substrate 34, and the P+ doped region 44, the anode terminal 50. Between the semiconductor substrate 34". The filled STI trenches 68 A, 68B provide isolation to prevent or reduce current leakage between the cathode terminal 48 and the anode terminal 50 and the semiconductor substrate 34". In the gated diode 32" of Figure 8, both the N-type LDD implant 42 and the P-type LDD implant 46 are blocked. Blocking N-type LDD implants 42 and P-type LDD implants 46 reduces the original formation of N-type LDD implants 42 and P-type LDD implants without blocking N-type LDD implants 42 and P-type LDD implants 46. The parasitic capacitance between the sidewall of the body 46 and the >-well semiconductor material 64. For example, the total parasitic capacitance of the gated diodes 32... in Figure 8 can be "〇_6 fF/Vmx strip length" and "1. 2 fF/μηιχ strip length". Some parasitic capacitance will still be present between the gate electrode 52 and the N+ doped region 40 and the p+ doped region 44, but due to the N+ doped region 4〇 and the p+ doped region 44. The distance from the gate electrode 52 increases, and the parasitic capacitance will be much smaller. In addition, 147074. Doc •18- 201104757 As previously described above, in the gated diode 32", (for example, W)m〇sfet, the 'blocking N-type LDD implant 42 and the P-type LDD implant 46 will not be disadvantageous. Ground affects the gated diode 32'|. A gated diode having at least one blocked LDD implant (such as the gated diodes 32, 32, 32, and 32" discussed above) can be included in any circuit, integrated circuit Or in a circuit application. An example includes an electrostatic discharge (ESD) protection circuit. The ESD protection circuit can be configured similar to the ESD protection circuit 18 illustrated in FIG. 1, wherein one of the conventional ESD surge diodes 2, 22 Or more than one or more gated diodes having at least one blocked ldd implant. The use of one or more gated diodes having at least one blocked LDD implant in the ESD protection circuit enhances the voltage clamping time due to the fast turn-on time of the gated diode, and due to the gated diode The high conductivity properties of the body enhance the shunting of excess current. Again, one or more gated diodes having at least one blocked LDD implant are used to reduce the load capacitance of the ESD protection circuit. This situation allows the fine protection circuit to protect the circuit that is sensitive to load capacitance while still achieving the ESD characteristics of the gated diode. It may be important to reduce the load capacitance in a protected circuit that is suitable, including operation at the desired efficiency, speed and/or sensitivity. A gated diode having at least one blocked LDD implant can be used in any device or circuit and can be used in particular for circuits where performance may be sensitive to load capacitance. In the real world of devices and circuits, including high-speed differential input/output circuits and radio frequency (RF) circuits, radio frequency (RF) circuits include, but are not limited to, low noise amplifiers (LNAs). Figure 9 illustrates a transceiver 7A as a possible device and/or integrated circuit for providing a protection circuit using 147074. Doc -19· 201104757 One or more gated diode protections with at least one blocked LDD implant Low Noise Amplifier (LNA). The (these) gated diodes used in the protection circuit can be one or more of the previously described gated diodes 32, 32, 32, 32. Transceiver 70 can be implemented with a semiconductor semiconductor (SEMI) and/or SOC technology. Transceiver 70 can be used in any device including, by way of example, a mobile telephone or terminal, a digital assistant (PDA), a wireless local area network (LAN), or other similar wireless communication device. As illustrated in Figure 9, the transceiver 70 can include a receiver front end 72, a radio frequency (RF) transmitter 74, an antenna 76, a switch 78, and a processor 8. The receiving and stealing front end 72 receives information from the loaded radio frequency signals of one or more remote transmitters (not shown). A low noise amplifier (LNA) 82 amplifies the incoming signal received by antenna 76. Protection circuit 84 is added to receiver front end 72 to protect LNA 82 and downstream circuitry from surges (including ESD surges). However, adding a load capacitor to the LNA 82 reduces the sensitivity of [ΝΑ 82. In this regard, the protection circuit 84 can have at least one gated diode having at least one blocked LDD implant. In this manner, the added load capacitance from the protection circuit 84 is reduced by using the gated diode in the latch circuit 84 while still providing excellent turn-on time and high conductivity handling capabilities. The gated diode for use in the ESD protection circuit 84 can be one or more of the previously described gated diodes 32, 32, ', 321 . Alternatively, the security circuit 84 can be an ESD protection circuit and can be configured similar to the ESD protection configuration and ESD protection circuit 18 illustrated in Figure JA or any other desired configuration or circuit. For example, a gated diode can be provided to clamp excess positive 147074. Doc 201104757 Voltage, excessive negative voltage or both' to cause the resulting excess current to shunt. The amplified signal leaving the LNA 82 can be provided to the rf subsystem 86, which can then be digitized using an analog digital (A/D) converter 88. The digitized signal can be provided from an analog to digital (A/D) converter 88 to an asynchronous/synchronous integrated circuit (ASIC) or other processor 80 for processing according to the application. For example, the ASIC or processor 8 can process the digitized received signal to extract information or binabit bits transmitted in the received signal. This processing may include demodulation, decoding, and error correction operations. The ASIC or processor 80 can be implemented by one or more digital signal processors (DSp). On the transmit side, the ASIC or processor 8 can receive the digitized data generated as a result of the received signal, and the ASIC or processor 8 encodes the digitized data for transmission. After encoding the data, the ASIC or processor 8 outputs the encoded data to the RF transmitter 74. The modulator 9 receives data from the ASIC or processor 80, and in this embodiment operates in accordance with one or more modulation schemes to provide a modulated signal to the power amplifier circuit 92. Power amplifier 92 amplifies the modulated signal from modulator 90 to a level suitable for transmission from antenna 76. FIG. 1A illustrates an exemplary ESD protection circuit that can be used as the protection circuit 84 in the transceiver 70 of FIG. The figure illustrates a protection circuit 84 that is configured to protect the input of the LNA 82. As illustrated, the protection circuit 84 includes two gated diodes 93, 94 coupled to the bond pads 96, and a transient clamp portion 98 coupled to the ports 1 and Vss 1〇2. The gated diodes 93, 94 each have at least one via 147074. Doc-21 - 201104757 Blocked LDD implants, and as an example, may be provided in accordance with any of the gated diodes discussed above. The protected iLNA 82 includes an amplifying 1^ channel type thin oxide field effect transistor (NFET) 104, and a source degeneration inductor 〇6 between the source (S) and Vss 102 of the NFET 1〇4. If a positive current is injected into the bond pad 96 relative to Vss 1 在2 during the cdm event, current will flow from the bond pad 96 through the gated diode 93 to Vdd 1 00, and then from vdd 1〇〇 Transient clamping portion 98 to 乂 55 10 ^ transient clamping portion 98 includes NFET 108 coupled from Vdd 1 至 to vss 102; resistor capacitor (RC) transient detector or rC circuit 110; Inverter 112, which acts as a buffer between RC transient detector 110 and NFET 108. During the high speed transient voltage appearing as Vdd 100 to Vss 102, the RC transient detector 11 turns the NFET 108 on' thereby allowing the NFET 108 to shunt large currents with a small voltage drop. During normal operation, NFET 108 is biased off by RC transient detector 110. As an example, the voltage drop between bond pad 96 and Vss 1〇2 should be low enough so that the gate (G) to source (S) voltage across NFET 104 is at a pulse width of 1 nanosecond (ns). Within the gate oxide rupture voltage, 1 nanosecond corresponds roughly to a CDM pulse width. For a 2 Å thick oxide, the rupture voltage of the gate (G) to the source (8) of the NFET 104 is approximately 6.5 in the case of a 1 ns pulse. 9 V. The source degraded inductor W6 has less effect on the voltage drop across the gate (G) to the source (S) of the NFET 104. Therefore, for the current of the positive pad to Vss 102, the gated diode 93 and the NFET 108 have less than 6. in the case where the CDM current amplitude is several amps. The cumulative voltage drop of 9 V. H7074. Doc • 22· 201104757 A gated diode or integrated circuit in accordance with embodiments disclosed herein may be included or integrated in a semiconductor die, and/or in any other device, including an electronic device. Examples of such devices include, but are not limited to, a set-top box, an entertainment unit, a navigation device, a communication device, a PDA, a fixed location data unit, a mobile location data unit, a mobile phone, a cellular phone, a computer, a portable computer, a desktop computer, a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a A digital music player, a portable music player, a video player, a digital video player, a digital video disc (DVD) player, and a portable digital video player. Various modifications can be made to the above-described gated diode structure, in particular, depending on the composition of the various layers used and the touch, the order in which the layers are placed or deposited can be changed. It should also be appreciated that the order of the layers in the gated diodes of the above embodiments and the materials forming the layers are merely illustrative. Moreover, while the support structure is generally depicted as being circular or having a rounded corner in the illustrated embodiment, in alternative embodiments the support structure can have a different shape. Moreover, in some embodiments, other layers (not shown) may be placed or deposited and processed to form portions of the gated diode device or to form other structures on the substrate. In other embodiments, as will be known to those skilled in the art, such layers can be formed using alternative deposition, patterning, and etching materials and processes, can be placed or deposited in a different order, or by different The materials are in harmony. Please also note that 147074 is described herein in any of the exemplary embodiments. Doc •23- 201104757 The detailed tasks are described to provide examples and discussion. The described operations can be performed in the same way as the wealth of the money. Moreover, the operations described in a single operational task may actually be performed in a number of different tasks, and one or more of the operational tasks discussed in the illustrative embodiments may be combined. Those skilled in the art will also appreciate that information and signals may be represented using any of a variety of different techniques and techniques. For example, data commands, commands, information, signals, bits, symbols, and codes that may be referenced by the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields, or magnetic particles, light fields, or light particles, or any combination thereof. sheet. The previous description of the present invention is provided to enable any person skilled in the art to make or use the invention. Various modifications of the invention will be readily apparent to those skilled in the <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; Therefore, the present invention is not intended to be limited to the examples and the details described herein, but rather the broadest scope of the principles and novel features disclosed herein. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an example of a conventional electrostatic discharge (ESD) protection circuit in the prior art; FIG. 2 is a diagram of an exemplary comparison of input capacitances between a pair of input diodes. The polar body is embodied as a gated diode and as a shallow trench isolation (STI) diode; Figure 3 is an exemplary gated diode including a lightly doped (LDD) implant; Figure 4 is a representation An exemplary graphical symbol of the gated diode of Figure 3; 147074. Doc • 24· 201104757 Figure 5 is an illustrative comparison of the gate and cathode overlap capacitance of Figure 3 of the gated diode as a percentage of the total capacitance of the free-controlled diode; Figure 6 is an exemplary gate control a polar body that blocks n-type LDD implants to reduce the capacitance of the N+P-type well-gated diode; FIG. 7 is an alternative exemplary embodiment of a gate-controlled diode, the gate-controlled diode barrier P Type LDD implant to reduce the capacitance of the P+N well gated diode; Figure 8 is an alternative exemplary embodiment of a gated diode that blocks N-type LDD implants and P Type LDD implants to reduce the capacitance of the gated diode; Figure 9 is an exemplary radio frequency (RF) transceiver including a protection circuit having at least one gate 2 blocking at least one LDD implant The polar body; and FIG. 1 is an exemplary low noise amplifier protected by an ESD protection circuit that uses a gated diode having at least one blocked ldd implant. [Main component symbol description] 10 Voltage rail (vdd) / signal ground 12 Ground rail (GND) / Signal ground 14 Protected circuit 16 Signal pin 18 Conventional ESD protection circuit 20 Positive ESD surge diode 22 Negative ESD Wave diode 24 node 147074. Doc •25· 201104757 26 Modeling diagram 28 Gated control diode pair 30 STI diode pair 32 Gated diode 32' Gated diode 32" Complementary P-gate Gated diode 32'" P Type gated diode 34 base semiconductor substrate 34" semiconductor substrate 34'" semiconductor substrate 36 P-type well semiconductor material 38 P-type substrate 40 N+ doped region 42 N-type LDD implant 44 P+ doped region 46 P-type LDD implant 48 Cathode (k) or source (S) node terminal 50 Anode (a) or drain (D) node terminal 52 Gate electrode (G) 54 Gate terminal 56 Insulation layer 58A Spacer region 58B Spacer Area 60 Modeling Chart 147074. Doc -26- 201104757 62 Line 64 N-well semiconductor material 66 P-type substrate 68A Shallow trench isolation (STI) trench 68B Shallow trench isolation (STI) trench 70 Transceiver 72 Receiver front end 74 Radio frequency (RF) transmission 76 Antenna 78 Switch 80 Processor 82 Low Noise Amplifier (LNA) 84 Protection Circuit 86 RF Subsystem 88 Analog-to-Digital (A/D) Converter 90 Modulator 92 Power Amplifier Circuit 93 Gate Control Diode 94 Gate Control Diode 96 Bonded Pad 98 Transient Clamping Section 100 Rail Voltage (Vdd) 102 Vss 104 Amplified N-Channel Thin Oxide Field Effect Transistor (NFET) 147074. Doc •27· 201104757 106 Source degeneration inductor 108 N-channel field effect transistor (NFET) 110 Resistor capacitor (RC) Transient detector or RC circuit 112 Inverter a Anode G Gate K Cathode S Source 147074. Doc -28 -