30903twf.doc/n 201103080 六、發明說明： 【發明所屬之技術領域】 树明是有關於體電路的製造方法，且特別是 有關於一種半導體元件的製造方法。 【先前技術】 為符合市場輕、薄、短、小之需求’半導體製程不斷 # 地向更小線寬演進。然而，線寬縮小之後，各材料層的阻 值、圖案的輪廓以及缺陷的控制將更形重要。 舉例來說，在金屬·絕緣層.金屬電容器中，金屬電極 的應力遷移(stressmigration，SM)的效能不#，阻值位移分 佈太大’將嚴重影響電容器的電荷儲存特性。電容器彼此 之間的間隙變小’餞刻的殘留物若留在相鄰兩個電容器之 間，則可能會造成電容器橋接的問題。此外，電容器二電 極輪廓控制不當，則可能造成短路的問題。 电 ® 【發明内容】 本發明提供-種半導體元件的製造方法，用以改 力遷移的效能。 °… 本發明提供一種半導體元件的製造方法，用以有效 制圖案化的導電層的輪廓。 二 本發明提供一種半導體元件的製造方〉去，用以避 案化導電層之間橋接的問題。 本發明提出種半導體元件的製造方法。此方法包括於 201103080 ^ 〜^2008-0499 30903tw£doc/n 基底上形成含銘與銅的下電極材料層。接著，於下電極材 料層表面上依序形成絕緣材料層與上電極材料層。 於上電極材料層上形成光阻層。以圖案化的光阻層為罩 幕’進行另-侧步驟以移除上電極材料層以及部分之該 絕緣材料層其中剩餘之絕緣材料覆蓋於該下電極材料層之 表面。繼之，灰化移除圖案化的光阻層。之後，對下電極 材料層進行融合製程。之後，進行另—_倾，將剩餘 =，材料層與下電極材料層圖案化，以形成圖案化的絕 緣層”圖案化的下電極層，其中圖案化的上電極層、圖案 化的絕緣層、圖案化的表面處理層與圖案化的下電極層共 同構成金屬-絕緣層-金屬電容器。 、 依照本發明實施例所述，上述半導體元件的製造方法 述融合製程可以是在氣體環境中進行或是在沒有氣 =環?:進行，氣體環境中可以含有氣氣、氮Ϊ 。上述融合製程是在攝氏觸至度的 圍中進仃。上述融合製程進行的時間為05小時至2小時。 中，ίΓΐΓ月ΐ施例所述’上述半導體元件的製造方法 序开"I料層的方法包括：在上述基底上依 料成弟-阻Μ、含銘與銅的金屬層與第二阻障層。 依照本發明實施例所述’上述半導體元件的製:方法 挪、ίΓ其=與上述第二阻障層分別包括遍、τί、 依照本發明實施酬述，上述半導體元件_造方 中’上迷含轉銅的金屬層為_合金層或㈣銅合金層。 U08-0499 30903nvf.d〇c/n 201103080 更包ίΤίΓΓ—_述，上料導體元件的製造方法 ί、==絕緣材料層之前，進行熱處理製择，於 上义下電極材料層表面形成表面處理層。 依照本發明實施例所述，上述半導 述熱處理製程使上述第二阻障層表面形成上:表面 φ 本發明實施例所述’上述半導體元件的製造方法 :電製程包括臭氧爾程、氧嶋丄他氣 中明實施例所述’上述半導體元件的製造方法 述絕緣材料層包括氧化物、氮化物、氧嫌化物 且d ¥Ub物/氮化物/氧化物堆疊層或其組合。 明實施例所述’上述半導體元件口的製造方法 組合。U上電姉料層包括TiN、Ti、Ta、、紹或其 中，實施例所述，上述半導體元件的製造方法 中上述基底上已形成多重金屬内連線。 底卜半導體元件的製造方法，包括於基 二導t電材料層、絕緣材料層與圖案化的第 行多數個熱製程，其所累積之熱預算 中形成耕$電材料層或上述圖案化的第二導電層 溶‘而凉奂進行融合製程’使上述析出物固態 化、，邑、，象層。之後，圖案化上述第一導電材料層，以形成圖 201103080 -08-0499 3〇903twf.doc/n 案化的第一導電層。 健、本㈣實關聽，上辭導料件㈣造方法 中’上述融合製程可以是在氣體環境中進行 '有氣 環境中進行，上述氣體環境中含有氫Γ、Γ氣、 上述融合製程進行的溫度範圍為攝氏100 度。上述融合製程進行的時間為〇 5小時至2小時。 依照本發明實施例所述，上述半導體元件的製造方法 中’上料健製純減處理製程、絲 電 漿灰化製程。 依照本發明實施例所述，上述半導體元件的製造方法 中，在形成上述圖案化的第一導電層之後不進行 製程。 σ 本發明之半導體元件的製造方法，可以改善應 的效能。 本發明之半導體元件的製造方法，可以減少圖案化 導電層側壁突起的現象’有效控制圖案化的導電層的輪廓。 本發明之半導體元件的製造方法，可以避免圖案化 電層之間橋接的問題。 '、哥 為讓本發明之上述特徵和優點能更明顯易懂’下文 舉實施例，並配合所附圖式作詳細說明如下。 ' 【實施方式】 圖1Α至1G是依據本發明實施例所繪示之—種半 體元件的製造方法流程的剖面示意圖。 2〇ii〇3〇8〇00,0499 3〇9〇3_c/n 請參照圖1A戶厅示，基底i “4例如是邈輯電路區。基底 】 12上的介電声16二;與介電層18。第-電路區 一電路區有，1層固塞2〇A鱗線22A;第 Μ的；丨電層18中具有介層窗插塞24A。第二 L第電層16中具有介層窗插塞施與導線 介電fi底1〇之間還可包含電晶體、其他的 層16;介 金屬導線編出)。此外，介電 層η ^電層18之間可以再包括钱刻終止層或研磨終止 層％在與介層窗插塞Μ.上形成導電材料 包括阻為雜材料層。在—實施财，導電材料層％ 層32八^28、金屬層3G與阻障層32。阻障層28與阻障 包括含lit括^、^，々或其組合。金屬層抑 ^ ° ^ίίΓίί； 物理洛Γ 與阻障層32的形成方法例如是 如是濺是化，目沉積法。物理氣相沉積法例 如是30ίΓ疋洛鍵。阻障層28與阻障層32的厚度分別例 埃 至1000埃。金屬層30的厚度例如是500至80〇〇 別為施例中，阻障層28、金屬層3G與阻障層32分 層^ j方法形成之5〇0埃的·、6〇00埃的銘鋼合金 句/、5〇埃的Ti/400埃的TiN。在另一實施例中，阻障層 201103080 ⑻8-0499 3〇903t\vf.doc/] 28、金屬層30與阻障層32分別為以濺鍍方法形成5〇〇埃 的TaN/250埃的Ti/25〇埃的TiN、6〇〇〇埃的鋁銅合金層與 50埃的Ti/400埃的TiN。 接著，進行熱處理製程，於導電材料層26表面形成 表=處理層34。當導電材料層26由阻障層28、金屬層3〇、 阻障層32構成時，進行熱處理製程之後，可使得阻障層 32的表面形成表面處理層34。相較於無表面處理層的 情況，表面處理層34與後續形成之絕緣層36之間具有較 佳的介面特性。熱處理製程例如是電漿製程，所通入的氣 體例如是含氧的氣體’所形成的表面處理層34例如是氧化 層。氧化層例如是二氧化鈦層。電漿製程中所通入的含氧 的氣，例如衫氧、氧或具氧化能力之氣體。在一實施例 中，電漿製程進行的條件例如是通入的氣體為1〇〇〇 sccm 至3000%(：111的氧氣；壓力為6〇〇至2〇〇〇毫托；溫度為攝 氏200度至4〇〇度；進行的時間例如是1〇秒至3〇〇秒。在 接著，請參照圖1B，在表面處理層34上形成絕緣材料層 36 :絕緣材料層36包括氧化物、氮化物、氧化物/氮化物 堆宜層、氧化物/氮化物/氧化物堆疊層或其組合。絕緣材 料層36的形成方法例如是化學氣相沉積法。絕緣材料層 36的厚度例如是15〇埃至1〇〇〇埃。 之後，再形成另一導電材料層38,或稱為上電極材料 層。導電材料層38包括TiN、Ti、Ta、TaN、鋁(aluminum) 或其組合。導電材料層38的厚度例如是i5〇埃至1000埃。 導電材料層38的形成方法例如是物理氣相沉積法或是化 201103080 —-^008-0499 30903tvvf.doc/n 學氣=積^_氣相沉積法例如是賤鑛或是蒸錢。 __ 層38上形成 層4〇的形成步驟包括塗布光阻材料曰^阻 硬烤等。 秋辟曝先、顯影、 其後，請參照圖1C，以圖1B所示的罔安儿止 二行?刻製程，移除未被圖案化光阻層4。 二，層38’稞露出絕緣材料層％， 二 12上方形成圖案化的導電層38a。軸 ^电路£ 餘刻法例如是電漿钱刻法。在—實施例=乾式 過程，除了將未被圖案化光阻層4〇 ^丁餘刻的 餘之絕緣#料層36覆蓋於表面處理層％之表t 36。，使剩 之後，移除圖案化的光阻層4〇。 法可以採用濕式移除法、乾式移除法^除^阻層40的方 移除法可贿㈣或是驗。赋移=、4合1^者。濕式 法。 从除奸以採用·灰化 ‘之’請參照圖1C斑id，卜、f y-、皆 f之後在撕_化製紅形 程、絕緣材料層沈積製程、光阻 ^ α括熱處理4 =中=::二積:_算二=: 析發明聚實集施心^ 尚未圖案化之前，即先進行融合製程仏V電材料層26 201103080 …08-_ 3_twf.doc/n 融人程42可以以爐管、加熱板(HotPiate)來進行。 真進是衫錢體環境巾進行或是在沒有氣體的 合，進二境中可以含有氨氣、氮氣或其組 〇.5小時至攝氏100至500度，進行的時間為 ^ ^ ^ 小呀0在—實施例中，融合製程42是在合古 行’ ^行的溫度範圍為攝氏300至 又進仃的時間為〇 5小時至2小時。在 ^道垂方面可以改善應力遷移的效能，另一方面可以# ^電材料層26中的析出物观、5⑽消失。消除導^ 化通可以避免最終卿成之圖案 的^ 物5GA'5()B未移除做而發生橋接 之後1參照圖m，在基底1G上方形朗案 阻曰44。為確保所形成的圖案化光阻層44不會因卜恭 極絕緣材料層36上表面的光阻殘留物 粒的殘留而剝離，通常，在形成圖案化的光阻層4个如 會進订表面電浆清洗，以清除上電極層撕或絕 2 36上表面的光阻殘留物或是污染顆粒。 、"曰 請參照㈣，以圖1£所示的圖案化的光阻層 為罩:二虫刻未被圖案化光阻層44所覆蓋 層36、表面處理層34與導電材料層％，以在第 = 1\=成圖案化的絕緣層36a、表面處理層％與圖純 的導電層26a，並在第二電路區14形成圖案化的絕緣層 10 201103080 υ〇8-〇499 30903twf.d〇c/n 、表面處理層I圖安 =化_ 二=::處= 宰圖案化的導電層如做為下電極層^ 求化的導電層38a做為 《，_ :如做為兩電極之間的;電二30903 twf.doc/n 201103080 VI. Description of the Invention: [Technical Field of the Invention] Shuming is a method of manufacturing a body circuit, and particularly relates to a method of manufacturing a semiconductor element. [Prior Art] In order to meet the market demand for light, thin, short, and small, the semiconductor process continues to evolve toward smaller line widths. However, after the line width is reduced, the resistance of each material layer, the contour of the pattern, and the control of defects will become more important. For example, in a metal/insulator layer. A metal capacitor, the stress migration (SM) of the metal electrode is not effective, and the resistance displacement distribution is too large, which will seriously affect the charge storage characteristics of the capacitor. The gap between the capacitors becomes smaller. If the engraved residue remains between two adjacent capacitors, the capacitor may be bridged. In addition, improper control of the capacitor's two-electrode profile may cause short-circuit problems. BACKGROUND OF THE INVENTION The present invention provides a method of fabricating a semiconductor device for improving the efficiency of migration. °... The present invention provides a method of fabricating a semiconductor device for effectively patterning a patterned conductive layer. The present invention provides a method for fabricating a semiconductor device to avoid the problem of bridging between conductive layers. The present invention proposes a method of manufacturing a semiconductor device. The method includes forming a layer of a lower electrode material containing a copper and a copper on a substrate of 201103080^~^2008-0499 30903 tw. Next, an insulating material layer and an upper electrode material layer are sequentially formed on the surface of the lower electrode material layer. A photoresist layer is formed on the upper electrode material layer. The patterned photoresist layer is used as a mask to perform a further side step to remove the upper electrode material layer and a portion of the insulating material layer, wherein the remaining insulating material covers the surface of the lower electrode material layer. Following this, ashing removes the patterned photoresist layer. Thereafter, a fusion process is performed on the lower electrode material layer. Thereafter, another _ tilt, the remaining =, the material layer and the lower electrode material layer are patterned to form a patterned insulating layer "patterned lower electrode layer, wherein the patterned upper electrode layer, the patterned insulating layer The patterned surface treatment layer and the patterned lower electrode layer together form a metal-insulating layer-metal capacitor. According to the embodiment of the invention, the method for fabricating the semiconductor device described above may be performed in a gas environment or In the absence of gas = ring?:, the gas environment may contain gas, nitrogen and nitrogen. The above fusion process is carried out in the range of Celsius touch. The fusion process is carried out for 05 hours to 2 hours. The method for manufacturing the above-mentioned semiconductor device according to the embodiment of the present invention includes: forming a metal layer and a second barrier on the substrate According to the embodiment of the present invention, the method for manufacturing the above-mentioned semiconductor device: the method, the method, and the second barrier layer respectively include a pass, τί, in accordance with the present invention, the semiconductor device _ In the creator, the metal layer containing the copper is _ alloy layer or (4) copper alloy layer. U08-0499 30903nvf.d〇c/n 201103080 More package Τ Τ _ _ , , , , , , , , , , , Before the layer of the insulating material is subjected to heat treatment, a surface treatment layer is formed on the surface of the upper electrode material layer. According to the embodiment of the present invention, the heat treatment process of the semiconductor described above forms the surface of the second barrier layer: Surface φ The method for manufacturing the above-mentioned semiconductor device according to the embodiment of the present invention: the electrical process includes the ozone process, the oxygen oxime gas, and the method for manufacturing the semiconductor device described above. The insulating material layer includes an oxide and a nitrogen. a compound, an oxygen compound, and a dUb material/nitride/oxide stack layer or a combination thereof. The combination of the above method for manufacturing the semiconductor element port described in the embodiment. The U power-on layer includes TiN, Ti, Ta, In the above method, in the method for fabricating a semiconductor device, a plurality of metal interconnects are formed on the substrate. The method for fabricating a semiconductor device includes a second conductive material layer. The edge material layer and the patterned first row of the plurality of thermal processes, the accumulated thermal budget of the accumulated thermal energy layer or the patterned second conductive layer dissolves and cools the fusion process to make the precipitate solid state Afterwards, the first conductive material layer is patterned to form the first conductive layer of the figure 201103080 -08-0499 3〇903twf.doc/n. Jian, Ben (4) In the method of making the fourth part, the above-mentioned fusion process can be carried out in a gas environment, where the gas environment contains hydroquinone or xenon, and the above fusion process is carried out at a temperature range of 100 degrees Celsius. The above-mentioned fusion process is carried out for a period of from 5 hours to 2 hours. According to an embodiment of the invention, in the method for manufacturing a semiconductor device described above, the method of manufacturing a semiconductor material is a process of purely reducing the processing and a process of wire ashing. According to the embodiment of the invention, in the method of fabricating the semiconductor device, the process is not performed after the patterning of the first conductive layer is formed. σ The method of manufacturing a semiconductor device of the present invention can improve the performance of the application. In the method of fabricating the semiconductor device of the present invention, the phenomenon of patterning the sidewall protrusion of the conductive layer can be reduced, and the contour of the patterned conductive layer can be effectively controlled. The method of fabricating the semiconductor device of the present invention can avoid the problem of bridging between patterned electrical layers. The above features and advantages of the present invention will become more apparent from the following description. [Embodiment] Figs. 1A to 1G are schematic cross-sectional views showing a flow of a method of manufacturing a semiconductor element according to an embodiment of the present invention. 2〇ii〇3〇8〇00,0499 3〇9〇3_c/n Please refer to Figure 1A for the household hall, the base i “4 is for example the circuit area. The substrate] 12 on the dielectric sound 16 2; The electric layer 18. The first circuit region has a circuit region, and the first circuit has a layer 2A scale A 22A; the second layer; the germanium layer 18 has a via window plug 24A. The second L electrode layer 16 has The via window plug may also include a transistor, other layers 16 between the dielectric dielectric and the dielectric layer. In addition, the dielectric layer η ^ electrical layer 18 may include money. The engraving stop layer or the polishing stop layer % forms a conductive material on the interposer plug layer, including a resist material layer. In the implementation, the conductive material layer % layer 32 八 28, metal layer 3G and the barrier layer 32. The barrier layer 28 and the barrier layer comprise a laminate comprising a laminate, a solder, a germanium, or a combination thereof. The metal layer is formed by a metal layer and the barrier layer 32 is formed by, for example, sputtering or deposition. The physical vapor deposition method is, for example, a 30 Å, and the thickness of the barrier layer 28 and the barrier layer 32 is, for example, 1000 angstroms, and the thickness of the metal layer 30 is, for example, 500 to 80 Å. The barrier layer 28, the metal layer 3G and the barrier layer 32 are layered by a method of 5 〇 0 Å, 6 〇 00 angstrom steel alloy sentence, 5 angstrom Ti / 400 angstrom TiN. In another embodiment, the barrier layer 201103080 (8) 8-0499 3〇903t\vf.doc/] 28, the metal layer 30 and the barrier layer 32 respectively form a TaN/250 Å Ti of 5 Å by sputtering. /25 Å of TiN, 6 Å of aluminum-copper alloy layer and 50 Å of Ti/400 Å of TiN. Next, a heat treatment process is performed to form a surface = treatment layer 34 on the surface of the conductive material layer 26. When the conductive material When the layer 26 is composed of the barrier layer 28, the metal layer 3, and the barrier layer 32, after the heat treatment process, the surface of the barrier layer 32 can be formed into the surface treatment layer 34. Compared with the case without the surface treatment layer, the surface The treatment layer 34 has a better interface property with the subsequently formed insulating layer 36. The heat treatment process is, for example, a plasma process, and the surface treatment layer 34 formed by a gas such as an oxygen-containing gas is, for example, an oxide layer. The oxide layer is, for example, a titanium dioxide layer. The oxygen-containing gas introduced in the plasma process, such as oxygen, oxygen or oxidation energy In one embodiment, the plasma process is carried out, for example, by a gas passing from 1 〇〇〇 sccm to 3000% (: 111 oxygen; a pressure of 6 〇〇 to 2 Torr mTorr; It is 200 degrees Celsius to 4 degrees Celsius; the time taken is, for example, 1 second to 3 seconds. Next, referring to FIG. 1B, an insulating material layer 36 is formed on the surface treatment layer 34: the insulating material layer 36 includes oxidation A nitride, an oxide/nitride stack, an oxide/nitride/oxide stack, or a combination thereof. The method of forming the insulating material layer 36 is, for example, a chemical vapor deposition method. The thickness of the insulating material layer 36 is, for example, 15 Å to 1 Å. Thereafter, another layer of conductive material 38, or layer of the upper electrode material, is formed. Conductive material layer 38 includes TiN, Ti, Ta, TaN, aluminum, or a combination thereof. The thickness of the conductive material layer 38 is, for example, i5 Å to 1000 Å. The method of forming the conductive material layer 38 is, for example, a physical vapor deposition method or a method of chemical vapor deposition or a chemical vapor deposition method such as bismuth or steaming. The step of forming the layer 4 on the layer 38 includes applying a photoresist material, blocking hard baking, and the like. The first exposure, development, and subsequent, please refer to FIG. 1C, and the unpatterned photoresist layer 4 is removed by the two-row etching process shown in FIG. 1B. Second, the layer 38' 稞 exposes the insulating material layer %, and the patterned conductive layer 38a is formed over the second 12 . The axis ^ circuit £ remnant method is, for example, a plasma money engraving. In the embodiment - dry process, except that the insulating layer # 36 which is not patterned by the photoresist layer 4 is overlaid on the surface of the surface treatment layer t 36 . After the remaining, the patterned photoresist layer 4 is removed. The method can adopt the wet removal method, the dry removal method, the method of removing the resistance layer 40, or the bribe (four) or the inspection. Assign =, 4 in 1 ^. Wet method. Please refer to Figure 1C for smear, s, f y-, and f after the smuggling to adopt the ashing id, the red process, the deposition process of the insulating material layer, the photoresist, and the heat treatment 4 =中=::二积:_算二=: Analysis of the invention of the actual collection of the heart ^ Before the patterning, the fusion process 仏V electrical material layer 26 201103080 ... 08-_ 3_twf.doc/n It can be carried out by a furnace tube or a hot plate. True is the body of the money body towel or in the absence of gas, in the second environment can contain ammonia, nitrogen or its group 〇. 5 hours to 100 to 500 degrees Celsius, the time is ^ ^ ^ small In the embodiment, the fusion process 42 is in the range of 3005 hours to 2 hours in the range of the temperature range from 300 to 3,000. In the aspect of the channel, the effect of stress migration can be improved, and on the other hand, the precipitates in the electrical material layer 26 can be eliminated, and 5(10) disappears. Eliminating the conduction can prevent the final pattern of the 5GA'5()B from being removed without bridging. After 1 is referred to the figure m, the square case is blocked on the substrate 1G. In order to ensure that the formed patterned photoresist layer 44 is not peeled off due to the residual of the photoresist residue on the upper surface of the insulating material layer 36, generally, four patterned photoresist layers are formed. The surface is cleaned by plasma to remove photoresist residue or contaminated particles on the upper surface of the upper electrode layer. ""Please refer to (4), and the patterned photoresist layer shown in Fig. 1 is used as a cover: the layer 36 covered by the patterned photoresist layer 44, the surface treatment layer 34 and the conductive material layer%, The insulating layer 36a patterned at the =1\=, the surface treatment layer % and the pure conductive layer 26a, and the patterned insulating layer 10 in the second circuit region 14 201103080 υ〇8-〇499 30903twf. D〇c/n, surface treatment layer I 图安=化_二=::处 = slaughter patterned conductive layer as the lower electrode layer ^ conductive layer 38a as ", _: as two Between the electrodes
的圖4化Γ電™ 在又，例"二電路二==。 吟“層26b則疋做為銲墊。之後，將光阻層44移除。移 j阻層44的方法可以咖濕式移除法、乾式移除法或是 〜兩者。濕式移除法可以使㈣或紐。乾式移除法可 以採用電漿灰化法。 $由於導電材料層％進行圖案化製程之後，不再進行 # =製程’因此’可以避免圖案化導電層26a、26b中的金 屬曰曰格重新排列’而導致重新排舰的金屬晶粒突出於圖 案化之導電層26a、26b的側壁，改變圖案化之導電層26a、 26b的輪廓的情形。 带其後，請參照圖1〇，在基底1〇上形成介電層46。介 毛層46之材質例如是氧化石夕、硼璃石夕玻璃、礦矽玻璃或是 氮，矽，形成的方法例如是化學氣相沈積法。之後，再利 用微影與姓刻製程蝕刻部分的介電層46以及部分的圖案 化的絕緣層36b、部分的圖案化的表面處理層34b，以形成 11 30903twf.doc/n 201103080 ------2008-0499 介層窗開π 48 ’裸露_案化之導電層视，並形成介層 窗開口 50,裸露出圖案化的導電層撕。之後， ^ ，中，導電層’例如是鎢金屬，以麵^ 52、54。之後，再於介電層46上形成分別電性連接介層窗 52、54的導線56、58。導線56、58之材質例如是紹或銘 合金。Figure 4 of the Γ Γ 在 TM in the case of again, the second circuit ===.层 "layer 26b is used as a solder pad. Thereafter, the photoresist layer 44 is removed. The method of shifting the resist layer 44 may be a wet removal method, a dry removal method, or both. Wet removal The method can be (4) or New Zealand. The dry removal method can use the plasma ashing method. Since the patterning process of the conductive material layer is performed, the #=process is no longer performed. Therefore, the patterned conductive layers 26a, 26b can be avoided. The metal grids are rearranged to cause the rearranged metal grains to protrude from the sidewalls of the patterned conductive layers 26a, 26b, changing the contour of the patterned conductive layers 26a, 26b. 1A, a dielectric layer 46 is formed on the substrate 1 . The material of the via layer 46 is, for example, oxidized stone, borosilicate glass, ore glass or nitrogen, and is formed by a chemical vapor phase. After the deposition method, the dielectric layer 46 and a portion of the patterned insulating layer 36b and a portion of the patterned surface treatment layer 34b are etched by the lithography and the etch process to form 11 30903 twf.doc/n 201103080 - -----2008-0499 The window is opened π 48 'naked _ case guide The electrical layer is viewed and a via opening 50 is formed to expose the patterned conductive layer. Thereafter, the ^, the conductive layer 'is, for example, tungsten metal, to the surface 52, 54. Thereafter, the dielectric layer 46 The wires 56 and 58 which are respectively electrically connected to the vias 52 and 54 are formed. The materials of the wires 56 and 58 are, for example, Shao or Ming alloy.
本發明實施例所採用的方法是在進行導電材料層％ 的圖案化製歡前進行融合縣A，實驗結果顯示所形成 的半導體元件在歷㉟’小時的熱烘烤之後，不僅可以改 善應力遷移的效能，而且還可使得阻值位移的分佈小於 5%。此外，融合製程42還可以消除導電材料層％中的析 出物50A、50B。由於導電材料層26中的析出物5〇A、遞The method adopted in the embodiment of the present invention is to perform the fusion county A before performing the patterning of the conductive material layer %. The experimental results show that the formed semiconductor component can not only improve the stress migration after the 35' hour hot baking. The performance, but also allows the distribution of resistance displacement to be less than 5%. In addition, the fusion process 42 can also eliminate precipitates 50A, 50B in the layer of conductive material. Due to the precipitates in the conductive material layer 26, 5〇A,
已經在導電材料層26圖案化之前消除，因此，在導電材料 層26圖案化形成圖案化的導電層26a與2北之後，不會有 析出物殘留所導致的橋接問題。此外，圖案化之導電層 26a、26b形成之後不再進行融合製程，因此不會有晶格重 新排列導致金屬晶粒突出於圖案化之導電層26a、26b的侧 壁’改變圖案化之導電層26a、26b的輪廓的情形。 相反地，若在進行導電材料層26的圖案化製程之前， 不進行融合製程42，而將融合製程改在導電材料層26圖 案化成圖案化的導電層26a與26b之後才進行，則，雖同 樣可以改善應力遷移的效能，但是，實驗結果顯示其所形 成的半導體元件在歷經500小時的熱烘烤之後，阻值位移 分佈較差(大於20%)，且導電材料層26中的析出物50A、 12 201103080 ------UU8-0499 30903twf.d〇c/n 50B在進行導電材料層26的圖案化步驟時很可能無法被 移除而導致最終所形成之圖案化導電層26a、26b之間發生 橋接的問題，此外，在圖案化導電層26a、26b形成之後才 進行融合製程，則會有晶格重新排列導致金屬晶粒突出於 圖案化之導電層26a、26b的側壁，改變圖案化之導電層 26a、26b的輪廓的情形。 綜合以上所述，本發明之半導體元件的製造方法，是 φ 在對基底上已歷經多個熱製程且已析出物的導電材料層進 行圖案化製程之前，先進行融合製程，一方面用以改善應 力遷移的效能，另一方面使導電材料層中的析出物消失， 以避免最終所形成之圖案化導電層之間因為析出物未移除 而發生橋接的問題。此外，由於導電材料層進行圖案化製 程之後，不再進行其他的融合製程，因此，可以避免圖案 化‘黾層中的金屬晶格重新排列，而導致重新排列後的金 屬晶粒突出於圖案化之導電層的侧壁，改變圖案化之導電 層的輪廓。 鲁 雖然本發明已以實施例揭露如上，然其並非用以限定 本發明，任何所屬技術領域中具有通常知識者，在不脫離 本發明之精神和範圍内，當可作些許之更動與潤飾，故本 發明之保護範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1A至1G是依據本發明實施例所緣示之一種半導 體元件的製造方法流程的剖面示意圖。 13 201103080 一一-2008-0499 30903twf.doc/n 【主要元件符號說明】 10 :基底 12、14 :電路區 16、18 :介電層 17 :钱刻終止層或研磨終止層 20A、20B、24A、24B :介層窗插塞 22A、22B :導線 26、38 :導電材料層 26a、26b :圖案化的導電層 28、32 :阻障層 30 :金屬層 34 :表面處理層 34a、34b :圖案化的表面處理層 36 :絕緣層 38a :圖案化的導電層 40、44 :圖案化的光阻層 42 :融合製程 46 :介電層 48、50 :介層窗開口 52、54 :介層窗 56、58 :導線 14It has been eliminated before the patterning of the conductive material layer 26, and therefore, after the conductive material layer 26 is patterned to form the patterned conductive layers 26a and 2, there is no bridging problem caused by the residue of precipitates. In addition, after the patterned conductive layers 26a, 26b are formed, the fusion process is not performed, so that there is no lattice rearrangement, and the metal grains protrude from the sidewalls of the patterned conductive layers 26a, 26b to change the patterned conductive layer. The case of the outline of 26a, 26b. Conversely, if the fusing process 42 is not performed before the patterning process of the conductive material layer 26 is performed, and the fusing process is performed after the conductive material layer 26 is patterned into the patterned conductive layers 26a and 26b, the same is true. The effect of stress migration can be improved, but the experimental results show that the formed semiconductor element has a poor resistance displacement distribution (greater than 20%) after 500 hours of thermal baking, and the precipitate 50A in the conductive material layer 26, 12 201103080 ------UU8-0499 30903twf.d〇c/n 50B is likely to be removed during the patterning step of the conductive material layer 26, resulting in the resulting patterned conductive layer 26a, 26b. The problem of bridging occurs, and further, after the patterning conductive layers 26a, 26b are formed, the fusing process is performed, and the lattice rearrangement causes the metal grains to protrude from the sidewalls of the patterned conductive layers 26a, 26b, changing the patterning. The case of the outline of the conductive layers 26a, 26b. In summary, the manufacturing method of the semiconductor device of the present invention is that φ is subjected to a fusing process before the patterning process of the conductive material layer on the substrate that has undergone a plurality of thermal processes and precipitates, and is used to improve on the one hand. The effect of stress migration, on the other hand, causes the precipitates in the layer of conductive material to disappear, avoiding the problem of bridging between the patterned patterned conductive layers that are formed because the precipitates are not removed. In addition, since the other fusing process is not performed after the patterning process of the conductive material layer, the metal lattice rearrangement in the patterned layer can be avoided, and the rearranged metal grains are protruded from the patterning. The sidewall of the conductive layer changes the contour of the patterned conductive layer. Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Figs. 1A to 1G are schematic cross-sectional views showing the flow of a method of fabricating a semiconductor device according to an embodiment of the present invention. 13 201103080 一一-2008-0499 30903twf.doc/n [Main component symbol description] 10: Substrate 12, 14: circuit area 16, 18: dielectric layer 17: money stop layer or polishing stop layer 20A, 20B, 24A 24B: via window plugs 22A, 22B: wires 26, 38: conductive material layers 26a, 26b: patterned conductive layers 28, 32: barrier layer 30: metal layer 34: surface treatment layers 34a, 34b: pattern Surface treatment layer 36: insulating layer 38a: patterned conductive layer 40, 44: patterned photoresist layer 42: fusing process 46: dielectric layer 48, 50: via opening 52, 54: via window 56, 58: wire 14