201102993 六、發明說明： 【發明所屬之技術領域】 本發明係有關於一種信號同步技術，特別有關於影像 顯示器之源極驅動器所使用的信號同步技術。 【先前技術】 第1圖圖解一種影像顯示器，其中包括一顯示區域 φ 1〇2、一時序控制器（timing controller)l04、一掃描驅動器 (scan driver) 106、以及由複數個源極驅動器（source drivers) SD广SD6所組成的一源極驅動電路i〇8。 時序控制器104控制掃描驅動器1〇6循序輸出複數個 掃描信號，一列一列掃描顯示區域102内的像素。此外， 時序控制器104更提供一時脈信號elk與複數條資料流（包 括圖中data〗所示之複數條資料流、data〗所示之複數條資 料流------data6所示之複數條資料流)至源極驅動電路1〇8。 • 源極驅動器SDi接收時脈信號cik與該等資料流 data]、並根據時脈信號Clk解讀該等資料流data〗以獲得複 數筆資料；源極驅動器SD2接收時脈信號elk與該等資料 流data2、並根據時脈信號Clk解讀該等資料流data2以獲得 複數筆資料；…；源極驅動器SD6接收時脈信號elk與該 等資料流data6、並根據時脈信號elk解讀該等資料流data6 以獲得複數筆資料。源極驅動器SD〗〜SD6把獲得的該些資 料轉換為電壓形式，驅動顯示區域102内掃描中像素顯示 影像。 201102993 門雨要複雜制器104與該些源極驅動11 SDl〜SE>6之 哭^ _ =線。拉線料隸號料，驗源極驅動 :d Γ 接收到的時脈clk、與資科流她】、…、 或data6不同步，導致資料被 _ 錯誤影像。 、“錯誤。顯不區域1G2將顯示 【發明内容】 本發明揭露-種影像顯示器，射包括 一時序控制器以及具有+ 顯不&域、 =3:=:動=:延遲該第-資料流-延遲二 弟一貝料"丨L，且根據該時脈信號、或諛 一反相時脈信號擷取該第二資料流以供誃 像。 、 ’、δΛ .、'、員不區域顯示影 ^述㈣1、與第二資料流之擷取時 反相時脈信號）的驗證與最佳化由驗證信 仏旒或 器於驗證錢雜時驗證上錢遲量、與"源極驅動 最佳值，據.⑽驗證錢除糾設H、° 4脈亚求得 本發明更詳細揭露源極驅動器之信極 驅動器包括-時脈接收器、一反相器、—第原名 資料接收器、一可調式延遲單元、一第 ：：：、；201102993 VI. Description of the Invention: [Technical Field] The present invention relates to a signal synchronization technique, and more particularly to a signal synchronization technique used in a source driver of an image display. [Prior Art] FIG. 1 illustrates an image display including a display area φ 1 〇 2, a timing controller 104, a scan driver 106, and a plurality of source drivers (source) Drivers) SD wide SD6 consists of a source driver circuit i〇8. The timing controller 104 controls the scan driver 1 to sequentially output a plurality of scan signals, and scans the pixels in the display area 102 in a column by column. In addition, the timing controller 104 further provides a clock signal elk and a plurality of data streams (including a plurality of data streams shown by data in the figure, and a plurality of data streams indicated by data). A plurality of data streams) to the source drive circuit 1〇8. The source driver SDi receives the clock signal cik and the data stream data, and interprets the data stream data according to the clock signal Clk to obtain a plurality of data; the source driver SD2 receives the clock signal elk and the data Streaming data2 and interpreting the data stream data2 according to the clock signal Clk to obtain the plurality of data; the source driver SD6 receives the clock signal elk and the data stream data6, and interprets the data streams according to the clock signal elk. Data6 to get multiple data. The source drivers SD to SD6 convert the obtained data into a voltage form to drive the pixels in the scanning area of the display area 102 to display images. 201102993 The door rain is complicated by the controller 104 and the source drives 11 SDl~SE>6 crying ^ _ = line. Pull the wire material, the source drive: d 接收 The received clock clk, and the undergraduate flow her], ..., or data6 are out of sync, causing the data to be _ error image. "Error. Display area 1G2 will be displayed" [Invention] The present invention discloses an image display, including a timing controller and having a + display & field, =3:=: move =: delay the first data The flow-delay second brother and one of the materials "丨L, and according to the clock signal, or the first inversion clock signal, the second data stream is extracted for the image. , ', δΛ ., ', not Verification and optimization of the area display image (4) 1, and the inverted clock signal when the second data stream is captured) is verified by the verification letter or the device when verifying the money, and the source is " The best value of the pole drive, according to (10) verification money in addition to the correction H, ° 4 pulse to find the more detailed disclosure of the source driver of the source driver including - clock receiver, an inverter, - the original name information Receiver, an adjustable delay unit, a first:::,;
步控制單元。 以及一R ，接收n 一時脈信號。反相器耦接 =以產生-反相時脈信號。第Γ多工器 ‘ 收器、與反相器，且根據一時脈反轉控制信號輪出上述= 201102993 脈信號、或反相時脈信號。資料接收器接收一第一資料流。 ' 可調式延遲單元以一延遲量延遲該第一資料流，以產生一 第二資料流。第一閂鎖根據該第一多工器之輸出擷取上述 第二資料流。參考第一閂鎖之輸出，已成功克服信號不同 步問題。 同步控制單元負責驗證、最佳化該可調式延遲單元所 使用的上述延遲量、與該時脈反轉控制信號。同步控制單 元接收一驗證信號、以及該第一閂鎖之輸出。驗證信號致 • 能時，同步控制單元根據該第一閂鎖之輸出驗證該可調式 延遲單元所使用之上述延遲量是否適用，據以設定該延遲 量於該驗證信號除能時的值。此外，同步控制單元更於驗 證信號致能時根據該第一閂鎖之輸出驗證上述時脈信號、 反相時脈信號何者適合擷取該第二資料流，據以設定時脈 反轉控制信號於驗證信號除能時之值。 上述信號同步技術並不限定於影像顯示領域中。上述 信號同步裝置不僅可應用影像顯示器之源極驅動器内，更 ® 可應用於任何電子設備中。 本發明亦揭露一種信號同步方法，用以同步所接收的 一時脈信號與一第一資料流。該信號同步方法包括：延遲 該第一資料流一延遲量以產生一第二資料流；根據一擷取 時脈擷取該第二資料流，以獲得該第一資料流所實際傳輸 之資料，其中，該擷取時脈為該時脈信號、或該時脈信號 的一反相時脈信號；於一驗證信號致能時，驗證該延遲量 是否適用，據以設定該延遲量於該驗證信號除能時之值； 以及，於該驗證信號致能時，更驗證上述時脈信號、反相 201102993 時脈信號何者適合作為該擷取時脈，據以於該驗證信號除 能時使用。 為讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂’下文特舉出較佳實施例’並配合所附圖式，作詳 細說明如下。 【實施方式】 第2圖圖解本案影像顯示器的一種實施方式。相較於 第1圖之傳統技術，第2圖對時序控制器2〇4與源極驅動 電路208内的複數個源極驅動器，〜SD6,作了特別的設 計。時序控制器204除了輸出一時脈信號dk、複數條資料 流（包括複數條資料流data!、複數條資料流data2、…、以 及複數條資料流data6)，更輸出一驗證信號de_skew。時序 控制器204可以一專用線路輸出該驗證信號de—skew，亦 可令該驗證信號de一skew載於傳統技術已存在之信號線 中。 源極驅動器sDl’接收驗證信號de_skew、時脈信號clk 與複數條貪料流data!、源極驅動器Sd2,接收驗證信號 de一skew、時脈信號dk與複數條資料流datai、…、源極驅 動器SD0接收驗證信號de—skew、時脈信號cik與複數條 "貝料流data6。在實際驅動顯示區域1〇2前，各源極驅動器 會對所接收的信號進行一信號同步操作。該些源極驅動器 將=驗證信號de—skew致能時對此信號同步操作進行驗證 與最佳化，據以於驗證信號de__skew除能時使用。 201102993 第3圖圖解本案源極驅動器的一種實施方式，其中僅 以一源極驅動器所接收的複數個資料流之一資料流為例， 圖解該資料流(標號為data，又稱第一資料流）與時脈信號 elk之同步技術。第3圖所揭露之内容可應用於第2圖所有 源極驅動器SEV〜sd6,中，同步源極驅動電路208所接收的 所有信號。 參閱第3圖，源極驅動器300包括：一時脈接收器302、 一反相器304、一第一多工器Mux〗、一資料接收器306、 • 一可調式延遲單元308、一第一閂鎖Latch!、以及一同步控 制單元310。 時脈接收器302接收時脈信號elk。反相器304耦接時 脈接收器302，以產生一反相時脈信號clk_inv。第一多工 器Mux〗耦接時脈接收器302與反相器304,且根據一時脈 反轉控制彳s號En輸出時脈信號elk、或反相時脈信號 clk_inv。資料接收器306接收第一資料流data。可調式延 遲單元308以一延遲量延遲該資料接收器306所接收到的 馨第一資料流data ’以產生第二資料流data_delay。根據第一 多工器Mux〗之輸出’第一閂鎖Latch〗擷取上述第二資料流 data一delay。源極驅動器300以第一閂鎖Latch〗之輸出供第 2圖顯示區域102顯示影像。圖中將實際用於影像顯示之 資料標示為data_drive。 此外’為了確保源極驅動器300内其他後續操作有正 確的邏輯判斷’源極驅動器300更以第一多工器MuXl >以 〈輸 出.作為後續使用之時脈’稱之為邏輯時脈clk_l0gic。由於 資料data一drive之生成與第一閂鎖Latch]所依據之時脈有 201102993 關，且第一閂鎖Latch]所依據之時脈與源極驅動器3〇〇其 他後續操作皆採用一致的時脈一邏輯時脈clkj〇gk—故源 極驅動器300内其他後續操作不會發生邏輯判斷錯誤。 至於可調式延遲單元308所使用的延遲量、二時脈反 轉控制信號En之設定則由同步控制單元31〇決定。同步控 制單元31 〇根據驗證信號de_skew動作，驗證信號如―skew 致能時’ 1¾步控制單it 310根據該第一閃鎖Utchi之輸出Step control unit. And an R, receiving n-clock signals. The inverter is coupled = to generate an -inverted clock signal. The second multiplexer ‘receivers and the inverters, and rotates the above-mentioned = 201102993 pulse signal or inverted clock signal according to a clock inversion control signal. The data receiver receives a first data stream. The adjustable delay unit delays the first data stream by a delay amount to generate a second data stream. The first latch captures the second data stream based on the output of the first multiplexer. Referring to the output of the first latch, the signal different step problem has been successfully overcome. The synchronization control unit is responsible for verifying and optimizing the amount of delay used by the adjustable delay unit and the clock inversion control signal. The synchronization control unit receives a verification signal and an output of the first latch. When the verification signal is enabled, the synchronization control unit verifies whether the delay amount used by the adjustable delay unit is applicable according to the output of the first latch, and accordingly sets the delay amount to the value when the verification signal is disabled. In addition, the synchronization control unit further verifies the clock signal and the inverted clock signal according to the output of the first latch when the verification signal is enabled, which is suitable for capturing the second data stream, thereby setting the clock inversion control signal. The value at which the signal is verified to be disabled. The above signal synchronization technique is not limited to the field of image display. The above signal synchronizing device can be applied not only to the source driver of the image display, but also to any electronic device. The invention also discloses a signal synchronization method for synchronizing a received clock signal with a first data stream. The signal synchronization method includes: delaying the first data stream by a delay amount to generate a second data stream; and extracting the second data stream according to a capture clock to obtain data actually transmitted by the first data stream, The capture clock is the clock signal or an inverted clock signal of the clock signal; when a verification signal is enabled, verify whether the delay amount is applicable, and the delay amount is set according to the verification. The value of the signal when it is disabled; and when the verification signal is enabled, it is further verified that the clock signal and the inverted 201102993 clock signal are suitable as the acquisition clock, and are used when the verification signal is disabled. The above and other objects, features, and advantages of the present invention will become more <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; [Embodiment] FIG. 2 illustrates an embodiment of the image display of the present invention. Compared to the conventional technique of Fig. 1, Fig. 2 shows a special design of the plurality of source drivers, SD6, in the timing controller 2〇4 and the source driver circuit 208. The timing controller 204 outputs a verification signal de_skew in addition to a clock signal dk and a plurality of data streams (including a plurality of data streams!, a plurality of data streams data2, ..., and a plurality of data streams data6). The timing controller 204 can output the verification signal de-skew on a dedicated line, and can also cause the verification signal to be carried in a signal line existing in the conventional technology. The source driver sD1' receives the verification signal de_skew, the clock signal clk and the plurality of gracious data data!, the source driver Sd2, the reception verification signal de-skew, the clock signal dk, and the plurality of data streams datai, ..., the source The driver SD0 receives the verification signal de-skew, the clock signal cik, and the plurality of lines "bee stream data6. Each source driver performs a signal synchronization operation on the received signal before actually driving the display area 1〇2. The source drivers verify and optimize the synchronization operation of the signal when the verification signal de-skew is enabled, so as to be used when the verification signal de__skew is disabled. 201102993 FIG. 3 illustrates an embodiment of the source driver of the present invention, in which only one data stream of a plurality of data streams received by one source driver is taken as an example, and the data stream (labeled as data, also called first data stream) is illustrated. ) Synchronization with the clock signal elk. The contents disclosed in Fig. 3 can be applied to all signals received by the synchronous source driving circuit 208 in all of the source drivers SEV to sd6 of Fig. 2. Referring to FIG. 3, the source driver 300 includes a clock receiver 302, an inverter 304, a first multiplexer Mux, a data receiver 306, an adjustable delay unit 308, and a first latch. Lock Latch!, and a synchronization control unit 310. The clock receiver 302 receives the clock signal elk. The inverter 304 is coupled to the clock receiver 302 to generate an inverted clock signal clk_inv. The first multiplexer Mux is coupled to the clock receiver 302 and the inverter 304, and outputs a clock signal elk or an inverted clock signal clk_inv according to a clock inversion control 彳s. The data receiver 306 receives the first data stream data. The adjustable delay unit 308 delays the first data stream data received by the data receiver 306 by a delay amount to generate a second data stream data_delay. The second data stream data-delay is retrieved according to the output 'first latch Latch' of the first multiplexer Mux. The source driver 300 displays an image for the second map display area 102 with the output of the first latch Latch. The data actually used for image display is labeled as data_drive. In addition, 'to ensure that other subsequent operations in the source driver 300 have the correct logic judgment', the source driver 300 is further referred to as the first multiplexer MuXl > <output. as the clock for subsequent use' is called the logical clock clk_l0gic . Since the data data-drive generation and the first latch Latch] are based on the clock 102102993, and the first latch Latch is based on the clock and the source driver 3 is the same as other subsequent operations. Pulse-logic clock clkj〇gk—There will be no logic error in other subsequent operations in the source driver 300. The delay amount used by the adjustable delay unit 308 and the setting of the second clock inversion control signal En are determined by the synchronization control unit 31. The synchronization control unit 31 动作 operates according to the verification signal de_skew, and when the verification signal is “skew enabled”, the control unit single 310 is output according to the first flash lock Utchi.
執行-驗證程序與-最佳化程序。該驗證程序將提供多種 測試條件(不同的En設定、不同的延遲量設定）測試第3圖 所示之電路。基於上述驗證程序之_結果，該最佳化程 序將找出該可調式延遲單元3G8之上述延遲量的最佳值、 並且妥善設定時脈反轉控制信號Εη，以於驗證信號 de_skew除能時使用。 ★第4A與4B圖以兩種信號不同步狀況說明第3圖中部 分信號之關係；其中’隨著不同步程度之差異，已以上述 最佳化程序決定時脈反轉控制信號En之致能、或除 能，並已選擇好適當的延遲量。 參閱第4A圖，未有信號線延遲的第一資料流顯示為 ideal ’其中第一筆資料⑴必須根據時脈信號他之上 被、· 4取第—筆資料(2)必須根據時脈信號dk之下降緣 :貝取然而’ Λ際傳送到源極接收器細的第一資料流 一^不與時脈虎Clk同步，與理想資料流data-ideal存 ίΜΜ二1〇2針對偏移4〇2,同步控制單元310根據驗證、 4〇4私&之、"果叹定可調式延遲單元308提供一延遲量 ， 時脈反轉控制信號En。經過可調式延遲單 201102993 元308作用後，第一資料流data經延遲量404延遲成第二 ' 資料流data_delay。此外，第一多工器Mux!在致能的時脈 ' 反轉控制信號En操作下輸出反相時脈信號Clk_inv操作第 一閂鎖Latch〗擷取第二資料流data_delay。參閱第4A圖， 第二資料流data一delay内第一、第二筆資料（1、2)分別由反 相時脈信號clk_inv之上升緣、下降緣成功擷取。反相時脈 信號clk_inv提供足夠的設定區間（setup time，如標號406) 與維持區間（hold time ’如標號408)擷取第二資料流 9 data_delay，可確保資料判讀正癌。 參閱第4B圖’其中，實際傳送到源極接收器300的第 一資料流data與理想資料流data_ideal存在一偏移410。針 對偏移410，同步控制單元310根據驗證、最佳化程序之 結果設定可調式延遲單元308提供一延遲量412，且除食t 該時脈反轉控制信號En。經過可調式延遲單元3〇8作用 後，第一資料流data經延遲量412延遲成第二資料流 data_delay。此外，由於時脈反轉控制信號En除能，第一 ® 多工器厘1^1輸出該時脈信號elk操作第一閂鎖Latchi。第 二資料流data—delay内第一、第二筆資料（1、2)分別由時脈 信號elk之上升緣、下降緣成功擷取。如圖所示，時脈^ 號elk以足夠的設定區間（如標號414)與維持區間（如標號 416)擷取第二資料流data一delay内的資料，可確保資料Ί 讀正確。 、 ^ 接下來舉例說明上述驗證程序。假設可調式延遲單元 3〇8提供N.種延遲量供使用者選擇，可延遲該第一資料= data零個至(N_丨)個時間單位。驗證信號de—skew致能時机 201102993 第一資料流data傳送2N個測試資料以提供2N次測試；對 應之’第一閂鎖Latch!之輸出呈2N個對照資料。詳細說 明之’關於其中N個測試資料，同步控制單元31〇令時脈 反轉控制信號En致能’且令該可調式延遲單元3〇8在上述 N個延遲量間切換；關於其餘^^個測試資料，同步控制單 元310令時脈反轉控制信號En除能，且令該可調式延遲單 το 308在上述N個延遲量間切換。比對上述2N個測試資Execution-verification procedures and optimization procedures. This verification procedure will provide a variety of test conditions (different En settings, different delay settings) to test the circuit shown in Figure 3. Based on the result of the above verification procedure, the optimization program will find the optimum value of the delay amount of the adjustable delay unit 3G8 and properly set the clock inversion control signal Εη to disable the verification signal de_skew. use. ★ The 4A and 4B diagrams illustrate the relationship of some signals in Figure 3 with two kinds of signal out-of-synchronization conditions; where 'with the difference in the degree of unsynchronization, the clock reversal control signal En has been determined by the above optimization procedure. Can, or disable, and have chosen the appropriate amount of delay. Referring to Figure 4A, the first data stream without signal line delay is displayed as ideal 'where the first data (1) must be based on the clock signal, and the fourth data is taken (2) must be based on the clock signal The falling edge of dk: Becking however 'The first data stream transmitted to the source receiver is not synchronized with the clock Clk, and the ideal data stream data-ideal ΜΜ2〇2 for the offset 4〇 2. The synchronization control unit 310 provides a delay amount, the clock inversion control signal En, according to the verification, 4〇4 private & After the adjustable delay of the 201102993 element 308, the first data stream data is delayed by the delay amount 404 into the second 'data stream data_delay. In addition, the first multiplexer Mux! outputs the inverted clock signal Clk_inv to operate the first latch Latch under the enabled clock 'reverse control signal En operation' to retrieve the second data stream data_delay. Referring to Fig. 4A, the first and second data (1, 2) in the second data stream data-delay are successfully captured by the rising edge and the falling edge of the inverted phase clock signal clk_inv, respectively. The inverted clock signal clk_inv provides a sufficient set interval (such as reference numeral 406) and a maintenance interval (hold time ' as indicated by reference numeral 408) to obtain a second data stream 9 data_delay to ensure that the data is positively diagnosed. Referring to Fig. 4B', the first stream data actually transmitted to the source receiver 300 has an offset 410 from the ideal stream stream data_ideal. For the offset 410, the synchronization control unit 310 sets the adjustable delay unit 308 to provide a delay amount 412 according to the result of the verification and optimization procedure, and divides the clock inversion control signal En. After being acted upon by the adjustable delay unit 3〇8, the first data stream data is delayed by the delay amount 412 into the second data stream data_delay. Further, since the clock inversion control signal En is disabled, the first ® multiplexer 1^1 outputs the clock signal elk to operate the first latch Latchi. The first and second data (1, 2) in the second data stream data-delay are successfully captured by the rising edge and the falling edge of the clock signal elk. As shown in the figure, the clock number elk captures the data in the second data stream data-delay with a sufficient set interval (such as reference numeral 414) and a maintenance interval (such as reference numeral 416) to ensure that the data is read correctly. , ^ Next, illustrate the above verification procedure. Assuming that the adjustable delay unit 3〇8 provides N. kind of delay amount for the user to select, the first data = data zero to (N_丨) time units can be delayed. Verification signal de-skew enable timing 201102993 The first data stream transmits 2N test data to provide 2N tests; the output of the corresponding 'first latch Latch!' is 2N comparison data. Detailed description of 'with respect to N test data, the synchronization control unit 31 commands the clock inversion control signal En to enable' and causes the adjustable delay unit 3〇8 to switch between the above N delay amounts; The test data, the synchronization control unit 310 disables the clock inversion control signal En, and causes the adjustable delay single το 308 to switch between the N delay amounts. Compare the above 2N test funds
料與2N個對照資料，同步控制單元31〇可得到2N個測試 結果。上述2N測試資料可為同一樣版資料(咖帅㈣。 接著，進行最佳化程序。根據上述2N個測試結果，估 算怎樣的延遲量、時脈反轉控制信號En設定為可行，其最 佳值將在驗證信號de一skew除能時使用。 此段舉例說明上述最佳化方法。假設可調式延遲單元With 2N comparison data, the synchronization control unit 31 can obtain 2N test results. The above 2N test data can be the same version of the data (Cai Shuai (4). Next, the optimization process is performed. Based on the above 2N test results, it is estimated that the delay amount and the clock inversion control signal En are set to be feasible, and the best The value will be used when the verification signal de-skew is disabled. This section illustrates the above optimization method. Suppose the adjustable delay unit
308提供8種延遲量(N=8)供使用者選擇，可延遲該第一資 料流data零錄七個時間單位。在驗證程序進行16次⑽ 測試後，最佳化程序可根據16次職縣找㈣佳的延遲 量、En值設定。使用者可取三個時間單位之延遲量為一基 ^值η的初始值（即㈣），並且統計時脈反轉控制信號En (稱為苐-總合她W、時脈反轉控制錢&為 ΪΓ遲n+1(4)〜7個時間單位的測試成功總數(稱為第i t〇tal2)、時脈反轉控制信號En為除㈣㈣下 〇〜n_時間單位的測試成功總數(稱為第三總合如 «反轉控制信號En為除能的狀態下延遲n+i(4)〜7個) 比 間單位的測試成功總數(稱為第四總合t_4)。藉由反覆、 201102993 較該等總數值totalftotaU與調整該基準值η，可完成該最 ^ 佳化程序。 • 第5圖以流程圖詳述該同步控制單元310於該驗證信 號de_skew致能時之動作。首先執行上述驗證程序（S502)， 共包括2N次測試。接著，執行後續最佳化程序。步驟S504 計算上述第一至第四總數(totali-totaLO。步驟S506比較上 述總數1〜qtotalr totaU)。若最大值為第一或第二總數 (total!或total2)，則致能該時脈反轉控制信號En(步驟 籲 S508)，且以步驟S510比較第一、第二總數(total〗、total2)。 若第一總數(total!)大於第二總數（total2)，則降低基準值 n(步驟S512)，且回到步驟S504。若第一總數(total!)小於 第二總數(total2)，則提升基準值η(步驟S514)，且回到步驟 S504。若第一總數(total〗）等於第二總數(total2)，則維持基 準值η且結束流程。另外’若最大值為第三或第四總數 (total3或total4)，則除能該時脈反轉控制信號En(步驟 S516)，且以步驟S518比較第三、第四總數(total3、total4)。 ^ 若第三總數（totals)大於第四總數（totaU)，則降低基準值 η(步驟S520)，且回到步驟S504。若第三總數(total3)小於 第四總數(totaU)，則提升基準值η(步驟S522)，且回到步驟 S504。若第三總數(totals)等於第四總數(totaU)，則維持基 準值η且結束流程。該流程之結束也可用時間控制 (timeout)。第5圖所示之流程圖將完成時脈反轉控制信號 En的設定（步驟S508或S516)。至於該可調式延遲單元3〇8 之延遲量，則在驗證信號de_skew除能時以上述基準值n 設定之。 12 201102993 在影像顯時序控制器（第2圖之204)可 令驗證信號de「skew於晝面驅動的晝面準備區間 (V-blankmg)或列準備區間(H_blanking)中致能。帛6圖 -晝面驅動與時間之__。如圖所示，相之行進以 標號t顯不，顯示區間602對應顯示區域（第2圖之2〇 驅動。首先’時間t需先經歷一段晝面準備區間 V一Manking;接著’時間t反覆在列準備區間h㈣ 與顯示區間㈤間穿梭’以在驅動每—列前先經歷一 g 備時間。由於源極驅動器（如第2圖之叫，〜叫，)在晝 備區間V—baking或列準備區間H_blanki心並不^作顯 ^域(第2圖之搬），故晝面準備區間（心㈣或列 準備區間H—blanking很適合用來進行上述驗證、最佳化程 序。The 308 provides eight delay amounts (N=8) for the user to select, and the first data stream data can be delayed by seven time units. After the verification program is performed 16 times (10), the optimization program can be set according to the 16th job count (4) and the En value. The user can take the delay amount of three time units as the initial value of a base value η (ie, (4)), and count the clock inversion control signal En (called 苐-total her W, clock reversal control money & The total number of successful tests for n+1(4)~7 time units (called it〇tal2), and the clock inversion control signal En is the total number of successful tests for (n) (four) 〇~n_time units ( Called the third total, such as «reverse control signal En is the state of de-energization, delay n + i (4) ~ 7) the total number of test successes (called the fourth total t_4). 201102993 This optimization procedure can be completed compared to the total value totalftotaU and the adjustment of the reference value η. • Figure 5 is a flow chart detailing the action of the synchronization control unit 310 when the verification signal de_skew is enabled. The above verification procedure (S502) is performed, including 2N tests in total. Next, a subsequent optimization process is performed. Step S504 calculates the first to fourth totals (totali-totaLO. Step S506 compares the total number 1~qtotalr totaU). The maximum value is the first or second total (total! or total2), enabling the clock inversion The signal En is determined (step S508), and the first and second totals (total, total2) are compared in step S510. If the first total (total!) is greater than the second total (total2), the reference value n is lowered (step S512), and returning to step S504. If the first total number (total!) is less than the second total number (total2), the reference value η is raised (step S514), and the process returns to step S504. If the first total number (total) is equal to The second total (total2) maintains the reference value η and ends the flow. Further, if the maximum value is the third or fourth total (total3 or total4), the clock inversion control signal En is disabled (step S516), And comparing the third and fourth totals (total3, total4) with step S518. ^ If the third total (totals) is greater than the fourth total (totaU), the reference value η is lowered (step S520), and the process returns to step S504. If the third total (total3) is smaller than the fourth total (totaU), the reference value η is raised (step S522), and the process returns to step S504. If the third total (totals) is equal to the fourth total (totaU), the reference value η is maintained. And the process ends. The end of the process can also be timeout. The flow chart shown in Figure 5 will be completed. The setting of the clock inversion control signal En (step S508 or S516). The delay amount of the adjustable delay unit 3〇8 is set by the above reference value n when the verification signal de_skew is disabled. 12 201102993 The timing controller (204 in Figure 2) enables the verification signal de "skew" to be enabled in the face-by-side drive preparation interval (V-blankmg) or column preparation interval (H_blanking).帛6图 - 昼 驱动 drive and time __. As shown in the figure, the progress of the phase is indicated by the reference t, and the display interval 602 corresponds to the display area (Fig. 2 is driven by 2〇. First, the time t needs to go through a face preparation interval V-Manking; then the time t repeats Between the column preparation interval h (four) and the display interval (five) to pass a g backup time before driving each column. Since the source driver (such as the call of Figure 2, ~ call), in the backup interval V-baking or The column preparation interval H_blanki heart does not make the display field (the second figure is moved), so the face preparation interval (heart (four) or column preparation interval H-blanking is very suitable for the above verification and optimization procedures.
除了利用晝面準備區問V V 侑匕間Vj>lanking或列準備區間 H—blankmg於影像顯示㈣—再執行上述驗證、最佳 第5圖之流程)，亦可在影像顯示器開機之際就完成 =證、最佳化程序。或者，甚至可在影像顯示器出^ 則就完成上述驗證、最佳化程序。 第7圖為本案源極驅動器的另一種實施方式。盘第^ =源極驅動器300相較，源極驅動器彻改以時脈接收 = 302所接收之上述時脈信號灿作為邏輯時脈他㈣c， 用/供源極驅動器内其他後續電路使用。如此一來， 右時脈反轉控制錢En致能，第一多工器Mux!提供 in；：^ 、後，電路所使用之邏輯時脈clk J〇gic(固定為叫。若以 201102993In addition to using the kneading preparation area to ask the VV daytime Vj>lanking or the column preparation interval H-blankmg in the image display (4) - then performing the above verification, the best picture 5 process), can also be completed when the image display is turned on = certificate, optimization procedures. Alternatively, the verification and optimization procedures described above can be performed even on the image display. Figure 7 is another embodiment of the source driver of the present invention. Compared with the source driver 300, the source driver is changed to the clock signal received by the clock reception = 302 as the logic clock (4) c, and is used by other subsequent circuits in the source driver. In this way, the right clock inversion control money En enables, the first multiplexer Mux! provides in;:^, after, the logic clock used by the circuit clk J〇gic (fixed to call. If 201102993
第一閂鎖Latch!之輸出最為data_drive使用，後續電路之 邏輯運算會發生錯誤。為了避免源極驅動器700後續電路 於時脈反轉控制信號En致能時發生邏輯判斷錯誤，第7 圖特別設計一第二閂鎖Latch2與一第二多工器MuX2，其 中’第二閂鎖Lately與後續電路一致由邏輯時脈 clk_logic(為cik)操作，可將第一閃鎖Latch!之輸出延遲至 正確的時間點，避免源極驅動器700後續操作發生邏輯判 斷錯誤。第二多工器MuX2負責隨著時脈反轉控制信號En 之致月b/除能麵接第一栓鎖Latch〗之摘取結果、或第二栓鎖 Latch2之掘取結果作為資料data—drive，供後續電路使用。 相較於源極驅動器300，源極驅動器7〇〇之設計亦可確保 源極驅動器7〇〇其他後續操作能有正破的邏輯判斷。 本案所揭露之信號同步技術可有效限制可調式延遲單 元308之尺寸。可調式延遲單元3〇8最多僅需提供ι/2時 脈週期之延遲，因此尺寸無須太大。 +此外，凡是相位偏移在-1/4〜1/4時脈週期的資料流，都 可藉上述技術解決。 此外’本案所使狀信號同步技術不Μ安裝於影像 =盗之源極驅動器中，亦可應用於任何電子裝置中作為 m同步使用。 14 201102993 【圖式簡單說明】 • 第1圖圖解一種傳統影像顯示器； 第2圖圖解本案影像顯示器的一種實施方式； 第3圖圖解本案源極驅動器的一種實施方式； 第4A與4B圖以圖例說明第3圖中部分信號之關係； 第5圖以流程圖說明本發明一種實施方式，其中顯示 該驗證信號de_skew致能時，該同步控制單元310之動作； 第6圖圖解一畫面驅動與時間之間的關係；以及 # 第7圖為本案源極驅動器的另一種實施方式。 104〜時序控制器； 108〜源極驅動電路； 208〜源極驅動電路； 302〜時脈接收器； 306〜資料接收器； ;310〜同步控制單元； 404、412〜延遲量； 408、416〜維持區間； clk_inv~反相時脈信號； data_delay〜第二資料流； 【主要元件符號說明】 102〜顯示區域； 106〜掃描驅動益， 204〜時序控制器； 300〜源極驅動器； 304〜反相器； 308〜可調式延遲單元 402、410〜偏移； 406、414〜設定區間， 602〜顯示區間； elk〜時脈信號； clk_logic〜邏輯時脈； data〜弟·貢料流， data_drive〜實際使用之資料； data!、…、data6〜各為複數條資料流； 15 201102993 de_skew〜驗證信號； ' En〜時脈反轉控制信號； H_blanking〜列準備區間；The output of the first latch Latch! is most used by data_drive, and an error occurs in the logic operation of the subsequent circuit. In order to avoid a logic judgment error when the subsequent circuit of the source driver 700 is enabled when the clock inversion control signal En is enabled, FIG. 7 specifically designs a second latch Latch2 and a second multiplexer MuX2, where the second latch is Lately is consistent with the subsequent circuit by the logic clock clk_logic (for cik), which can delay the output of the first flash lock Latch! to the correct time point, avoiding the logic judgment error of the subsequent operation of the source driver 700. The second multiplexer MuX2 is responsible for the extraction result of the month b/disabling surface connected to the first latch Latch with the clock inversion control signal En, or the result of the second latch Latch2 as the data data. Drive, for subsequent circuits. Compared to the source driver 300, the design of the source driver 7〇〇 also ensures that the source driver 7 can have a broken logic decision for other subsequent operations. The signal synchronization technique disclosed in the present disclosure can effectively limit the size of the adjustable delay unit 308. The adjustable delay unit 3〇8 only needs to provide a delay of up to ι/2 clock period, so the size does not have to be too large. + In addition, any data stream with a phase offset of -1/4 to 1/4 clock period can be solved by the above technique. In addition, the signal synchronization technology used in this case is not installed in the source device of the image=theft source, and can also be used as m synchronization in any electronic device. 14 201102993 [Simple description of the diagram] • Figure 1 illustrates a conventional image display; Figure 2 illustrates an embodiment of the image display of the present invention; Figure 3 illustrates an embodiment of the source driver of the present invention; Figures 4A and 4B are illustrated by legend The relationship between the partial signals in FIG. 3 is illustrated. FIG. 5 is a flow chart illustrating an embodiment of the present invention, wherein the action of the synchronization control unit 310 is displayed when the verification signal de_skew is enabled; and FIG. 6 illustrates a screen driving and time. The relationship between; and #7 is another implementation of the source driver of the present case. 104~sequence controller; 108~source drive circuit; 208~source drive circuit; 302~clock receiver; 306~ data receiver; 310~sync control unit; 404, 412~delay amount; 408,416 ~ maintenance interval; clk_inv~ inverted clock signal; data_delay~ second data stream; [main component symbol description] 102~ display area; 106~ scan driver benefit, 204~ timing controller; 300~source driver; Inverter; 308~adjustable delay unit 402, 410~offset; 406, 414~set interval, 602~display interval; elk~clock signal; clk_logic~logic clock; data~di·gong stream, data_drive ~ actual use of the data; data!, ..., data6 ~ each is a plurality of data streams; 15 201102993 de_skew ~ verification signal; ' En ~ clock inversion control signal; H_blanking ~ column preparation interval;
Latch〗、Latch2〜第一、第二閂鎖； Mux〗、Mux2〜第一、第二多工器； SD!、…、SD6〜源極驅動器； SDr.....SD6’〜源極驅動器； t〜時間轴；以及 φ V_blanking〜畫面準備區間。Latch〗, Latch2~first and second latches; Mux, Mux2~first and second multiplexers; SD!,...,SD6~source drivers; SDr.....SD6'~source drivers ; t ~ time axis; and φ V_blanking ~ screen preparation interval.
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