201101317 六、發明說明： 【發明所屬之技術領域】 本發明涉及一種儲存裝置及其控制方法，尤其涉及一種非揮發性儲存 裝置及其控制方法。 【先前技術】 隨著半導體制㈣進步’快閃記髓的儲存紐越來越高，單位記憶 細胞可儲存的錄絲越多，使得快閃記鐘晶片齡龍的容量越來越 大。然而’快閃記憶體隨著容量的加大，㈣大小的#理單位也將有所不 同。 習知-般綱記舰料位記Μ容餘施(Byte位元組)加上冗餘 位元(spare _ bit) ’如第1A圖、第1β圖所示。第u圖中，記憶頁中包 括四個512位元組的記憶區段㈣_、8卜％、％，各記憶區段中分別 儲存資料do、m、D2、D3，而冗餘區域中為存有根據資料別、d】、D2、 D3所產生的ECC修復碼E〇、m、E2、E3。而第m圖中記憶頁中也是 〇 =四個512位元組的記憶區段s〇、I S2、S3，各記憶區段中分別儲存 貝料DO、D卜D2、D3 ’不同的是’根據資料D〇、以、D2、D3所產生的 ECC修復碼EG、m、E2、E3為分雛著紀錄在記憶區段切，，、幻 後面的位置。 在貝料讀取時，如讀取D〇，同時也須將e〇讀取出來，以便進行資料 D〇的錯誤偵測與修復，以確保輪出正確的資料。同理，D1、D2、D3的輸 出’亦須分別讀取El、E2、P办At., 來偵測及修復錯誤位元，以確保輸出資料正 確性。也就是分別利用Ε〇,、Ε2、Ε3來碟保〇0督〇2、〇3輸出的 正確性。 4 201101317 大容量的快閃記憶體單位記憶頁容量為淵加上冗餘位，如第2圖所 示。每區段的大小變成1024位元組，其中為包括兩個512位元組的資料。 而每ι〇24侃組大小舰n料為触若干㈣Ecc猶倾偵錯及修 復。如第2圖，記憶區段s〇的資料，包括D〇及⑴，利用一咖碼· 來作保護，記憶區段S1的資料，包括D2及m，利用一咖碼肪來作 保護。 細’―般系紅所㈣的記《段大小蘇如大容量,_記憶體變 〇成1024位元組’系統上的一記憶區段仍為512位元組的大小。所以，當系 統要求於大容量快閃記題中讀取阳位元組师料時，快閃記憶體的控 制單元仍胁_記麵帽出刪位元組及其咖碼，以檢查刪位 元組的資料中是否有錯誤，若有則予以修復，藉此輸出該筆512位元組正 確的資料。 如第2圖所不，當系統欲讀取資料D0時，須將S0(D0+D1)中的資料以 及由D0與D1產生的Ecc碼E〇1由快閃記憶體中讀取出來，藉此檢查 Ο有無錯誤資料。若有，則將錯誤位元予以修復，以輸出正確的資料D0。 由上述可發現’若系統欲讀取犯位元組的D〇時，為了執行咖來 確遇身料的正確性’仍需讀取整個聰位元組s〇的資料及其咖碼無 法直接4取D0的資料。由於欲輸出〇〇仍須讀取〇1及和⑽的咖 來執行錯誤偵測修復，將造成錯誤位元偵測修復的時間加長，影響 快閃記憶體資訊處理的效能。 【發明内容】 於此本發明提供一種可加快資料讀取時間的非揮發性儲存裝置 5 201101317 及其控制方法。 本發3職—_輸_⑽：帅咖 快閃;:憶體係包括記憶體陣列及資料緩衝區。控制翠元包含錯誤修正: ==啡爾晴姆峨帛物㈣—修正碼和 碼於时料分職__、第—紅碼和第二修正 ❹ 心;第:=。其巾，第—修正於綱伽者詩衫含有錯誤位 儿第-修正瑪用於檢測及修正使用者資料的錯誤位元。 似 街雜舰物物··接 ==，依據所接收_娜，㈣—修正碼和第 以及分別儲存使用者資料、第— ’ / 1和第-修正碼於非揮發性儲存裝 置。，、中’第-修正碼用於檢測使用者資料是否含有錯誤位心 碼用於檢觀修正伽者資料的錯綠心 " 體所= 用本發明_«性储存裝置及其控制方法，當讀取小於快閃記憶 ο , 犯時’透過額外增加-修復碼錢資料的正確性， 從而提升資料的存取速度。 有關本發明的較佳實施例及其功效，兹配合圖式說明如后。 【實施方式】 =_示，瓣_嫩3包含：瓣面％、控制單元μ 及快閃Γ憶體33。連接介面35用以電連接主機1。控制單元3!"含錯 2早疋3U，錯誤修復單元311可根據控制單元^所接收的資料產生 正碼及第二修正碼。其中，第—修正碼可為循環冗餘檢驗碼㈣， 正顿錯寒碼卿卜㈣包軸_ 331及緩 6 201101317 衝為333。主機1傳送資料存取命令給儲存裝置3，儲存裝置3祕制單元 31透過連接介面35接收命令，_執行命令。 當控制單τ〇31接收到資料寫入命令時，透過連接介面％由主機端接 收使用者資料，而錯誤修復單元311根據使用者資料產生CRC碼及Ε(χ 碼’然後控鮮το 31將細者資料、CRC碼及Ε(χ碼傳送雜閃記憶體 331上的緩衝器333 ’接著快閃記憶體再將緩衝器333十的資料，以如第4 圖所示的資料架構，寫入記憶陣列331中。其中CRC碼為根據每512位元 Ο201101317 VI. Description of the Invention: [Technical Field] The present invention relates to a storage device and a control method thereof, and more particularly to a non-volatile storage device and a control method thereof. [Prior Art] With the advancement of the semiconductor system (4), the storage of the flash memory is getting higher and higher, and the more the recording memory that the unit memory cells can store, the larger the capacity of the flash clock chip age dragon. However, as the capacity of flash memory increases, the size of the (four) size unit will also be different. The conventional general-purpose ship's material level is described as the remainder (Byte Byte) plus the redundant bit (spare _ bit) as shown in Figure 1A and Figure 1β. In the figure u, the memory page includes four 512-bit memory segments (four)_, 8b%, %, and the data do, m, D2, and D3 are stored in each memory segment, and the redundant regions are stored. There are ECC repair codes E〇, m, E2, E3 generated according to the data, d], D2, D3. In the m-picture, the memory pages are also 记忆=four 512-bit memory segments s〇, I S2, S3, and the memory materials DO, D Bu D2, D3 'different in each memory segment are ' According to the data D〇, 、, D2, D3, the ECC repair codes EG, m, E2, and E3 are recorded in the memory segment, and the position behind the phantom. When reading the material, such as reading D〇, it is also necessary to read e〇 for error detection and repair of data D〇 to ensure that the correct data is rotated. Similarly, the outputs of D1, D2, and D3 must also read El, E2, and P, respectively, to detect and repair the error bits to ensure the correctness of the output data. That is to use the Ε〇, Ε2, Ε3 to ensure the correctness of the output of the 〇2, 〇3. 4 201101317 Large-capacity flash memory unit memory page capacity is plus plus redundant bits, as shown in Figure 2. The size of each segment becomes 1024 bytes, which is the data including two 512 bytes. And each ι〇24侃 group size n material is a touch (4) Ecc is still misplaced and repaired. As shown in Figure 2, the data of the memory segment, including D〇 and (1), is protected by a code, and the data of the memory segment S1, including D2 and m, is protected by a coffee code. The memory of the fine---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Therefore, when the system requests to read the meta-command in the large-capacity flashing question, the control unit of the flash memory still threatens to delete the bit group and its coffee code to check the deleted bit element. Whether there is an error in the data of the group, if any, repair it, thereby outputting the correct data of the 512-bit group. As shown in Figure 2, when the system wants to read the data D0, the data in S0 (D0+D1) and the Ecc code E〇1 generated by D0 and D1 must be read from the flash memory. This check has no error data. If so, the error bit is repaired to output the correct data D0. From the above, it can be found that if the system wants to read the D〇 of the squad, in order to perform the correctness of the body, it is still necessary to read the data of the entire squad and its coffee code. 4 Take the data of D0. Since it is still necessary to read the 〇1 and (10) coffees to perform error detection and repair, the error bit detection and repair time will be lengthened, which affects the performance of the flash memory information processing. SUMMARY OF THE INVENTION The present invention provides a non-volatile storage device 5 201101317 and a control method thereof that can speed up data reading time. This issue 3 posts - _ lose _ (10): handsome coffee flash;; memory system includes memory array and data buffer. Control Tsui Yuan contains bug fixes: == morphemim 峨帛 ( (4) - correction code and code in the hourly division __, the first - red code and the second correction ❹ heart; The towel, the first-corrected in the singer's singer, contains the wrong bit. The correct-bit is used to detect and correct the error bit of the user data. Like the street cargo object ·· ==, according to the received _ Na, (4) - correction code and the first and separately store the user data, the first ' / 1 and the first correction code in the non-volatile storage device. , the 'the first correction code is used to detect whether the user data contains an incorrect bit center code for detecting the wrong green heart of the corrected gamma data" body = using the invention _ «sex storage device and its control method, When the reading is less than the flash memory ο, when the guilt is made, 'by adding extra-fixing the correctness of the money data, thereby increasing the access speed of the data. Preferred embodiments of the present invention and their effects are described below in conjunction with the drawings. [Embodiment] =_ shows that the flap_nender 3 includes: the flap %, the control unit μ, and the flash memory 33. The connection interface 35 is used to electrically connect the host 1. The control unit 3!" contains the error 2 early 3U, and the error repair unit 311 can generate the positive code and the second correction code according to the data received by the control unit. Among them, the first-correction code can be the cyclic redundancy check code (four), and the positive-correction code is 333, and the rush is 333. The host 1 transmits a data access command to the storage device 3. The storage device 3 secret unit 31 receives the command through the connection interface 35, and executes the command. When the control unit τ 〇 31 receives the data write command, the user data is received by the host terminal through the connection interface %, and the error repair unit 311 generates the CRC code and Ε according to the user data (the code 'and then the control το 31 The finer data, the CRC code, and the Ε (the buffer 333 on the weight transfer memory 331) is followed by the flash memory and then the data of the buffer 333 is written in the data structure as shown in FIG. Memory array 331. The CRC code is based on every 512 bits Ο
組資料所產生，i^ECC碼為根據每⑽4位元組的區段資料產生，亦可更 包括每512位元組資料的CRC碼來產生。 由第4圖中看到，本發明f料儲存模式為每512位元組後紀錄一 crc 碼’而每刪位元組的資料提供ECC碼。例如，分別在5i2位元組數據 DO、D1後記錄其CRC碼CO、CU’並將數據D〇、D1的修復碼記錄在 DO、CO、D卜C1之後。藉此’當系統讀取512位元組大小的資料時，控 制單元則可先檢查該M2位元組資料與其CRC碼，若無發現錯誤，則可直 接輸出該512位元組的資料，而無須讀取整個腦位元組兩個區段的資料 與其ECC碼，再以其ECC碼檢查1〇24位元組資料是否含有錯誤。 而若檢查該si2位元組資料的CRC碼發現資料有錯誤，則控制單元31 再讀取該1024位元組的記憶區段中的另夕卜512 4立元組資料及其咖瑪， 作錯誤修復的動作。於修復完成後，再輸出該512位元組的正確資料。 而資料寫入及讀取的流程如第5圖、第6圖及第7圖所示。 資料寫入方法流程。非揮發性 接著參閱第4圖及第5圖，說明本發明 31便準備接受主 儲存裝置3接收主機1傳來的資料寫入命令，其控制單元 201101317 機1傳來的使用者資料On。控制單元將資料Dn暫存於本身的緩衝器中 (步驟S101)並根據Dn產生CRC碼Cn (步驟S103)，而Cn為接著紀錄在 Dn後面(步驟娜)。然後接收下一筆資料D(n+1)，將咖+1)暫存於控制單 元31的緩衝器中，並紀錄在Cn後，並根據D(n+1)產生crc碼c㈣广 再將C(n+1)接著紀錄在D(n+1)後面。 此時，判斷儲存資料是否達到產生ECC碼的條件，亦即若快閃記憶體 要求X Bytes的資料需要γ廳的ECC碼保護，則每χ吻⑵的資料接收 Ο後’即產生-ECC碼倾該XBytes的制者倾。（但是若寫人的使用者 資料不足XBytes，且後面沒有位址連續的寫人資料，則可根據該筆不足χ Bytes的使用者^料來產生ECC碼。）(步驟⑽7)。當達到產生me碼的條 件時控制單元可根據Dn及吻心)或Dn、Cn、以叫及c(W)來產生 碼E(n-l，n)(或是可勤以以)與c(n l)來產生Ecc碼。）(步驟s·)，並 將E(n l，n)接著紀錄在Cn後(步驟S1U)，以保護及d㈣)或、^、 (1)及C(n-l)的資料正確性。然後控制單元31再繼續接收下筆使用者資 〇 料並重複上述流程產生各筆資料相對應的CRC碼及ECC碼(如第4圖所 示 DO CO、Dl、ci、E01、D2、C2、D3、C3、E23..·)。 田主機1傳送來的資料都已接收並處理完後(步驟S113)，或資料尚未 接收几，但控制單元31中緩衝器的資料已達到快閃記憶體33使用者資料 的單位時(步驟S123)，便將處理好的使用者資料(已產生相對應的CRC及 CC馬)傳送到快閃記憶體33的緩衝器333(步驟S115或步驟S125)，然後 再將該此次赵 μ二貝科寫入記憶陣列331(步驟S117或步驟S127)(如第4圖所示）。 8 201101317 若資料尚未接收完，馳制單元M賴接收接下來的使用者資料，並進行 上述處理程式，以完成資料寫入動作。 接著請參閱第4圖及第6圖，說明由非揮發性儲存裝置3中讀取資料 D0，小於ECC所保護的資料大小(D()+D1或胳⑶仙+⑶的方法。非揮 發性儲存裝置3收耻機丨傳來讀取資料DG的指令後，控鮮元31於記 隐陣列331中5貝取含有資料D〇的記憶頁的資料到快閃記憶體幻的緩衝器 333中(S2〇l)。當然’承前述，該記憶頁的資料也包括D〇的CRC碼c〇及 〇 ECC碼E01(如第4圖）。接著控制單元31由快閃記憶體33的緩衝器333讀 取D0及C0’並暫存於控制單元的緩衝器中(伽)。然後藉由c〇檢查叫步 驟S2〇5)是否存有錯誤位元(步驟，），若沒有發現錯誤位元，雜接輪出 D0(步驟S125)，而不像現有技術(第2圖)須讀取D〇、卬及e〇i來债測錯 誤以輸出正確的D0，有效加快了資料讀取的速度。 若是CRC檢測發現D0存有錯誤位元，此時再由快閃記憶體％的緩 衝器扭中讀取D1及E()1至控制單元的資料緩衝器（步驟8啊或從快閃 〇記憶體33内緩衝器中讀取m、α和簡·制單元内的緩衝器中(如果 衝是透過計算D0、C0、D1和C1產生)），以執行錯誤位元的侧及修復 並判斷錯誤位元是否可修復(步驟仙）。若可修復，則執行ECC功能修復 該錯誤位元(步驟⑵3)，且於修復後，輸出正確的數據D0(步驟奶5)。否則， 報告讀取錯誤(步驟S127)。 接著請參閱第4圖及第7圖，說明由非揮發性記憶裝置3中讀取資料 D贿，等於ECC所保護的資料大小的方法。非揮發性記憶裝置3收到主 機1傳來讀取資料D〇+D1的指令後，控制單元S1於記憶陣列识中讀取 9 201101317 含有資料DO與D1的記憶㈣料馳閃記憶體驗衝器如竹步驟 綱。該記憶頁的資料為包括D〇、m及E〇1(如第*圖）。接著控制單元 μ由快閃記憶體的緩衝㈣讀取DG、m及·，並暫存於控制單元μ 的緩衝器中(步驟伽).根據E〇1針對D〇及m執行錯誤細及修復， 執行咖功能(步驟伽），檢測判斷數據D〇, m是否含有錯誤位元(步驟 _7) ’然後判斷資料中的錯誤位元是否可修復(步驟咖卜若可修復，則 修復資料D0，D1的錯誤位元(步驟_並於修復後，輸出阢及以至主機 Ο 1(步驟S313);否則，報告讀取錯誤。若數據D〇，m不含錯誤位元，則直 接輪出數據D0和D1 (步驟S313)。 由於大容量的快閃記憶體’單位儲存密度較高，所需的ecc強度也較 高。例如，每1024位元組被要求需要24位元的ECC修復能力。而若每512 位元組即提供-ECC碼保護其資料的可靠度，由於不祕證錯誤位元將平 均分散於兩個512位元組的區段(無法預設5丨2位元組内僅出現丨2位元的錯 誤，有可能發生12位元以上的錯誤），因此這樣將造成每1〇24位元組所需 〇 要的ECC碼位數將增加許多。 假設每512位元組提供16位元的ECC修復能力(實際上採16位元ECC 仍有風險，亦即於該512位仍有可能發生π位元以上的錯誤），則每1〇24 位元組共需提供16*13*2=416位元給ECC碼使用。這樣的情形，ECC碼將 佔用冗餘空間的許多位元，甚至有可能快閃記憶體的冗餘空間不夠存放這 樣大的ECC碼。而本發明每512位元組利用一 CRC碼檢查錯誤位元，則 每1024位元組僅需提供4個組給CRC碼使用，再加上1024位元組所需的 ECC 碼共 24*13+8=320 位元。 201101317 知上所述，本發明在使用每一組ECC碼保護資料區段長度大於512位 疋組的快閃記憶體時，可在針對讀寫較小的讀寫單位，亦即讀寫512位元 組沒有發生錯誤的情形下，藉由額外增加CRC檢查碼確定資料正確性，而 提升存取速度，同時確保適足的錯誤偵測與修復的能力。 惟，以上所述，僅為本發明的具體實施例的詳細說明及圖式而已並 非用以限制本發明，本發明的所有範圍應以下述的申請專利範圍第為準， 任何熟悉該獵藝者在本發明的倾内，可㈣思及_化或修飾皆可涵 ® 蓋在以下本案所界定的專利範圍。例如，以上是以快閃記憶體為例進行的 說明’但本領域的普通技術人員可輕易想到的是，快閃記憶體為非揮發性 記憶體的-種’事實上，本發明也可應用於其他類型的非揮發性記憶體， 如 EPROM (Erasable Programmable Read Mem〇ry，可抹除可編程唯讀 s己憶體）、EEPROM (Electrically Erasable Programmable Read Only Memory， 電可抹除可編程唯讀記憶體）、PRANKPh—gehncbmAec^The group data is generated. The i^ECC code is generated based on the segment data of each (10) 4-bit group, and may also be generated by the CRC code of each 512-bit data. As seen from Fig. 4, the f-storage mode of the present invention records a crc code every 512 bytes and the ECC code is provided for each deleted tuple. For example, the CRC codes CO, CU' are recorded after the 5i2 byte data DO, D1, respectively, and the repair codes of the data D〇, D1 are recorded after the DO, CO, D Bu C1. Therefore, when the system reads the 512-bit size data, the control unit can first check the M2 byte data and its CRC code. If no error is found, the 512-bit data can be directly output. It is not necessary to read the data of the two sections of the entire brain byte and its ECC code, and then check whether the 1〇24 byte data contains errors by its ECC code. If the CRC code of the si2 byte data is found to be incorrect, the control unit 31 reads the 512 4 epoch data and the gamma in the memory segment of the 1024 byte. The action of bug fixes. After the repair is completed, the correct data of the 512-bit tuple is output. The flow of data writing and reading is shown in Figures 5, 6, and 7. Data writing method flow. Non-volatile Next, referring to Figures 4 and 5, the present invention 31 is prepared to accept the data storage command transmitted from the host 1 by the main storage device 3, and the control unit 201101317 receives the user data On from the machine 1. The control unit temporarily stores the material Dn in its own buffer (step S101) and generates a CRC code Cn based on Dn (step S103), and Cn is then recorded after Dn (step Na). Then, the next data D(n+1) is received, and the coffee +1) is temporarily stored in the buffer of the control unit 31, and recorded after Cn, and the crc code c (four) is generated according to D(n+1). (n+1) is then recorded after D(n+1). At this time, it is judged whether the stored data reaches the condition for generating the ECC code, that is, if the flash memory requires X Bytes data to be protected by the ECC code of the γ hall, then the data of each kiss (2) is received and the ECC code is generated. Pour the makers of the XBytes. (However, if the user data of the writer is less than XBytes, and there is no continuous writer data in the address, the ECC code can be generated according to the user of the Bytes.) (Step (10) 7). When the condition for generating the me code is reached, the control unit may generate the code E(nl,n) according to Dn and the kiss heart) or Dn, Cn, call and c(W) (or may be diligently) and c(nl). ) to generate the Ecc code. (Step s·), and then E(n l,n) is recorded after Cn (step S1U) to protect the correctness of the data of d(4)), ^, (1) and C(n-l). Then, the control unit 31 continues to receive the user information and repeats the above process to generate the CRC code and the ECC code corresponding to each piece of data (such as DO CO, Dl, ci, E01, D2, C2, D3 shown in FIG. 4). , C3, E23..·). After the data transmitted by the field host 1 has been received and processed (step S113), or the data has not been received, but the data of the buffer in the control unit 31 has reached the unit of the user data of the flash memory 33 (step S123) , the processed user data (the corresponding CRC and CC horse have been generated) is transmitted to the buffer 333 of the flash memory 33 (step S115 or step S125), and then the current Zhao yubei The memory is written to the memory array 331 (step S117 or step S127) (as shown in Fig. 4). 8 201101317 If the data has not been received, the mobile unit M will receive the next user data and perform the above processing to complete the data writing action. Next, please refer to FIG. 4 and FIG. 6 for a method of reading data D0 from the non-volatile storage device 3, which is smaller than the size of the data protected by the ECC (D()+D1 or ((3) sen+(3). Non-volatile After the storage device 3 receives the command to read the data DG, the control unit 31 takes the data of the memory page containing the data D〇 into the flash memory 333 buffer 333 in the hidden array 331 ( S2〇l). Of course, the data of the memory page also includes the CRC code c〇 and the ECC code E01 of D〇 (as shown in Fig. 4.) Then, the control unit 31 is buffer 333 of the flash memory 33. Read D0 and C0' and temporarily store it in the buffer of the control unit (gamma). Then check whether there is an error bit (step,) by c〇, if no error bit is found, The miscellaneous turns out D0 (step S125), instead of reading D〇, 卬, and e〇i as in the prior art (Fig. 2) to test the error to output the correct D0, effectively speeding up the data reading. If the CRC detection finds that D0 has an error bit, then the D1 and E()1 are read from the buffer of the flash memory% to the data buffer of the control unit (step 8 or flash memory) The buffer in the body 33 reads the buffers in the m, α, and simple cells (if the rush is generated by calculating D0, C0, D1, and C1) to execute the side of the error bit and repair and judge the error. Whether the bit can be repaired (step fairy). If it is repairable, the ECC function is executed to fix the error bit (step (2) 3), and after the repair, the correct data D0 is output (step milk 5). Otherwise, the report is read incorrectly (step S127). Next, please refer to FIG. 4 and FIG. 7 for a method of reading data bribes from the non-volatile memory device 3, which is equal to the size of the data protected by the ECC. After the non-volatile memory device 3 receives the command from the host 1 to read the data D〇+D1, the control unit S1 reads in the memory array. 9 201101317 Memory (4) material flash memory experience buffer containing data DO and D1 Such as bamboo steps. The data of the memory page includes D〇, m and E〇1 (as shown in the figure *). Then, the control unit μ reads DG, m, and · from the buffer (4) of the flash memory, and temporarily stores it in the buffer of the control unit μ (step gamma). Performs error correction and repair for D〇 and m according to E〇1. Execute the coffee function (step gamma), check whether the judgment data D〇, m contains the error bit (step _7) 'and then judge whether the error bit in the data can be repaired (if the step is repairable, the repair data D0) , D1 error bit (step _ and after repair, output 阢 and even host Ο 1 (step S313); otherwise, report read error. If the data D 〇, m does not contain error bits, then directly rotate the data D0 and D1 (step S313). Since the large-capacity flash memory has a higher unit storage density, the required ecc intensity is also high. For example, every 1024-bit tuple is required to require 24-bit ECC repair capability. If each 512-bit tuple provides the -ECC code to protect the reliability of its data, since the error-free bits will be evenly spread over the two 512-bit segments (unable to preset 5 丨 2 octets) Only 丨2 bit errors occur, there may be more than 12 bit errors), so this will make The number of ECC codes required for each 24-bit tuple will increase a lot. It is assumed that each 512-bit tuple provides 16-bit ECC remediation capability (in fact, 16-bit ECC is still risky, that is, If the 512 bits still have errors of more than π bits, then a total of 16 * 13 * 2 = 416 bits should be provided for each ECC code to use the ECC code. In this case, the ECC code will occupy redundancy. Many bits of space, and even the redundant space of the flash memory is not enough to store such a large ECC code. However, the 512-bit tuple of the present invention uses only one CRC code to check the error bit, and only 1024 bytes are needed. Four groups are provided for the CRC code, and the ECC codes required for the 1024-bit tuple are 24*13+8=320 bits. 201101317 As described above, the present invention uses each group of ECC codes to protect the data area. When the segment length is greater than the flash memory of the 512-bit group, the data can be determined by additionally adding a CRC check code in the case that no read/write unit for reading and writing is small, that is, no error occurs in reading and writing 512-bit groups. Correctness, while improving access speed while ensuring adequate error detection and repair capabilities. The detailed description and drawings of the specific embodiments of the present invention are not intended to limit the invention, and all the scope of the invention should be based on the scope of the following claims. Within the scope of the patent defined in the following paragraphs, for example, the above is a description of flash memory as an example, but one of ordinary skill in the art can easily think of it. Yes, the flash memory is a non-volatile memory type. In fact, the present invention is also applicable to other types of non-volatile memory, such as EPROM (Erasable Programmable Read Mem〇ry, erasable programmable only) EEPROM (Electrically Erasable Programmable Read Only Memory), PRANKPh-gehncbmAec^
Memory ^ > MRAM(Magnetic Random Access ϋ Memory ^ > FRAM(Feiroelectric Random AccessMemory ^ > MRAM (Magnetic Random Access ϋ Memory ^ > FRAM (Feiroelectric Random Access
Memory，鐵電隨機存取記憶體)等。 【圖式簡單說明】 第1A圖、第1B圖：現有技術小容量記憶體儲存資料於記憶區段的示 意圖。 第2圖.現有赫大容量記，隨齡熱於記舰制示意圖。 第3圖：本發明具體實施模式中_系統的架構示意圖。 第4圖：本發明-較佳實施繼存資料於記憶區段的示意圖。 201101317 第5圖：本發明具體實施模式中使用者資料到快閃記憶體的流程圖。 第6圖：本發明具體實施模式中從快閃記憶體讀取小資料量的流程圖。 第7圖：本發明具體實施模式中從快閃記憶體讀取大資料量的流程圖。 【主要元件符號說明】 1 :主機 3:非揮發性儲存裝置 31 :控制單元 311 :錯誤修正單元 33 :快閃記憶體 331 :記憶陣列 333 :緩衝器 35 :連接介面 12Memory, ferroelectric random access memory), etc. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A and Fig. 1B are diagrams showing the prior art small-capacity memory storing data in a memory segment. Figure 2. The existing large capacity record, with the age of the heat in the record system. Figure 3: Schematic diagram of the architecture of the system in the specific implementation mode of the present invention. Figure 4: The present invention - a preferred embodiment of the data stored in the memory segment. 201101317 Figure 5: Flow chart of user data to flash memory in a specific implementation mode of the present invention. Figure 6 is a flow chart showing the reading of a small amount of data from a flash memory in a specific embodiment mode of the present invention. Figure 7 is a flow chart showing the reading of a large amount of data from a flash memory in a specific embodiment mode of the present invention. [Main component symbol description] 1 : Host 3: Non-volatile storage device 31 : Control unit 311 : Error correction unit 33 : Flash memory 331 : Memory array 333 : Buffer 35 : Connection interface 12