201044782 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種開關驅動電路，特別是指一種電 晶體開關驅動電路。 【先前技術】 參閱圖1及圖2，眾所皆知地，金氧半場效電晶體 (metal-oxide semiconductor field-effect transistor，以下簡稱 MOS)通常是被拿來當作開關使用，圖}為一種習知的開關 模組，具有一 MOS 91及一控制M0S 91啟閉的開關驅動電 路93，利用開關驅動電路93對M0S 91的閘極輸入高準位 電壓，以令MOS 91通路，在導通的瞬間，汲集與源極間的 電壓V從高準位降到零，而電流1則從零迅速上升，如圖2 所示，在V與I交集區域92中產生的重疊面積代表M〇s 91的切換損失（switching l〇ss)，同理可知，在開關驅動電路 93使M0S 91斷路的瞬間，亦會有切換損失，也就是說， 若開關切換的頻率越高則切換損失會越大。切換損失除了 會損耗功率外還會影響元件的壽命’因此好的開關模組其 切換損失必須要小。 除了切換損失外，MOS 91還有在通路狀態時的導通損 失（conduction loss)以及斷路狀態時的漏電流（^匕狀 current)，導通損失肇因於M0S 91開關本身的内阻，而此 内阻在MOS 91導通時是與其通道寬度呈反比，閘極與源極 間的電壓越大’則通道寬度越大且内阻越小，導通損失也 就越小，反之亦然；漏電流則是由於開關驅動電路93是控 201044782 制MOS 91的閘極電壓於零準位，M〇s 91仍有些許的漏電 流在没極與源極間流動，對與開關模組連接的後端電路造 成影響，嚴重的話，可能還會造成誤動作。因此，一個好 的開關模組，最好還必須要降低導通損失以及漏電流所造 成的不良影響。 【發明内容】 因此’本發明之目的，即在提供一種降低電晶體開關 的切換損失、導通損失與漏電流的開關驅動電路。 於是，本發明開關驅動電路，用以接受一第一高準位 訊號以控制-電晶體開關通路，以及接受—零準位:號以 控制該電晶體開關斷路，該開關驅動電路包含一準位轉換 單元及-輪出選擇單元；該準位轉換單元包括一輸入端、 -第-輸出端及一第二輸出$，該準位轉換單元的該輸入 端當接收該零準位訊號，會由該第二輸出端輸出—負壓準 位訊號，而當該輸入端接收到該第_高準位訊號會由該 第-輸出端輸出一第二高準位訊號；該輸出選擇單元分別 電連接該第-輸出4、該第二輸出端，以及該電晶體開關 的閘極’當該準位轉換單元的該輸人端接收到該零準位訊 號，該輸出選擇單元會將該第二輸出端輸出的該負壓準位 訊號傳送給該電晶體開關的問極，使該電晶體開關斷路， 當該準位轉換單元的該輸人端接收到該第_高準位訊號， 該輸出選擇單元會將該第-輸出端輸出的該第二高準位訊 號傳送給該電晶__閘極，使該電晶體開關通路。 較佳地，本發明的準位轉換單元還包括了一橋接於該 201044782 一橋接於該輸入 輸’_第一輪出端之間的第 端與該第二輸出端 叫碼之間的第二電 開關’第-開關的—端電連接二—第-開關及-第二 直流源’另-端電連接該第：該：-高準位訊號的 該零準位訊號，該第一開關為通:二當該:入端接收到 使得哕筮 Φ ^ ^ 該第一電容被充電， 便侍該第一電容的跨壓成為第 電連接一地端， 準位，第二開關的一端 接收到#m古嘴 第―輪出端，當該輸入端 Ο 〇 接收到該第一兩準位訊號， 容心雷法兮性 弟—開關為通路，該第二電 使以苐一電容的跨壓成為第—高準位。 前段所述的該第-開關較佳地可以是一第一二極體， ^陽極電連接該直流源，陰極電連接該第一輸出端，而該 第一開關較佳地可以是一第--权祕 . 弟一一極體，其陽極電連接該第 一輸出端，陰極電連接該地端。 較佳地，前述準位的相對關係為第二高準位為第一高 準位的兩倍，而負壓準位為第一高準位的負i倍。 更佳地，本發明開關驅動電路是輸出一電壓訊號予 MOS開關的閘極，以控制此M〇s開關的通路與斷路。 本發明之功效在於，利用電容儲存電能的特性，讓原 本僅有一個輸入第一高準位訊號的直流源，轉換成一個第 二高準位訊號輸出給電晶體開關，或負壓準位訊號輸出給 電晶體開關，較第一高準位還要高的第二高準位訊號，可 以讓電晶體開關在通路時’其通道寬度更寬，開關内阻因 此變得更小，導通損失也就減少，而負壓準位訊號可以讓 電晶體開關在斷路時’其通道閉鎖得更緊也更難以傳遞電 201044782 子，而減少了漏電流的產生，除此之外，第二高準位訊號 與負壓準位訊號還可以讓電晶體開關的閘極充放電更加迅 速’使得切換損失更小。 【實施方式】 有關本發明之前述及其他技術内容、特點與功效，在 以下配合參考圖式之一個較佳實施例的詳細說明中，將可 清楚的呈現。 參閱圖3，本發明開關驅動電路1〇之較佳實施例包含 一準位轉換單元1、一輸出選擇單元2及一反向單元3 (i請_，開關驅動電路1()可用以接受—第—高準位訊號 以控制-電晶體開關（圖未示）開啟，以及接受—零準位訊號 以控制該電晶體開關關閉。在以下的描述及圖式中，是以 -個電容Cgs來等效電晶體開關（本實施例是以NM〇s為例） 的閘極電谷’以示意充放電的情況。 »亥反向單元3包括彼此的汲極電連接的一 一麵W，勵SQl的源極電連接—直流源VeQ/而 麵OS Q2的源極電連接至—地端4。纟本實施例中直流源 Vcc怪提供—第—高準位（5伏特）的電Μ訊號，而PM0S Q, 與-丽OS Q4閘極是用以接受—方“(例如：脈衝寬度 調製訊號’或稱PWM訊號）的控制，來讓反向單元3的輸 出端31 ’依據所接受的方波來從輸出端31輸出第—高準位 訊號（直流源Vcc提供）或零準位訊號（地端4提供）。 接的輸入端13、一第一輸出端u及一第二輸出端η， 該準位轉換單元包括-與反向單元3的輪出端η電連 橋 201044782 接於該輸入端13與該第一輸出端u之間的第一電容Cl、 一橋接於該輸入端13與該第二輸出端12之間的第二電容 C2、一第一二極體Di及一第二二極體D2;該第一二極體 Di的陽極電連接該直流源Vcc，陰極電連接該第一輸出端 11 ’當該輸入端13接收到由反向單元3傳輸過來的零準位 讯號，該第一二極體Di被導通，該第一電容Cl會被直流源 Vcc透過第一二極體Di充電，使得該第一電容Cl上的跨壓 vci升高至第一高準位（5伏特）；第二二極體D2的陽極電連 接第二輸出端12，陰極電連接該地端4，當該輸入端13接 收到該第一高準位訊號，該第二二極體〇2被導通，第二電 谷C2會被直流源Vcc透過PMOS Q〗充電，使得該第二電容 C2上的跨壓να也升高至第一高準位（5伏特）。 該輸出選擇單元2具有分別作為選擇開關使用的一 PMOS Q3及一 NMOS Q4 ’ PMOS 〇3的源極電連接該第一輸 出端11，閘極電連接該直流源Vcc，汲極則電連接該電晶體 開關的閘極電容Cgs，而NMOS Q4的源極電連接該第二輸 出端12，閘極電連接該地端4，汲極則電連接該電晶體開 關的閘極電容Cgs。 配合圖3參閱圖4，以下敘述及對應圖式中，是忽略第 一二極體Di與第二二極體D2的壓降，並且假設第一電容 Ci與第一電容ο都已經充飽，兩者的跨壓Vei、ν。2皆為第 一高準位（5伏特），而每個跨壓的正負方向定義則如圖3上 所示。當反向單元3的PMOS 斷路，而NM〇s q2通路， 會由輸出端31輸出零準位訊號，準位轉換單元丨的輸入端 201044782 13的電壓準位則同樣會是零準位，以接收到訊號的瞬間暫 態來看’由於第二電容C2的跨壓V。2為第一高準位（5伏特） ，與第二電容C2之負端電連接的第二輸出端12的電壓會在 一負壓準位（在本實施例中’負壓準位為_5伏特），並且讓第 二二極體D2被逆偏而斷路，而NM0S Q4的閘源極跨壓vgs4 此時會是第一咼準位（5伏特），大於臨界電壓（thresh〇ld voltage) ’因此NMOS Q4的汲源極間的通道打開，讓第二輸 出端12輸出該負壓準位的電壓訊號到電晶體開關的閘極電 容Cgs正端；在這個暫態中，由於第一電容心的跨壓yd也 是第一高準位（5伏特），因此第一輸出端丨丨的電壓會在第一 高準位，而PMOS Q3的閘源極跨壓Vgs3會是〇，大於臨界 電壓（threshold voltage)，因此PM〇s Q3的汲源極間的通道 關閉；電晶體開關的閘極電容Cgs正端最後接收到負壓準位 訊號，讓原本累積的電荷可以依循圖4中箭頭h的方向迅 速地被放掉，且通道因為閘極是負電壓準位而閉鎖得更緊 ，達到減少切換損失以及減少漏電流的功效。 配合圖3參閱圖5,以下敘述同樣是忽略第一二極體 D!與第二二極體&的壓降，並假設第一電容g與第二電 谷c2都已經充飽，兩者的跨壓^、ve2皆為第_高準位（5 伏特），而每個跨壓的正負方向定義則如圖3上所示。當反 向旱π 3的PMOS Q,通路，而麵〇s Q2斷路，會由輸出端 31輸出第-间準位訊號，準位轉換單元i的輸人端η的電 壓準位則同樣會是第一高準位以接收到訊號的瞬間暫態 來看’由於第-電容Cl的跨壓w為第—高準位（5伏特）， 201044782 與第電谷Ci之正端電連接的第一輸出端u的電壓會在第 二高準位（在本實施例中，第二高準位為1〇伏特，也就是兩 倍的第一高準位），並且讓第一二極體⑶被逆偏而斷路，而 PMOS Q3的間源極跨麼Vgs3此時會是負屢準位卜$伏特），小 於臨界電壓（threshold v〇ltage)，因此pM〇s Q3的沒源極間 的通道打開’讓第一輸出$ U輸出該第一高準位的電壓訊 號到電晶體開關的閘極電容Cgs正端；在這個暫態中，由於 第一電谷C2的跨壓να也是第一高準位（5伏特），因此第二 〇 輸出端12的電壓會在第零準位，❿NMOS Q4的閘源極跨 壓Vgs4會疋〇，小於臨界電壓（thresh〇id ，因此 NMOS Q4的汲源極間的通道關閉；電晶體開關的間極電容 Cgs正端最後接收到第二高準位訊號，可以迅速地依循圖5 中箭頭I2的方向累積電荷，且通道張得更寬，達到減少切 換損失以及減少導通損失的功效。 必須要注意的是，本發明開關驅動電路1〇除了如前述 所提外，亦可以應用在Ρ_開關上，甚至是絕緣撕雙極 ^ 電晶體（insulated gate bipolar transist〇r，簡稱 IGBT)上並 不以本實施例及其對應圖式為限。 配合圖3參閱圖6,目6為一實驗的量測波形圖，實驗 所採用的電路規格為：（1)直流源ν“為5伏特；（2)第一電 容G和第二電容C2為4·7 "F ;(3)電晶體開關的間極等 效電容 Cgs 為 0.022 //F ; (4)具有 PM0S q〗與 NM〇s 的反向單元3的規格為MIC4420 ; (5)PM0S Q3的規格為 IRLML5103 ; (6) NMOS Q4 的規格為 NDS335N (?)第一二 201044782 極體Di與第二二極體D2的規格A 1AKein ^ β 格為1N58l9。圖ό的波形61 疋輸入10 kHz的方波vg，而波开《丨 反小62則是電晶體開關的閘 極所對應接收到的電壓訊號位準， 高值與最低值分別在-5伏特跟1〇 可以達成本發明所要求的輸出。 其振幅為15伏特，而最 伏特’實驗結果證明確實 综上所述，本發明之功效在於利用第一電容&和第二 電容C2儲存電能的特性，讓原本僅有_個輸人第—高準位 訊號的直流源Vcc，轉換成一個第二高準位訊號輸出給電晶 體開關負壓準位訊號輸出給電晶體開關，讓電晶體開 關在通路時，其通道寬度更寬，開關内阻因此變得更小， 導通損失也就減少，並且在電晶體開關斷路時，其通道閉 鎖得更緊也更難以傳遞電子，而減少了漏電流的產生，除 此之外，第二尚準位訊號與負壓準位訊號還可以讓電晶體 開關的閘極充放電更加迅速，使得切換損失更小。 惟以上所述者，僅為本發明之較佳實施例而已，當不 能以此限定本發明實施之範圍，即大凡依本發明申請專利 範圍及發明說明内容所作之簡單的等效變化與修飾，皆仍 屬本發明專利涵蓋之範圍内。 10 201044782 【圖式簡單說明】 圖1為一種習知開關模組的電路示意圖； 圖2為電晶體開關於切換通路或斷路狀態時，所產生 的切換損失示意圖； 圖3為本發明開關驅動電路之較佳實施例的電路示意 圖， 圖4為本實施例所驅動的電晶體開關，其暫態為放電 的電路示意圖； 〇 圖5為本實施例所驅動的電晶體開關，其暫態為充電 的電路示意圖；及 圖6為本實施例的實驗量測波形圖。 11 201044782 【主要元件符號說明】 10......... 開關驅動電路 Ii…… …··放電電流方向 Ci......... 第一電容 12…… •…充電電流方向 C2......... 第二電容 1…… .....準位轉換單元 Cgs........ 電晶體開關的 11 ·. •…第輸出端 閘極等效電容 12··_. …··第二輸出端 Q1、Q3. · PMOS 13•…. •…輸入端 Q2、Q4 _. NMOS 2…… •…輸出選擇單元 Di......... 第一二極體 3…… .....反向單元 D2......... 第二二極體 31 •…輸出端 Vcc........ 直流源 4…… .....地端 vg......... 方波 61 .···. •…波形 Vgs x Vgs3 x Vgs4 N Vcl N Vc2 62••… •…波形 跨壓 12201044782 VI. Description of the Invention: [Technical Field] The present invention relates to a switch drive circuit, and more particularly to a transistor switch drive circuit. [Prior Art] Referring to FIG. 1 and FIG. 2, it is well known that a metal-oxide semiconductor field-effect transistor (MOS) is usually used as a switch. A conventional switch module has a MOS 91 and a switch drive circuit 93 for controlling the opening and closing of the MOS 91, and the switch drive circuit 93 inputs a high-level voltage to the gate of the MOS 91 to make the MOS 91 path open. At the instant, the voltage V between the collector and the source drops from the high level to zero, and the current 1 rises rapidly from zero. As shown in Fig. 2, the overlapping area generated in the intersection area 92 of V and I represents M〇. The switching loss of s 91 is similar. It can be seen that there is a switching loss at the moment when the switch driving circuit 93 turns off the MOS 91, that is, if the switching frequency is higher, the switching loss will be more. Big. In addition to the loss of power, the switching loss will affect the life of the component. Therefore, the switching loss of a good switching module must be small. In addition to the switching loss, the MOS 91 also has a conduction loss in the path state and a leakage current in the open state, and the conduction loss is due to the internal resistance of the MOS switch itself. When the MOS 91 is turned on, it is inversely proportional to the width of the channel. The greater the voltage between the gate and the source, the larger the channel width and the smaller the internal resistance, the smaller the conduction loss, and vice versa. The leakage current is Since the switch drive circuit 93 controls the gate voltage of the MOS 91 of the 201044782 to zero level, the M〇s 91 still has a slight leakage current flowing between the gate and the source, causing a back-end circuit connected to the switch module. Impact, if it is serious, may also cause malfunction. Therefore, a good switching module must also reduce the adverse effects of conduction loss and leakage current. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a switch drive circuit that reduces switching loss, conduction loss, and leakage current of a transistor switch. Therefore, the switch driving circuit of the present invention is configured to receive a first high level signal to control the transistor switching path, and to receive a zero level: to control the transistor switch to open, the switch driving circuit includes a level a conversion unit and a wheel-out selection unit; the level conversion unit includes an input terminal, a first-output terminal, and a second output $, and the input terminal of the level conversion unit receives the zero-level signal The second output terminal outputs a negative voltage level signal, and when the input terminal receives the first high level signal, a second high level signal is outputted by the first output terminal; the output selection unit is electrically connected The first output 4, the second output terminal, and the gate of the transistor switch 'when the input terminal of the level conversion unit receives the zero level signal, the output selection unit will output the second output The negative pressure level signal outputted by the terminal is transmitted to the pole of the transistor switch to open the transistor switch, and when the input end of the level conversion unit receives the first high level signal, the output selection The unit will have the first output The output of the second high level signal is transmitted to the transistor __ gate, so that the transistor switches the path. Preferably, the level conversion unit of the present invention further includes a second bridge between the first end of the 201044782 bridged between the input and the output of the first round and the second output. The electric switch 'the first end of the first switch is connected to the second switch and the second DC source' is electrically coupled to the zero: the first switch is the high level signal. Pass: two when: the input is received so that 哕筮Φ ^ ^ the first capacitor is charged, the cross-voltage of the first capacitor becomes the first electrical connection, the level, the end of the second switch is received #m古嘴第―轮出端, when the input terminal Ο 〇 receives the first two level signals, the Rong Lei 兮 兮 兮 — — — 开关 开关 开关 开关 开关 开关 开关 开关 开关 开关 开关 开关 开关 开关 开关 开关 开关 开关 开关 开关 开关 开关 开关 开关 开关 开关 开关 开关 开关 开关 开关Become the first - high standard. The first switch described in the preceding paragraph may preferably be a first diode, the anode is electrically connected to the DC source, the cathode is electrically connected to the first output, and the first switch may preferably be a first - 权密. Brother, the anode, the anode is electrically connected to the first output, and the cathode is electrically connected to the ground. Preferably, the relative relationship of the aforementioned levels is that the second high level is twice the first high level, and the negative pressure level is the negative i times of the first high level. More preferably, the switch driving circuit of the present invention outputs a voltage signal to the gate of the MOS switch to control the path and open circuit of the M〇s switch. The function of the invention is that the characteristic of storing electric energy by the capacitor is such that only one DC source inputting the first high-level signal is converted into a second high-level signal output to the transistor switch, or the negative pressure level signal output. For the transistor switch, the second high-level signal higher than the first high-level position allows the transistor switch to have a wider channel width during the path, the switch internal resistance is thus smaller, and the conduction loss is reduced. The negative voltage level signal can make the transistor switch open and its channel is locked tighter and it is more difficult to transmit electricity 201044782, which reduces the leakage current. In addition, the second high level signal and The negative pressure level signal can also make the gate of the transistor switch charge and discharge more quickly', making the switching loss smaller. The above and other technical contents, features, and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments. Referring to FIG. 3, a preferred embodiment of the switch driving circuit 1 of the present invention includes a level conversion unit 1, an output selection unit 2, and a reverse unit 3 (i, _, the switch drive circuit 1 () is available for acceptance - The first-high-level signal is turned on by a control-transistor switch (not shown), and the -zero-level signal is received to control the transistor switch to be turned off. In the following description and diagram, the capacitor Cgs is used. The equivalent transistor switch (in this embodiment, NM〇s is taken as an example) of the gate electric valley 'to illustrate the charge and discharge situation.» The reverse unit 3 includes one side of the mutual electrical connection of the bucks. The source of the SQ1 is electrically connected—the source of the DC source VeQ/the surface of the OS Q2 is electrically connected to the ground terminal 4. In this embodiment, the DC source Vcc provides the first-high-level (5-volt) power signal. And the PM0S Q, and the - OS Q4 gate are used to accept - "" (for example: pulse width modulation signal ' or PWM signal) control, so that the output 31 ' of the reverse unit 3 is based on accepted The square wave outputs the first high-level signal (provided by the DC source Vcc) or the zero-level signal from the output terminal 31. The terminal 4 is provided with an input terminal 13, a first output terminal u and a second output terminal η. The level conversion unit includes - and the turn-out terminal η of the reverse unit 3 is connected to the input terminal 201044782. a first capacitor C1 between the terminal 13 and the first output terminal u, a second capacitor C2 connected between the input terminal 13 and the second output terminal 12, a first diode Di and a second a diode D2; an anode of the first diode Di is electrically connected to the DC source Vcc, and a cathode is electrically connected to the first output terminal 11'. When the input terminal 13 receives the zero-position signal transmitted by the reverse unit 3 No. The first diode Di is turned on, and the first capacitor C1 is charged by the DC source Vcc through the first diode Di, so that the voltage across the first capacitor C1 rises to the first high level. (5 volts); the anode of the second diode D2 is electrically connected to the second output terminal 12, and the cathode is electrically connected to the ground terminal 4. When the input terminal 13 receives the first high level signal, the second diode 〇2 is turned on, and the second electric valley C2 is charged by the DC source Vcc through the PMOS Q, so that the voltage across the second capacitor C2 is also raised to the first high level. 5 volts. The output selection unit 2 has a PMOS Q3 and an NMOS Q4 ' PMOS 〇3 source respectively used as selection switches electrically connected to the first output terminal 11, the gate is electrically connected to the DC source Vcc, the drain Then electrically connecting the gate capacitance Cgs of the transistor switch, and the source of the NMOS Q4 is electrically connected to the second output terminal 12, the gate is electrically connected to the ground terminal 4, and the drain is electrically connected to the gate capacitance of the transistor switch. Referring to FIG. 4 in conjunction with FIG. 3, in the following description and corresponding drawings, the voltage drop of the first diode Di and the second diode D2 is ignored, and it is assumed that the first capacitor Ci and the first capacitor ο are charged. Full, the cross pressure between the two Vei, ν. 2 is the first high level (5 volts), and the definition of the positive and negative directions of each voltage is shown in Figure 3. When the PMOS of the reverse unit 3 is open, and the NM〇s q2 path, the zero-level signal is outputted by the output terminal 31, and the voltage level of the input terminal 201044782 13 of the level conversion unit 同样 is also zero level, The instantaneous transient of the received signal sees 'because of the voltage V across the second capacitor C2. 2 is the first high level (5 volts), and the voltage of the second output terminal 12 electrically connected to the negative terminal of the second capacitor C2 is at a negative voltage level (in the present embodiment, the 'negative pressure level is _ 5 volts), and the second diode D2 is reversed and disconnected, and the gate-source voltage of the NM0S Q4 cross-voltage vgs4 will be the first 咼 level (5 volts), which is greater than the threshold voltage (thresh〇ld voltage) Therefore, the channel between the source and the source of the NMOS Q4 is turned on, and the second output terminal 12 outputs the voltage signal of the negative voltage level to the positive terminal of the gate capacitance Cgs of the transistor switch; in this transient state, due to the first The cross-voltage yd of the capacitor core is also the first high level (5 volts), so the voltage of the first output terminal 丨丨 will be at the first high level, and the gate voltage of the PMOS Q3 will be 〇, greater than the critical value. The threshold voltage, therefore, the channel between the source and the source of PM〇s Q3 is turned off; the positive terminal of the gate capacitance Cgs of the transistor switch finally receives the negative pressure level signal, so that the originally accumulated charge can follow the arrow in FIG. The direction of h is quickly released, and the channel is locked tighter because the gate is at a negative voltage level. To reduce switching losses and reduce leakage current effect. Referring to FIG. 5 in conjunction with FIG. 3, the following description also ignores the voltage drop of the first diode D! and the second diode & and assumes that both the first capacitor g and the second valley c2 are fully charged, both The cross-over voltages ^ and ve2 are both the _ high level (5 volts), and the definition of the positive and negative directions of each cross-pressure is shown in Figure 3. When the reverse π 3 PMOS Q, the path, and the face 〇 s Q2 open, the output 31 outputs the first-to-level level signal, and the voltage level of the input terminal η of the level conversion unit i is also The first high level is based on the transient transient of the received signal. 'Because the voltage across the voltage of the first capacitor C is the first high level (5 volts), the first connection between the 201044782 and the positive terminal of the second valley Ci is first. The voltage at the output terminal u will be at the second high level (in this embodiment, the second high level is 1 volt, that is, twice the first high level), and the first diode (3) is Reverse bias and open circuit, and the PMOS Q3 cross-source crossover Vgs3 will be the negative repeat level b volts, less than the threshold voltage (threshold v〇ltage), so pM〇s Q3 no source channel Turn on 'Let the first output $ U output the voltage signal of the first high level to the positive terminal of the gate capacitance Cgs of the transistor switch; in this transient state, since the cross voltage να of the first electric valley C2 is also the first high The level (5 volts), so the voltage of the second output terminal 12 will be at the zeroth level, and the gate voltage of the NMOS NMOS Q4 will be 疋〇, less than The voltage (thresh〇id, so the channel between the source and the source of the NMOS Q4 is turned off; the positive terminal of the transistor switch Cgs finally receives the second high level signal, which can quickly accumulate in the direction of the arrow I2 in FIG. The charge is increased, and the channel is widened to reduce the switching loss and reduce the conduction loss. It should be noted that the switch driving circuit 1 of the present invention can be applied to the Ρ_switch even if it is mentioned above. The insulating gate bipolar transistor (IGBT) is not limited to this embodiment and its corresponding drawings. Referring to FIG. 6 in conjunction with FIG. 3, FIG. 6 is an experimental measurement waveform. The circuit specifications used in the experiment are: (1) the DC source ν is “5 volts; (2) the first capacitor G and the second capacitor C2 are 4·7 "F; (3) the interpole of the transistor switch The equivalent capacitance Cgs is 0.022 //F; (4) The specification of the reverse unit 3 with PM0S q and NM〇s is MIC4420; (5) The specification of PM0S Q3 is IRLML5103; (6) The specification of NMOS Q4 is NDS335N (?) The first two 201044782 Polar Di and the second diode D2 specifications A 1AKei The n ^ β grid is 1N58l9. The waveform of Figure 疋 is 疋 input square wave vg of 10 kHz, and the wave opening “丨 小 62 is the voltage signal level corresponding to the gate of the transistor switch, high value and The lowest value is -5 volts and 1 分别, respectively, to achieve the output required by the present invention. The amplitude is 15 volts, and the most volt' experimental results prove that, in summary, the effect of the present invention is to utilize the first capacitance & The second capacitor C2 stores the characteristics of the electric energy, so that the DC source Vcc, which originally only has the input of the first high-level signal, is converted into a second high-level signal output to the transistor switch, the negative pressure level signal is output to the transistor switch. When the transistor switch is in the path, the channel width is wider, the internal resistance of the switch is thus smaller, the conduction loss is reduced, and when the transistor switch is broken, the channel is locked tighter and it is more difficult to transmit electrons. In addition, the generation of leakage current is reduced. In addition, the second level signal and the negative voltage level signal can make the gate of the transistor switch charge and discharge more quickly, so that the switching loss is smaller. The above is only the preferred embodiment of the present invention, and the scope of the invention is not limited thereto, that is, the simple equivalent changes and modifications made by the scope of the invention and the description of the invention are All remain within the scope of the invention patent. 10 201044782 [Simple diagram of the diagram] FIG. 1 is a schematic circuit diagram of a conventional switch module; FIG. 2 is a schematic diagram of switching loss generated when the transistor switch is in a switching path or an open state; FIG. 3 is a switch drive circuit of the present invention; FIG. 4 is a schematic circuit diagram of a transistor switch driven by the present embodiment, wherein the transient state is a discharge circuit; FIG. 5 is a transistor switch driven by the embodiment, and the transient state is charged. A schematic diagram of the circuit; and FIG. 6 is an experimental measurement waveform diagram of the present embodiment. 11 201044782 [Description of main component symbols] 10......... Switch drive circuit Ii.........·Discharge current direction Ci......... First capacitor 12... •...Charge current Direction C2......... Second capacitor 1.............. Level conversion unit Cgs........ Transistor switch 11 ·. •... Output terminal gate, etc. Effect capacitor 12··_. ...··Second output terminals Q1, Q3. · PMOS 13•.... •...Input terminal Q2, Q4 _. NMOS 2... •...output selection unit Di....... .. first diode 3.........reverse unit D2......... second diode 31 •...output Vcc........ DC source 4 ...... ..... ground end vg......... square wave 61 .···. •...waveform Vgs x Vgs3 x Vgs4 N Vcl N Vc2 62••... •...waveform crossover 12