201040969 w / w, 29888twf doc/n t · 六、發明說明： 【發明所屬之技術領域】 本發明是有關於—麵作記㈣的方法與記憶體裝 置，且特別是有關於在記憶體裝置中減少第二位元效應 (second bit effect)的方法與記憶體裝置。 【先前技術】 〇 ^圮憶體是一種用來儲存資訊或資料的半導體元件。隨 著電腦微處理器的功能越來越強大，藉由軟體執行的程式 與操作也隨之增加。因此，對於具有高儲存容量記憶體的 需求也逐漸增加。 在各種U己k體產品中，非揮發性記憶體(n〇n_v〇latUe 圮憶體）允許多次的資料程式化(programming)、讀取 (reading)以及抹除(erasing)操作，且甚至在記憶體的電源中 斷之後還能夠保存儲存於其中的資料。由於這些優點，非 揮發性記憶體已成為個人電腦與電子設備中廣泛使用的記 〇 憶體。 熟知的關於電何儲存結構(charge storage structure)的 电子可私式化可抹除（electricaiiy pr〇grammabie and erasable)非揮發性記憶體技術如電子可抹除可程式化唯讀 吕己憶體(electrically erasable programmable read-only 記憶 體’ EEPROM)以及快閃記憶體(flash記憶體）已經使用於 各種現代化應用。快閃記憶體設計成具有記憶胞陣列，其 可以獨立地程式化與讀取。一般的快閃記憶體記憶胞將電 201040969 ry/υιζζ ^888twf.d〇c/n 何，存於洋置閘極(fl〇ating职叫。另—種快閃記 電賴捉結構(如职__ping輕⑽），如—層二 夕(SlN)材料，而非用於浮置閘極元件中的導體門祕 料。當電荷捕捉記憶胞被程式化時且^ 電荷藉由電荷捕捉層來：足= 應電源時保持資料狀態。電= 上胞了以被缝成為二端雜胞(twG_sided _ ^，由於電射會軸㈣料財 此^ 構的快閃記憶體元件中，超過一位元的二::捉f 記憶胞中。 W貝峨存在母-個 /Λ 胞可以被程式化為在電荷捕捉結構 盘ίί;:完全分離的位元(以電荷分別集中靠近源極區 二參&的方式）。記憶胞的程式化可以藉由通道敎 ^rmd h()t eleetn)n ’ _)注入來進行，其在通道區 ‘二 '子。—些熱電子獲得能量而被捕捉在電荷捕捉結構 、。猎將施加至源極端與沒極端的偏壓(㈣互換 =捉至讀捕捉結構的任—部分(靠近祕區、靠近及極 因此’如果沒有㈣齡在記憶射，記憶胞的 二廢(—Id V〇ltage)具有對應位元】與】的组合的 、、如果电荷儲存在電荷捕捉結構中靠近源極區但不 及極區，臨界電壓具有對應位元1與〇的組合的不同值。如 果電荷儲存在靠近祕區对靠近源祕，臨界電壓具有 201040969 ry /υ ιζ / 29888twf.doc/n 另一個值。在此狀況下，臨界電壓對應位元〇與1的組合。 最後，如果電荷儲存在靠近源極區與汲極區，臨界電墨為 最高’且對應位元〇與〇的組合。因此，可以儲存四種不同 的組合(位元00、（H、10與⑴，且每-種組合具有相對應 的臨界電壓。在讀取操作期間，流過記憶胞的電流將取^ •於記憶胞的臨界電壓而改變。典型地，此電流將具有四個 不同值，而每-者對應於不同的臨界電壓。因此，藉由檢 ❹ 測此電流，可以判定儲存於記憶胞中的位元組合。 全部有效的電荷範圍或臨界電難圍可以歸類為記 憶體操作裕度(memory operation wind〇w)。換言之，記憶 體操作裕度藉纟料化轉(level)絲除㈣之間的差里 來定義。由於記憶胞操作需要各種狀態之間的良好位料 離(level s叩aration) ’因此需要大的記憶體操作裕度。然 而，二位兀記憶胞的效能通常隨著所謂的，，第二位元效應” 而降低。在第二位元效應之下，在電荷捕捉結構中定域;；匕 的(localized)電荷彼此互相影響。舉例來說，在反向讀取 Ο (― readi_乍期間’施加讀取偏壓至汲極端且檢測 到儲存在靠近源極區的電荷（即”第一位元,，）。然而，之後 靠収極區的位元（即，，第二位元")產㈣取靠近源極區的 第-位兀的電位障(potential barrier)。此能障可藉由施加適 當的偏縣克服’使驗極感應轉降低咖in_induced barrier bwering，DIBL)效應來抑制靠近汲極區的第二位元 的效應’且允許檢測第-位元的儲存狀態。然而，當靠近 及極區的第一位TL被程式化至高臨界電壓狀態且靠近源極 5 201040969 P970127 29888twf.doc/n 區的第一位元在未程式化狀態時，第二位元實質上提高了 能障。因此，隨著關於第二位元的臨界電壓增加，第一位 元的讀取偏壓已不足夠克服第二位元產生的電位障。因 此，由於關於第二位元的臨界電壓增加，關於第一位元的 臨界電壓也提高，因而降低了記憶體操作裕度。第二位元 效應減少了 2-bit/cell操作的記憶體操作裕度。因此，需要 抑制記憶體元件中的第二位元效應的方法與元件。 【發明内容】 本發明提供一種讀取記憶胞的方法，其可以減輕第二 位元效應。 本發明另提供一種操作記憶胞的方法，其可以縮減操 作裕度。 本發明提出一種操作具有第一資料儲存區（data storage)與第二資料儲存區的記憶胞的方法。此方法包括施 加第一位元線電壓至記憶胞來檢測記憶胞的第一電流。當 第一電流大於關於第一位元線電壓的第一參考電流時，判 定第一資料儲存區為未程式化狀態。當第一電流小於第一 參考電流時，施加第二位元線電壓至記憶胞來檢測記憶胞 的第二電流。然後，當第一電流與第二電流之間的第一差 異大於第一參考電流與第二參考電流之間的第二差異時， 判定第一資料儲存區為未程式化狀態。然而，當第一差異 小於或等於第二差異時，判定第一資料儲存區為程式化狀 態。 29888twf.doc/n 201040969 A / / V ϋ / 依照本發明的實施例，第二位元線電壓與第一位元線 電壓不同。 依照本發明的實施例，第二位元線電壓大於第一位元 線電壓。 依照本發明的實施例，用於檢測第一電流的第一字元 線電壓等於用於檢測第二電流的第二字元線電壓。201040969 w / w, 29888twf doc/nt · VI. Description of the invention: [Technical field of the invention] The present invention relates to a method and a memory device for face-to-face (4), and in particular to reduction in a memory device A second bit effect method and memory device. [Prior Art] 圮 圮 圮 is a semiconductor component used to store information or data. As computer microprocessors become more powerful, the programs and operations that are performed by software increase. Therefore, the demand for memory having a high storage capacity is also gradually increasing. Among various U-k products, non-volatile memory (n〇n_v〇latUe memory) allows multiple programming, reading, and erasing operations, and even The data stored in it can also be saved after the power supply of the memory is interrupted. Because of these advantages, non-volatile memory has become a widely used memory in personal computers and electronic devices. Well-known electronic chargeable eraseable (electricaiiy pr〇grammabie and erasable) non-volatile memory technology such as electronic erasable and programmable only read Luiji recall ( Electrical erasable programmable read-only memory 'EEPROM' and flash memory (flash memory) have been used in a variety of modern applications. The flash memory is designed to have an array of memory cells that can be programmed and read independently. The general flash memory memory cell will be electric 201040969 ry/υιζζ ^888twf.d〇c/n He, stored in the ocean gate (fl〇ating job call. Another - kind of flash flash electric traction structure (such as _ _ping light (10)), such as the layered sang (SlN) material, rather than the conductor gate material used in the floating gate element. When the charge trapping memory cell is programmed and the charge is passed through the charge trapping layer: Foot = The data state should be maintained when the power is supplied. The electricity = the upper cell is sewn into a two-terminal hybrid (twG_sided _ ^, due to the electric radiation axis (4), the flash memory component of the structure is more than one bit. The second:: catch f memory cells. W bellows exist mother-of-one / cell can be programmed into a charge trapping structure ίί;: completely separated bits (with charge separately concentrated near the source region two gins & The way the memory cell can be programmed by the channel 敎^rmd h()t eleetn)n ' _) is injected in the channel area 'two'. - Some of the hot electrons get energy and are captured in the charge trapping structure. Hunting will be applied to the source extremes and no extreme bias ((4) interchange = capture to the capture part of the capture structure - close to the secret zone, close and extremely so 'if there is no (four) age in memory shot, the memory of the two waste (- Id V〇ltage) has a combination of corresponding bits] and if the charge is stored in the charge trapping structure near the source region but not in the polar region, the threshold voltage has a different value of the combination of the corresponding bit 1 and 〇. The charge is stored close to the secret zone and close to the source. The threshold voltage has another value of 201040969 ry /υ ιζ / 29888twf.doc/n. In this case, the threshold voltage corresponds to the combination of the bit 〇 and 1. Finally, if the charge is stored Near the source and drain regions, the critical ink is the highest ' and the corresponding bit 〇 is combined with 〇. Therefore, four different combinations can be stored (bits 00, (H, 10 and (1), and each - The combination has a corresponding threshold voltage. During the read operation, the current flowing through the memory cell will change depending on the threshold voltage of the memory cell. Typically, this current will have four different values, and each Corresponding to different critical voltages Therefore, by detecting this current, the combination of bits stored in the memory cell can be determined. All valid charge ranges or critical electrical difficulties can be classified as memory operation wind〇w. In other words, the memory operation margin is defined by the difference between the leveling and the dividing. Because the memory cell operation requires a good level of s叩aration between the various states, it needs to be large. The memory operation margin. However, the performance of the two-bit memory cells generally decreases with the so-called, second bit effect. Under the second bit effect, the domain is fixed in the charge trapping structure; The localized charges interact with each other. For example, during a reverse read Ο (“readi_乍”, a read bias is applied to the 汲 extreme and a charge stored near the source region is detected (ie, One element, ,.) However, the bit (ie, the second bit ") of the collector region is then taken (4) to take the potential barrier near the first position of the source region. The obstacle can be overcome by applying the appropriate partial county Should reduce the in_induced barrier bwering, DIBL) effect to suppress the effect of the second bit near the bungee region 'and allow the detection of the storage state of the first bit. However, when the first bit TL close to the polar region is programmed When the first bit in the high threshold voltage state is close to the source 5 201040969 P970127 29888twf.doc/n in the unprogrammed state, the second bit substantially increases the energy barrier. Therefore, with respect to the second bit The threshold voltage is increased and the read bias of the first bit is not sufficient to overcome the potential barrier generated by the second bit. Therefore, since the threshold voltage with respect to the second bit increases, the threshold voltage with respect to the first bit also increases, thereby lowering the memory operation margin. The second bit effect reduces the memory operation margin for 2-bit/cell operations. Therefore, there is a need for methods and components that suppress the second bit effect in a memory component. SUMMARY OF THE INVENTION The present invention provides a method of reading a memory cell that can alleviate a second bit effect. The present invention further provides a method of operating a memory cell that can reduce operational margin. The present invention provides a method of operating a memory cell having a first data storage and a second data storage area. The method includes applying a first bit line voltage to a memory cell to detect a first current of the memory cell. When the first current is greater than the first reference current with respect to the first bit line voltage, the first data storage area is determined to be unprogrammed. When the first current is less than the first reference current, the second bit line voltage is applied to the memory cell to detect the second current of the memory cell. Then, when the first difference between the first current and the second current is greater than a second difference between the first reference current and the second reference current, determining that the first data storage area is in an unprogrammed state. However, when the first difference is less than or equal to the second difference, it is determined that the first data storage area is in a stylized state. 29888 twf.doc/n 201040969 A / / V ϋ / According to an embodiment of the invention, the second bit line voltage is different from the first bit line voltage. In accordance with an embodiment of the invention, the second bit line voltage is greater than the first bit line voltage. In accordance with an embodiment of the invention, the first word line voltage for detecting the first current is equal to the second word line voltage for detecting the second current.
依照本發明的實施例，此方法更包括定義記憶胞的程 式化確認電壓(program verify v〇ltage)以及定義記憶胞的低 臨界電壓分佈的上限。此外，程式化確認電壓與低臨界電 壓分佈的上限之間的差異約為600 mV。 本發明另提出一種記憶體裝置。此記憶體裝置包括記 憶體與控制器。記憶體具有多個記憶胞。每—個記憶胞具 有第一資料儲存區與第二資料儲存區。控制器用於對每一 個記憶胞進行讀取步驟〇:切(11吨评〇(^8)。對二每_；個艽俨 步：包括施加第—位元線電屋至記憶胞來檢測‘ =2；7流。當第—電流大於關於第-位元_壓的 流時，判定第—資料儲存區為未程式化狀態。 田弟-電流小於第-參考電流時，施加第二位 讀胞來檢測記的第二電流 、^ 二電流之間的第一差異大於第一參4汽:^=第 態。然而，^ I 未程式化狀 資料儲存_程式化狀態。ί差料，判定第- 本發明又提供一種記憶體裝置。此記憶體裝置包括記 201040969 TO/01^7 2y«88twf.doc/n 憶體、檢測電路與控㈣。記憶體具有多個雜、胞 個記憶胞具有第-資簡存區與第二資料儲存區。檢測電 路用於在讀取步驟期間施加第一位 測記憶胞的第一電流，盆”第電，己憶胞來檢 線电㈣弟-參考電流時，檢測電路施加第二位元線電麗 至記憶胞來檢測記憶胞的第二電流。控制㈣於 化確認電壓而對每-個記憶胞進行讀取步驟。職 ^ 記憶胞，讀取步驟包括檢測第―資料儲存區的第二臨界带 ^ ’然後當第-臨界電壓小於程式化確認電 第二 資料儲存區為未程式化狀態。 t 胞巾的每—個資料儲存區讀取 貝科…在;f同的位元線電壓下目標資料儲存區㈣技 data storage)的臨界電屋分饰的表現用來判定目標資料儲 存區的程式化狀態。目此，即使操偷歧小，甚至操作 裕度不存在(dosed)，當檢測電流小於參考電流時，在第二 位元效應下的具有位元“丨，，的資料儲存區以及^有位元τ =資，存區可以被正破地區別。因此，當記憶胞的尺寸 縮小時’操作裕度將不再是阻礙。此外 於 胞操作的第二位元效應。另外，由於減輕了第二:元;^ 且具有小的操作裕度，因此增加了程式化速度以及減少了 私式化S己憶胞的時間。 為讓本發明之上述特徵和優點能更明顯易懂，下文特 舉實施例，並配合所附圖式作詳細說明如下。 201040969 r 7 / / 29888twf.doc/n 【實施方式】 咅円圖本發明—實施例所緣示的記憶胞的剖面示 W圖如目所不’ δ己憶胞i。。具有基底 102。基底 102 中形成有二個源極級極區W4。記憶胞⑽ 絕 〇8形成於源極她區刚之間的通道 捕1曰In accordance with an embodiment of the invention, the method further includes defining a program verify v〇ltage of the memory cell and defining an upper limit of the low threshold voltage distribution of the memory cell. In addition, the difference between the stylized confirmation voltage and the upper limit of the low-threshold voltage distribution is approximately 600 mV. The invention further provides a memory device. This memory device includes a memory and a controller. The memory has a plurality of memory cells. Each memory cell has a first data storage area and a second data storage area. The controller is used to perform the reading step for each memory cell: cut (11 tons of evaluations (^8). For each of the two _; one step: including applying the first bit line to the memory cell to detect ' = 2; 7 flow. When the first current is greater than the flow with respect to the first bit_pressure, it is determined that the first data storage area is unprogrammed. When the current is less than the first reference current, the second reading is applied. The first difference between the second current and the second current detected by the cell is greater than the first reference 4 steam: ^= the first state. However, the ^I is not programmed data storage_stylized state. The present invention further provides a memory device comprising: 201040969 TO/01^7 2y«88twf.doc/n memory, detection circuit and control (4). The memory has a plurality of memory cells Having a first-storage storage area and a second data storage area. The detection circuit is configured to apply a first current of the first memory cell during the reading step, the basin is "electrically charged, and the memory is recovered by the cell (4) - When the current is referenced, the detection circuit applies a second bit line to the memory cell to detect the second current of the memory cell. Control (4) The reading step is performed for each memory cell by confirming the voltage. The memory cell, the reading step includes detecting the second critical band of the first data storage area, and then when the first threshold voltage is less than the stylized confirmation voltage The data storage area is unprogrammed. t Each data storage area of the cell towel reads Beco... The critical electric house decoration of the target data storage area under the same bit line voltage The performance is used to determine the stylized state of the target data storage area. Therefore, even if the operation is small, even the operation margin does not exist. When the detection current is smaller than the reference current, the second bit effect has The bit "丨,, the data storage area and ^ have the bit τ = capital, the storage area can be distinguished by the ground. Therefore, when the size of the memory cell is reduced, the operational margin will no longer be an obstacle. In addition, the second bit effect of cell manipulation. In addition, since the second: element is reduced and has a small operational margin, the stylization speed is increased and the time for privately revisiting the cell is reduced. The above described features and advantages of the present invention will become more apparent from the description of the appended claims. 201040969 r 7 / / 29888 twf.doc/n [Embodiment] The present invention is a cross-section of a memory cell as shown in the embodiment, and the W image is not as it is. . There is a substrate 102. Two source-level polar regions W4 are formed in the substrate 102. Memory cell (10) 〇8 is formed in the channel between the source and her area.
位於絕緣層108的頂部上，豆驻士切/ ^ 1U Ο Ο IP雜由絕緣層⑽而與基底102 ^離。當熱電子被注人電荷捕捉層⑽ ^，使得記憶胞_的臨界電壓將在控制下被調f 叫與電荷捕捉層上’以將導體間極 極/沒極區辦其中之—具有靠近源 極/汲極區m其中另—儲^區施與靠近源 —位亓的:欠祖。m U储存E 為可程式化，以儲存 中。、貝厂*，—位兀的資料將被儲存在記憶胞100 當程式化第一資料儲ιΐΛ . 閘極m以及靠近第_^1 i 施加電壓至導體 貝料儲存區u〇a的源極/汲極區 〇4,因喊録直雜向的電場 /汲極區104沿記愔睑丨ηΛ ^ 义电卞田乃個源極 區職。當電^通、道而加速遠離第一資料儲存 道動，一些電子得到足夠的能量而 躍過底视緣層1G8的電 區n〇a周圍的電荷捕扭屏”早“工被捕捉在^胃料儲存 的位元被定義鱗計，日1 m巾°，b，當絲式化狀態 電壓增加，且第資料儲存區110a的臨界 枓储存區110a的位元由“丨，，轉變為 9 201040969 P970127 ^y«88twf.doc/n :。’亦t由邏輯狀態轉變為第二邏輯狀態。同樣地， §程式化第二資料儲存區车备 ^ 廿L U0b叶，靶加電壓至導體閘極 14以及罪近弟二資料儲存區u〇b的源極/汲極區1〇4,以 使電子被捕捉在第二資_存區麗周圍的電荷捕捉層 11匕中。一因此，第二資料儲存區議的臨界電壓將增加， 且第二資料儲存區110b的位元由“丨，，轉變為“〇„ 。 圖2為依如本發明一實施例所緣示的記憶體裝置的功 能方塊圖。圖3為圖2中的記憶體裝置的記憶體的電路圖。 如圖2與圖3所示，記憶體裝置2〇〇具有記憶體2〇2、控 制器204、列解碼器、（卿dec〇der)2〇6、行解碼器㈣腿: deC〇der)208、檢測電路21〇以及類比至數位轉換器 (anal〇g-t〇-digitalCOnverter)212。記憶體 2〇2 具有多個記 ^ 胞100(如圖1所示）。記憶體2〇2的記憶胞刚以η列: ^的方式配置成陣列，其中η與m為大於2的整數。控制 裔204耦接至列解碼器206與行解碼器2〇8，以控制記憶 體202的記憶胞1〇〇的操作。類比至數位轉換器Μ]耦接 至控制器施，以將所檢測的電流與參考電流分別轉換為 ，位值的形式。列解碼器206經由記憶體裝置2〇〇的多個 字元線W〇-Wn而施加字元線電壓至記憶胞1〇〇的導體閘極 114。行解碼器208經由記憶體裝置2〇〇的多個位元線 而施加位元線電壓至記憶胞1〇〇。如圖工與圖3所 示，每一個記憶胞100的導體閘極114耦接至字元線;〇w 中-條對應的字元線。每-個記憶胞⑽的源極/^區1 104轉接至位元線B(rBm+i中二條相鄰的位元線。舉例來 201040969 一 ^ …29888twf.doc/n 說，最左上方的記憶胞100的導體閘極耦接至字元線w， 且左上方的記憶胞100的源極/汲極區分別耦接至位元 B0 與 Bi。Located on the top of the insulating layer 108, the bean squirrel / ^ 1U Ο Ο IP is separated from the substrate 102 by the insulating layer (10). When the hot electrons are injected into the charge trapping layer (10)^, the threshold voltage of the memory cell will be adjusted under control and called on the charge trapping layer to make the pole/nopole region between the conductors close to the source. / The bungee area m, the other - the storage area is applied to the source-position: the ancestors. m U stores E as stylized for storage. , Bay Factory*, the data of the location will be stored in the memory cell 100. When the first data is stored, the gate m and the source near the _^1 i are applied to the source of the conductor bead storage area u〇a. / bungee area 〇 4, due to shouting straight electric field / bungee area 104 along the record 愔睑丨 Λ ^ Yidian Putian is a source area. When the electricity is turned on and the road is accelerated away from the first data storage track, some electrons get enough energy to jump over the charge trapping screen around the electric field n〇a of the bottom edge layer 1G8. The bit of the stomach material is defined as the scale, the day 1 m towel °, b, when the wire state voltage increases, and the bit of the critical volume storage area 110a of the data storage area 110a changes from "丨,, to 9 201040969 P970127 ^y«88twf.doc/n :. ' Also convert from logic state to second logic state. Similarly, § stylize the second data storage area vehicle ^ 廿 L U0b leaf, target plus voltage to the conductor gate The source/bungee area of the pole 14 and the sinner 2 data storage area u〇b is 1〇4, so that the electrons are captured in the charge trapping layer 11匕 around the second resource_store area. The threshold voltage of the second data storage area will increase, and the bit of the second data storage area 110b is changed from "丨," to "〇„. 2 is a functional block diagram of a memory device in accordance with an embodiment of the present invention. 3 is a circuit diagram of a memory of the memory device of FIG. 2. As shown in FIG. 2 and FIG. 3, the memory device 2 has a memory 2, a controller 204, a column decoder, a binary decoder, and a row decoder (four) leg: deC〇der) 208. A detection circuit 21A and an analog to digital converter (anal〇gt〇-digitalCOnverter) 212. The memory 2〇2 has a plurality of cells 100 (shown in Figure 1). The memory cells of memory 2〇2 are arranged in an array in the order of n columns: ^, where η and m are integers greater than two. The controller 204 is coupled to the column decoder 206 and the row decoder 2〇8 to control the operation of the memory cell 1 of the memory 202. The analog to digital converter Μ is coupled to the controller to convert the detected current and the reference current into a form of a bit value, respectively. The column decoder 206 applies a word line voltage to the conductor gate 114 of the memory cell 1 via a plurality of word lines W 〇 - Wn of the memory device 2 。. Row decoder 208 applies a bit line voltage to memory cell 1 via a plurality of bit lines of memory device 2A. As shown in Fig. 3, the conductor gate 114 of each memory cell 100 is coupled to a word line; 〇w - the corresponding word line. The source/^ area 1 104 of each memory cell (10) is transferred to the bit line B (two adjacent bit lines in rBm+i. For example, 201040969 a ^29888twf.doc/n says, the top left The conductor gate of the memory cell 100 is coupled to the word line w, and the source/drain regions of the upper left memory cell 100 are coupled to the bit B0 and Bi, respectively.
當從記憶胞100的一個資料儲存區讀取資料資訊時， 經由字元線1|中一條對應的字元線對記憶胞1〇〇的導 體閘極114施加字元線電壓(例如5V)，在讀取操作下將靠 近資料儲存區的源極/汲極區接地(groun(jed)，以及經由位 兀線B〇-Bm+1中一條對應的位元線對靠近另—個資料儲存 區的另一個源極/汲極區施加位元線電壓(例如丨6V)。如圖 1所示’當讀取記憶胞100的第一資料儲存區u〇a的位元 時，對導體閘極114施加字元線電壓，將靠近第一資料儲 存區ll〇a的源極/汲極區104接地，以及對另一個源極/汲 極區104施加第二位元線電壓。如果字元線電壓高於第— 育料儲存區ll〇a的臨界電壓，則源極/汲極區1〇4之間的 通道被開啟(turned on) ’且電流從源極/汲極區1〇4(遠離第 一貧料儲存區ll〇a)經過源極/汲極區1〇4(靠近第一資料儲 存區110a)與位元線BG_Bm+i巾—條對應的位元線而流到檢 測電路21G。然而’如果字元線電壓低於第—資料儲存區 n〇a的臨界電壓，則源極/汲極區1〇4之間的通道被關閉 (turned off) ’且檢測電路21〇將不會檢測到來自記憶胞⑽ 的電流。因此’檢測電路21〇將藉由制來自記憶胞削 的電流來判定第-資料儲存區11〇a的位元的邏輯狀態。同 樣地，、當讀取記憶胞⑽的第二資料儲存區110b的位元 日守’對導體閘極114施加字元線電壓，對源極/汲極區丨〇4(遠 11 201040969 py /υ u / zy688twf.doc/n 離第二資料儲存區110b)施加位元線電壓，以及將源極/汲 極區104(靠近第二資料儲存區ll〇b)接地。如果字元線電 壓高於第二資料儲存區110b的臨界電壓，則源極/汲極區 104之間的通道被開啟，且電流從源極/汲極區1〇4(遠離第 二資料儲存區ll〇b)經過源極/汲極區1〇4(靠近第二資料儲 存區110b)與位元線B(rBm+i中一條對應的位元線而流到 檢測電路210。然而，如果字元線電壓低於第二資料儲存 區110b的臨界電壓，則源極/沒極區1〇4之間的通道被關 閉’且檢測電路210將不會檢測到來自記憶胞1〇〇的電流。 對於一位元儲存的記憶胞(如記憶胞丨〇〇)，至少具有 四種程式化狀態（包括11、〇卜10與⑻）。在此實施例中， 記憶胞的未程式化狀態定義為邏輯“u，’。因此，當第一資 料儲存區與第二資料儲存區皆被程式化時，記憶ς的程式 ^狀態定義為賴‘W，。❹卜，每—個記憶胞的程式化狀 恶可以由對應的臨界分佈來表示14Α為依照本發 明-實施例的當記憶體的記憶胞被程式化而感測到第一電 心夺記憶胞的臨界電壓分佈圖。目4Β為依照本^月一實 =例的當記憶體的記憶胞被程式化而 ^ & ，的臨界電壓分佈圖。如圖4Α所示，二= ，示記憶胞議的第一資料儲存區 ：::車 110b的字元線電壓，而垂直軸表 弟—貧枓儲存£ 料儲存區110a與第二資料儲存區m ^胞1GG的第一資 量。如圖4A所示，第—臨界電 =存的位元的數 程式化狀態的記憶胞⑽的位元^示具有“11，， 曰]t界電壓的分佈。換 12 201040969 29888twf.doc/n 言之，當記憶胞的第一眘耝棘^ ,,,说貝枓储存區與弟二資料儲存區皆為 未私式化狀认弟-臨界電壓分怖搬 式化的位元的低臨界電壓分佈。 L胞的未红 此外，第二臨界電壓分佈404表示具有“ 01，，則 式化狀態的記憶胞100的/、 枉 07位兀1的臨界電壓的分佈。也就 是說，第二臨界電壓分佈4〇4矣_片 _ ^ ^ -次+丨M + r、丄、伸ϋ4表不當弟一貧料儲存區或第 -貝；4儲存a被程式化時記憶胞的未程式化元的臨界電壓 o 〇 分佈。換言之，第二臨界·分佈為在第二位元效應 下5己憶胞的未程式化元的臨界分佈。第三臨界電壓分 佈406表示記憶胞1〇〇的位元“〇，,的臨界電壓的分佈。換言 之，第三臨界電壓分佈偏麵記憶胞的已程式化位元的 b界電壓分佈。 如圖4A所示，第二臨界電壓分佈4〇4除了與第—臨 界電壓t佈402部分重疊之外，還與第三臨界電壓分佈概 部^重疊。麵可知’讀取記憶胞的資料資賴操作裕度 非韦小，甚至不存在。本發明提供了讀取儲存在第一資料 儲存區110a與弟一資料儲存區n〇b其中之一中的資料資 訊的操作方法。藉由應用本發明的操作方法，在第二位元 效應下可以輕易地與資料儲存區的程式化狀態做區別，即 使第二臨界電壓分佈404與第三臨界電壓分佈重疊且讀取 操作的操作裕度不存在。圖5為依照本發明一實施例所繪 不的記憶體的記憶胞的讀取方法的步驟流程圖。當讀取記 憶胞100中第一資料儲存區110a的資料資訊時，控制器 2〇4藉由經由字元線w〇_Wn施加字元線電壓至記憶胞 13 201040969 py/uiz/ zy»88twf.doc/n 的導體閘極114以及在記憶胞loo的源極/没極區之間 施加偏壓來進行讀取步驟。也就是說，藉由將第一位元線 電壓施加至源極/汲極區104(遠離第一資料儲存區11〇幻以 及將靠近第一資料儲存區ll〇b的源極/汲極區1〇4接地來 完成施加在源極/汲極區104之間的偏壓。如圖5所示，在 源極/汲極區104檢測到由第—位元線電壓所引發的第一 電流(步驟S501)。 "在步驟S5G3巾’將第-電流與關於第—位元線電壓 的第一參考電流做比較，且將字元線電壓施加至記憶胞 1〇〇。典型地，對於讀取記憶胞中的資料資訊，施加預定且 固定的字元線電壓至導體閘極114，且施加預定且固定的 線f壓至遠離待讀取的資料儲存區的源極/没極區 耩比車乂所產生的電流與關於字元線 :及施:位元線電壓至記憶胞來將所產生^ 程式化狀態。如果讀取的電流高於參考電流， 判定為—種邏輯狀態（即未程式化狀態）。換古 輯狀態電流’則將娜胞欺為另一種邏 元線：的二步:考:5中’當第-電流大於關於第-位 越高，則臨界電壓=儲存區肠的臨界電壓而言，電流 位元線電流大於關於第- 界電壓小:=4==料儲存區_的臨 爪的參考電壓。如圖4A所示，關 14 29888twf.doc/n 201040969 流電壓高於第—臨界電壓分佈402的上限 臨二Γ物布404，使得具有小於參考電壓的 士 U位7^可以被正確地區分為邏輯“1”，Β、々 錢fG”的位元被岭關定為邏輯“Γ。因此，當^ 100 Ο Ο 資訊被判定為邏輯:;，，時且區110a中的資料 未程式化狀態。，且_胃_存區皮判定為 、斤另ί ϋ f於第二位元效應增加了從目標f料儲存區(鄰 =一帛式化狀態的資料儲存區 ?:因此當所檢測的電流小於參考電流時，不i;;: =目標資料儲存區的資料資訊。就臨界電= 則臨界電壓越高。如圖4A所示， 貝抖储，讀取資料資訊’當所檢 灸； ;壓目=料:=臨界電壓高於關於參考電 ‘二;=:臨界電，之外，在第二位元== 當臨界參考電®的臨界電壓。因此， 儲存區中的位元是否目標資料 圖6A為依照本發明—實施例的在具有多種位元線電 201040969 ry/υιζ/ zy〇88twf.doc/n 壓的未程式化狀態“ 11 ”下記憶胞中資料儲存區的臨界電壓 分佈圖。圖6B為依照本發明一實施例的在具有多種位元 線電壓的程式化狀態“〇〇”下記憶胞中資料儲^的臨界電壓 分佈圖。值得注意的是’圖6A、圖與圖6C中的位元 線電壓變化可以藉由透過外部電源裝置探測(pr〇bing)位元 線的不同電壓來表現。如圖6A所示，不論位元線電壓如 何由IV改變為1.6V與2.3V，“η，，程式化狀態的記憶胞 100的位元“1”的臨界電壓分佈的圖案幾乎都相同。此外， 在排除由於電流隨不同的位元線電壓變化而產生的電壓偏 離係數(voltage deviation factor)之後，關於不同位元線電壓 的Sa界電壓分佈不會彼此偏移開。同樣地，如圖6b所示， 明顯可知，“00”程式化狀態的記憶胞丨00的位元“〇，，的臨界 電壓分佈的圖案幾乎都相同。此外，在排除電壓偏離係數 之後，臨界電壓分佈不會彼此偏移開。值得注意的是，“〇〇，， 程式化狀悲的記憶胞100的位元的臨界電壓分佈與“11” 程式化狀態的記憶胞100的位元“1”的臨界電壓分佈不會 被施加不同位元線電壓而影響。 圖6C為依照本發明一實施例的在具有多種位元線電 ®的程式化狀態“01” / “1〇”下記憶胞中資料儲存區的臨界 電壓分佈圖。如圖6C所示，臨界電壓分佈群組602表示 當位元線電壓由IV改變為1.6V、2.3V與3V時‘‘10，，或“0Γ 程式化狀態的記憶胞1〇〇的位元“〇，，的臨界電壓分佈。此 外’臨界電壓分佈群組604表示當位元線電壓由IV改變 為1.6V、2.3V與3V時“01”或“1〇，，程式化狀態的記憶胞1〇〇 16 29888twf.doc/n 201040969 的位元“l”的臨界電壓分佈。如圖6C所示，明顯可知，在 “ 10”或“01”程式化狀態的記憶胞丨00的位元“〇”的臨界電壓 分佈群組602中，臨界電壓分佈的圖案幾乎相同。此外， 在排除電壓偏離係數之後，臨界電壓分佈不會彼此偏移開。When reading data information from a data storage area of the memory cell 100, a word line voltage (for example, 5V) is applied to the conductor gate 114 of the memory cell through a corresponding one of the word lines 1|, In the read operation, the source/drain region near the data storage area is grounded (groun(jed), and a corresponding bit line pair via the bit line B〇-Bm+1 is adjacent to another data storage area. The other source/drain region applies a bit line voltage (for example, 丨6V). As shown in Fig. 1, when the bit of the first data storage area u〇a of the memory cell 100 is read, the conductor gate is 114 applies a word line voltage to ground the source/drain region 104 near the first data storage region 11a, and a second bit line voltage to the other source/drain region 104. If the word line The voltage is higher than the threshold voltage of the first-batch storage area ll〇a, and the channel between the source/drain region 1〇4 is turned on 'and the current is from the source/drain region 1〇4 ( Far away from the first lean storage area 〇a) through the source/drain region 1〇4 (near the first data storage area 110a) and the bit line corresponding to the bit line BG_Bm+i towel- Go to the detection circuit 21G. However, 'if the word line voltage is lower than the threshold voltage of the first data storage area n〇a, the channel between the source/drain regions 1〇4 is turned off' and the detection circuit 21〇 will not detect the current from the memory cell (10). Therefore, the 'detection circuit 21' will determine the logic state of the bit of the first data storage area 11a by making a current from the memory cell. Similarly, When the bit data of the second data storage area 110b of the memory cell (10) is read, the word line voltage is applied to the conductor gate 114, and the source/drain region is 丨〇4 (far 11 201040969 py /υ u / Zy688twf.doc/n applies a bit line voltage from the second data storage area 110b) and grounds the source/drain region 104 (near the second data storage area 11〇b) if the word line voltage is higher than the second The threshold voltage of the data storage area 110b, the channel between the source/drain region 104 is turned on, and the current flows from the source/drain region 1〇4 (away from the second data storage region 11〇b) through the source/ The drain region 1〇4 (near the second data storage area 110b) and the bit line B (rBm+i corresponding one of the bit lines flow to the inspection Circuit 210. However, if the word line voltage is lower than the threshold voltage of the second data storage area 110b, the channel between the source/potential area 1〇4 is turned off' and the detection circuit 210 will not detect the memory from The current of one cell. For a memory cell (such as memory cell) stored in a single cell, there are at least four stylized states (including 11, 10 10 and (8)). In this embodiment, the memory cell The unprogrammed state is defined as a logical "u,". Therefore, when both the first data storage area and the second data storage area are programmed, the state of the memory program is defined as "W,".程式 , , , , , , , , , , , , , , 程式 程式 程式 程式 程式 程式 程式 程式 程式 程式 程式 程式 程式 程式 程式 程式 程式 程式 程式 程式 程式 程式 程式 程式 程式 程式 程式 程式 程式 程式 程式 程式 程式 程式 程式 程式Critical voltage distribution map. The target voltage distribution map of the memory cell of the memory is programmed according to this ^^^^. As shown in Fig. 4, two =, the first data storage area of the memory cell::: the word line voltage of the car 110b, and the vertical axis cousin - the barren storage material storage area 110a and the second data storage area The first amount of m ^ 1GG. As shown in FIG. 4A, the bit cell of the memory cell (10) of the numbered stylized state of the first critical electric=stored bit has a distribution of voltages of "11,, 曰] t boundary. For 12 201040969 29888twf.doc/n In other words, when the first cell of the memory cell is cautious, it is said that the Bessie storage area and the second data storage area are both non-private and identifiable - the threshold voltage of the threshold voltage is shifted. In addition, the second threshold voltage distribution 404 indicates a distribution of threshold voltages of /, 枉07 bits 兀1 of the memory cell 100 having "01,". That is to say, the second threshold voltage distribution 4〇4矣_片_^^-time+丨M+r, 丄, ϋ4 is not a younger poor storage area or the first-be; 4 storage a is stylized The critical voltage o 〇 distribution of the unprogrammed element of the memory cell. In other words, the second critical distribution is the critical distribution of the unprogrammed elements of the 5 cells under the second bit effect. The third threshold voltage distribution 406 represents the distribution of the threshold voltage of the bit cell "〇," of the memory cell. In other words, the b-th boundary voltage distribution of the programmed bit of the third threshold voltage distribution of the memory cell. As shown in FIG. 4A, the second threshold voltage distribution 4〇4 overlaps with the third threshold voltage distribution portion, in addition to the partial overlap voltage t-distribution 402. It is known that the data memory operation of reading the memory cell is performed. The margin is not small, and does not even exist. The present invention provides an operation method of reading data information stored in one of the first data storage area 110a and the first data storage area n〇b. By applying the present invention The method of operation can be easily distinguished from the stylized state of the data storage area under the second bit effect, even if the second threshold voltage distribution 404 overlaps with the third threshold voltage distribution and the operational margin of the read operation does not exist. 5 is a flow chart of steps of a method for reading a memory cell of a memory according to an embodiment of the present invention. When reading data information of the first data storage area 110a in the memory cell 100, the controller borrows 4 By The word line voltage is applied from the word line w〇_Wn to the conductor gate 114 of the memory cell 13 201040969 py/uiz/ zy»88twf.doc/n and a bias between the source/no-polar region of the memory cell loo Pressing to perform the reading step. That is, by applying the first bit line voltage to the source/drain region 104 (away from the first data storage region 11 and close to the first data storage region 11〇b) The source/drain regions 1〇4 are grounded to complete the bias applied between the source/drain regions 104. As shown in FIG. 5, the first bit line is detected in the source/drain region 104. a first current induced by the voltage (step S501). " In step S5G3, the first current is compared with a first reference current with respect to the first bit line voltage, and the word line voltage is applied to the memory cell 1 Typically, for reading data information in the memory cell, a predetermined and fixed word line voltage is applied to the conductor gate 114, and a predetermined and fixed line f is applied to the data storage area away from the data storage area to be read. The source/no-polar region is compared to the current generated by the rut and the word line: and the application: the bit line voltage to the memory cell will be generated. ^ Stylized state. If the current read is higher than the reference current, it is judged as a logic state (ie, unprogrammed state). In the case of the ancient state current, the two cells are deceived into another logic line: : test: 5 when 'the first current is greater than the first bit, then the threshold voltage = the threshold voltage of the storage zone, the current bit line current is greater than the first boundary voltage: = 4 = = material storage The reference voltage of the zone_'s claw. As shown in FIG. 4A, the turn-off voltage is higher than the upper limit of the first-threshold voltage distribution 402, so that it has a smaller than the reference voltage. Bit 7^ can be divided into logical "1" by the correct region, and the bit of Β, 々钱fG" is determined by the ridge as logical "Γ. Therefore, when the information of ^ 100 Ο 被 is judged to be logical :;,, the data in the area 110a is not programmed. And _ stomach _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ When it is less than the reference current, it is not;;: = information information of the target data storage area. As for the critical power = the higher the threshold voltage, as shown in Fig. 4A, the shock storage, reading the information information 'when the moxibustion; Hook = material: = the threshold voltage is higher than the reference power 'two; =: critical power, in addition, the second bit == when the critical reference voltage is the threshold voltage. Therefore, whether the bit in the storage area is the target Figure 6A is a diagram showing the critical voltage distribution of a data storage region in a memory cell under an unstylized state "11" having a plurality of bit line voltages 201040969 ry/υιζ/ zy〇88 twf.doc/n pressure in accordance with the present invention. Figure 6B is a diagram showing a threshold voltage distribution of data stored in a memory cell under a stylized state "〇〇" having a plurality of bit line voltages in accordance with an embodiment of the present invention. It is noted that 'Figure 6A, Figure and The bit line voltage variation in Figure 6C can be detected by external power supply means (pr〇bing) The different voltages of the bit lines are represented. As shown in Fig. 6A, regardless of the bit line voltage, the IV is changed to 1.6V and 2.3V, "η, the threshold of the bit "1" of the memory cell 100 in the stylized state. The pattern of the voltage distribution is almost the same. In addition, after the voltage deviation factor due to the change of the current with different bit line voltages is excluded, the voltage distribution of the Sa boundary with respect to the voltage of the different bit lines is not biased. Similarly, as shown in Fig. 6b, it is apparent that the pattern of the threshold voltage distribution of the bits of the memory cell 00 of the "00" stylized state is almost the same. In addition, the voltage deviation coefficient is excluded. After that, the critical voltage distributions are not offset from each other. It is worth noting that, "〇〇,, the stylized memory cell 100 has a threshold voltage distribution and the "11" stylized state of the memory cell 100 The threshold voltage distribution of the element "1" is not affected by the application of different bit line voltages. Figure 6C is a stylized state "01" / "1" in a multi-bit line power® according to an embodiment of the invention. Next record The threshold voltage distribution map of the data storage area in the cell is recorded. As shown in FIG. 6C, the threshold voltage distribution group 602 indicates that ''10, or '0' when the bit line voltage is changed from IV to 1.6V, 2.3V and 3V. The threshold voltage distribution of the bit cell of the stylized state is "〇,". In addition, the threshold voltage distribution group 604 represents "01" when the bit line voltage is changed from IV to 1.6V, 2.3V, and 3V. Or "1", the threshold voltage distribution of the bit "1" of the memory cell of the stylized state 1〇〇16 29888twf.doc/n 201040969. As shown in Fig. 6C, it is apparent that at "10" or "01" In the threshold voltage distribution group 602 of the bit "〇" of the memory cell 00 of the stylized state, the pattern of the threshold voltage distribution is almost the same. Furthermore, the threshold voltage distributions are not offset from each other after the voltage deviation coefficient is excluded.
G ❹ 然而’如臨界電壓分佈群組604所示，“1〇”或“〇1，，程 式化狀態的記憶胞1〇〇的位元“:丨，，的臨界電壓分佈的圖案 稍微地扭曲。最重要的是，在排除電壓偏離係數之後，隨 著位元線電壓由IV改變為16V、2 3V與3V，臨界電壓 分佈朝較低的臨界電壓偏移。顯然地，如圖6A、圖6b與 圖6C所示’僅在第二位元效應下的具有位元“1”的資料儲 存區被位元線電塵的改變強烈地影響。也就是說，僅在第 m效j1下的位元“1”臨界電壓分佈將明顯地偏移。因 電壓大於參考電壓時(所檢測的電 存區的資料資訊可以藉由進一步施加不同 線电M，偵測記憶胞的電流的變化而準確地判定。 二位元線4B所不’當大於第—位元線電壓的第 儲存巴)且1 至源極/及極區104(遠離待讀取的資料 =資：電「壓r:同時，檢測到第二電流。二 下的所檢測的電==於在不.同的位元線電壓 因施加不同的位元繞 、3、；電壓偏離係數(藉由 就是說，如圖4A _ 4B所-的參考電流變化表示）。也 4A中的臨界電;就臨界電壓而言，對照圖 輪的臨界電壓分佈概，向右偏:== 17 201040969 尸y/iuz/ ^y588twf.d〇c/n 等於參考電壓差Dr，其關於冬#4 m你一 ώ 考電流變化）。 _於^加不同位碰電壓時的參 如果待讀取的資料館存區為具有第二位 程式化狀態，在不同的〇 _ & + >'應的未 大於_二： 線電壓下所檢測的電流的變化 大於因施加不同的位元線電壓而產生的電 =化 β之’如圖4A與圖4B所示，就臨界電壓而古'，、^ 4Α中的臨界電壓分佈404，在圖4Β中具有第^ 式化狀態的資料儲存區的臨界電壓 線電壓時料料；其關料絲不同位元 1 〇4(遠離第-資料儲存區= <立兀線電壓)至源極/汲極區 以檢測第-f°° U〇a)，且字元線電壓保持相同， 電壓大於第-位元值付心的疋，第二位元線 二電流與第-電Si差2因=_中’將第 同位元線電壓而產生的以:⑽加至記憶胞⑽的不 轉由排除因施加不同的變化做比棱。也就是說， 叛’在施加不同的位元線= 線1壓而產生的電壓偏離係 $見可以被細。目此，“”之娜界電《*佈的真實表 小於或等於關於第=—電流與第〜*t流之間的差異 二位元線電壓的第二電壓的第™參考電流與關於第 存區的臨界電壓分佈不差異時，第-資料儲 因此，第-資料儲存區：口的不、同饭元線電壓影響。 °° a的育料資釩被判定為邏輯 18 29888twf.doc/n 201040969 且第-資料儲存區ma被判定為程式化狀態(步驟 於第二 電流與第一電流之間的差異大於關 間的差異時，第-資料儲存區的臨界電 差分佈θ被所施加的㈣位元線電壓嚴重影響。因此 :資料儲存區_的資料#訊被狀為具有第二位元效G ❹ However, as shown by the threshold voltage distribution group 604, the pattern of the threshold voltage distribution is slightly distorted by "1" or "〇1, the bit of the memory cell of the stylized state": 丨, . Most importantly, after the voltage deviation factor is removed, the threshold voltage distribution is shifted toward a lower threshold voltage as the bit line voltage is changed from IV to 16V, 2 3V, and 3V. Obviously, the data storage area having the bit "1" under the second bit effect only as shown in Figs. 6A, 6b and 6C is strongly influenced by the change of the bit line electric dust. That is to say, the bit "1" threshold voltage distribution only under the mth effect j1 will be significantly shifted. When the voltage is greater than the reference voltage (the data information of the detected electrical storage area can be accurately determined by further applying different line charges M to detect the change of the current of the memory cell. The two-bit line 4B is not 'larger than the first - the first storage of the bit line voltage) and 1 to the source / and the polar region 104 (away from the data to be read = capital: electricity "voltage r: at the same time, the second current is detected. The second detected power == In the same bit line voltage due to the application of different bit windings, 3,; voltage deviation coefficient (by saying, as shown in Figure 4A _ 4B - reference current change). Also in 4A Critical power; in terms of the threshold voltage, the critical voltage distribution of the reference wheel is approximately to the right: == 17 201040969 The corpus y/iuz/ ^y588twf.d〇c/n is equal to the reference voltage difference Dr, which relates to winter #4 m you ώ test current change). _ ^ ^ when the voltage is different when the voltage is read, if the library storage area to be read has a second stylized state, in different 〇 _ & + > Not greater than _ 2: The change in current detected at the line voltage is greater than the power generated by applying different bit line voltages. As shown in FIG. 4A and FIG. 4B, the threshold voltage distribution 404 in the threshold voltage and the threshold voltage 404 in the data storage region of the data storage region in the state of FIG. Material; its off wire different bits 1 〇 4 (away from the first - data storage area = < vertical line voltage) to the source / drain area to detect the -f ° ° U 〇 a), and word line The voltage remains the same, the voltage is greater than the value of the first-bit value, the second bit line two current and the first-electro-Si difference 2 due to =_ in the 'the same bit line voltage generated by: (10) added to the memory The non-transition of the cell (10) is excluded by the application of different changes. That is to say, the voltage deviation caused by the application of different bit lines = line 1 pressure can be fined. Thus, "" The real table of the "Nanbu" is less than or equal to the TM reference current of the second voltage of the difference between the current and the **t stream and the threshold voltage of the second storage area When there is no difference in distribution, the first-data storage, therefore, the first-data storage area: the mouth does not, the same as the rice line voltage. ° ° a breeding material vanadium is judged as Logic 18 29888twf.doc/n 201040969 and the first-data storage area ma is determined to be stylized (stepwise when the difference between the second current and the first current is greater than the difference between the two, the critical data of the first-data storage area) The difference distribution θ is seriously affected by the applied (quad) bit line voltage. Therefore: the data storage area_data# is shaped to have the second bit effect
應的邏輯1，，’且第—資料儲存區施被判定為未程式化 狀態（步驟S505)。 圖7為依照本發明-實施例所緣示的定義製程裕度的 =驟流程圖。如圖7所示’在第一資料儲存區u〇a或第二 資料儲存區1 l〇b被讀取或程式化之前，本發明更包括定義 5己憶胞的低臨界電壓分佈的上限的步驟(步驟S7〇l)以及定 義記憶胞的程式化確認電壓的步驟(步驟S7〇3)。明顯地， 程式化確認電壓與記憶胞的低臨界電壓分佈的上限之間的 差異可以小如600 mV。此外，步驟S701與步驟S703進 行順序並不能改變。 圖8為依照本發明一實施例所繪示的記憶體的記憶胞 的5賣取方法的步驟流程圖。在本發明的另—實施例中，如 圖8所示’檢測由施加至源極/丨及極區1 〇4(遠離待讀取的資 料儲存區）的第一位元線電壓所引起的第一電流（步驟 S801)。然後’在步驟S803中，將第一電流與關於第一位 元線電壓與施加至記憶胞1〇〇的字元線電屢的第一參考電 流分別類比至數位轉換為第一電流數位值與第一參考數位 19 201040969 v^nnn /y«88twf.d〇c/n 值，以進行紀錄。在步驟S8〇5中，將第—電流數位值第 一參考數位值進行比較，以判定待讀取的資料儲存區的程 ^化狀態。當第一電流數位值大於第一參考數位值時，待 項取的資料儲存區被判定為未程式化狀態(步驟S8〇7)。另 一方面，當第一電流數位值小於第一參考數位值時，資料 儲存區無法被確實地判定是否為程式化狀態或具有第二位 元效應的未程式化狀態。 此外，如圖8所示，在步驟S8〇9中，當第一電流數 ，值小於第-參考數位值日夺，施加第二位元線電壓(不同於 第一位兀線電壓)至源極/汲極區丨〇4(遠離待讀取的資料儲 存區）’且字兀線電壓保持相同，以檢測第二電流。然後， 在步驟S811中，將第二電流與關於第二位元線電齡施 加至記憶胞100的字元線電壓的第二參考電流分別類比至 數位轉換為第二電流數位值與第二參考數位值，以進行紀 錄。此外，在步驟S813中，判定待讀取的資料儲存區程 的式化狀悲。也就是說，將第二電流數位值與第一電流數 位值之間的差異以及施加至記憶胞1〇〇的不同位元線電壓 所產生的參考數位值變化做比較。如果第二電流數位值與 第-電流數位值之間的差異小於或等於第一參考數位值與 第二參考數位值之間的差異，則列定待讀取的資料儲存區 為程式化狀態(步驟S815)。如果第二電流數位值與第一電 流數位值之間的差異大於第-參考數位值與第二袁考數位 值之間的差異，則判定待讀取的資料儲存區為具有第二位 元效應的未程式化狀態（步驟S807)。 20 201040969 x / / …心，298S8twf.doc/π 在本發明中，當從記憶胞的每_個資料儲存區讀取資 料時，將在不同位元線電壓下目標資料儲存區的臨界電屢 分佈的表現用來判定目標資料儲存區的程式化狀態。因 此，即使操作裕度很小或甚至不存在，當檢測電流小於參 考電流時，纟第二位元效應下的具有位元“Γ,的資料館存區 以及具有位元“〇”的資料儲存區可以被正確地區分。因此， 對於縮小記憶胞的尺寸來說’操作裕度將不再是阻礙。此 〇 外、，對於記憶胞操作的第二位元效應也被減輕。另外，由 於減輕了第一位元效應且操作裕度很小，因此增加了程式 化速度，以及縮短了程式化記憶胞的時間。 工 雖然本發明已以實施例揭露如上，然其並非用以限定 本發明，任何所屬技術領域中具有通常知識者，在不脫離 本發明之精神和範圍内，當可作些許之更動與潤飾，故 發明之保護範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 立圖1為依照本發明-實施例所繪示的記憶胞的剖面示 思、圖。 处圖2為依照本發明一實施例所繪示的記憶體裝置的功 月匕方塊圖。 圖3為圖2中的記憶體裝置的記憶體的電路圖。 。、圖4Α為依照本發明一實施例的當記憶體的 程式化而感測到第一電流時記憶胞的臨界電壓分^ 。 圖4Β為依照本發明一實施例的當記憶體二記=胞被 21 201040969 P970I27 29888twf.doc/n 程式化而感測到第二電流時記憶胞的臨界電壓分佈圖。 圖5為依照本發明一實施例所繪示的記憶體的記憶胞 的讀取方法的步驟流程圖。 圖6A為依照本發明一實施例的在具有多種位元線電 壓的未程式化狀態“11”下記憶胞中資料儲存區的臨界電壓 分佈圖。 圖6B為依照本發明一實施例的在具有多種位元線電 壓的程式化狀態“00”下記憶胞中資料儲存的臨界電壓分佈 圖。 圖6C為依照本發明一實施例的在具有多種位元線電 壓的程式化狀態“01” / “10”下記憶胞中資料儲存區的臨界 電壓分佈圖。 圖7為依照本發明一實施例所繪示的定義製程裕度的 步驟流程圖。 圖8為依照本發明一實施例所繪示的記憶體的記憶胞 的讀取方法的步驟流程圖。 【主要元件符號說明】 100 :記憶胞 110a :第一資料儲存區 110b ··第二資料儲存區 102 :基底 104 :源極/汲極區 108、112 :絕緣層 22 201040969 29888twf.doc/n 110 電荷捕捉層 114 導體閘極 200 記憶體裝置 202 記憶體 204 控制器 206 列解碼器 208 行解碼器 210 檢測電路 212 類比至數位轉換器 402 第一臨界電壓分佈 404 第二臨界電壓分佈 406 第三臨界電壓分佈 602、604 :臨界電壓分佈群組 B〇-Bm+i .位元線 D；l、D2 :電壓差 Dr :參考電壓差 〇 S501-S5n、S701-S703、S801-S815 :步驟 w0-wn:字元線 23The logic 1, 'and the first data storage area is determined to be unprogrammed (step S505). Figure 7 is a flow chart showing the definition of process margin in accordance with an embodiment of the present invention. As shown in FIG. 7 , before the first data storage area u〇a or the second data storage area 11b is read or programmed, the present invention further includes defining an upper limit of the low threshold voltage distribution of the 5 memory cells. The step (step S7〇1) and the step of defining the stylized confirmation voltage of the memory cell (step S7〇3). Obviously, the difference between the stylized confirmation voltage and the upper limit of the low threshold voltage distribution of the memory cell can be as small as 600 mV. Further, the order of steps S701 and S703 cannot be changed. FIG. 8 is a flow chart showing the steps of a method for selling a memory cell of a memory according to an embodiment of the invention. In another embodiment of the present invention, as shown in FIG. 8, 'detection is caused by the first bit line voltage applied to the source/germanium and the pole region 1 〇4 (away from the data storage region to be read). The first current (step S801). Then, in step S803, the first current is analogized with the first reference current with respect to the first bit line voltage and the word line applied to the memory cell, respectively, to digital conversion to the first current digital value and The first reference digit 19 201040969 v^nnn /y«88twf.d〇c/n value for recording. In step S8〇5, the first reference digit value of the first current digit value is compared to determine the process state of the data storage area to be read. When the first current digit value is greater than the first reference digit value, the data storage area to be retrieved is determined to be unprogrammed (step S8 - 7). On the other hand, when the first current digit value is smaller than the first reference digit value, the data storage area cannot be reliably determined whether it is a stylized state or an unprogrammed state having a second bit effect. In addition, as shown in FIG. 8, in step S8〇9, when the first current number is smaller than the first reference digital value, the second bit line voltage (different from the first bit line voltage) is applied to the source. The pole/drain region 丨〇4 (away from the data storage area to be read)' and the word line voltage remains the same to detect the second current. Then, in step S811, the second current is analogized to the second reference current of the word line voltage applied to the memory cell 100 with respect to the second bit line age to the digital conversion to the second current digital value and the second reference, respectively. Digital value for recording. Further, in step S813, it is determined that the pattern of the data storage area to be read is sad. That is, the difference between the second current digit value and the first current digit value and the reference digit value change produced by the different bit line voltages applied to the memory cell 1〇〇 are compared. If the difference between the second current digit value and the first current digit value is less than or equal to the difference between the first reference digit value and the second reference digit value, then the data storage area to be read is listed as a stylized state ( Step S815). If the difference between the second current digit value and the first current digit value is greater than a difference between the first reference digit value and the second meta-digit value, determining that the data storage area to be read has a second bit effect The unprogrammed state (step S807). 20 201040969 x / / ... heart, 298S8twf.doc / π In the present invention, when reading data from each data storage area of the memory cell, the critical power of the target data storage area under different bit line voltages The performance of the distribution is used to determine the stylized state of the target data store. Therefore, even if the operation margin is small or even absent, when the detection current is smaller than the reference current, the data storage area having the bit "Γ" under the second bit effect and the data storage area having the bit "〇" It can be correctly distinguished. Therefore, the operation margin will no longer be an obstacle to reducing the size of the memory cell. This second, the second bit effect on the memory cell operation is also alleviated. The first bit effect and the operation margin are small, thus increasing the stylization speed and shortening the time of the stylized memory cell. Although the invention has been disclosed above by way of example, it is not intended to limit the invention, any It is to be understood by those skilled in the art that the scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view and a diagram of a memory cell according to an embodiment of the present invention. FIG. 2 is a memory diagram according to an embodiment of the invention. Figure 3 is a circuit diagram of the memory of the memory device of Figure 2. Figure 4 is a schematic diagram of the memory when the first current is sensed in accordance with an embodiment of the present invention. The critical voltage of the memory cell is divided into. Figure 4 is a threshold voltage distribution of the memory cell when the second memory of the memory is stylized by the memory of the memory of the memory device 21 201040969 P970I27 29888twf.doc/n according to an embodiment of the invention. Figure 5 is a flow chart showing the steps of a method for reading a memory cell of a memory according to an embodiment of the invention. Figure 6A is an unprogrammed circuit having a plurality of bit line voltages according to an embodiment of the invention. FIG. 6B is a threshold voltage distribution of data storage in a memory cell under a stylized state “00” having a plurality of bit line voltages according to an embodiment of the invention. FIG. Figure 6C is a diagram showing a threshold voltage distribution of a data storage area in a memory cell under a stylized state "01" / "10" having a plurality of bit line voltages in accordance with an embodiment of the present invention. One real FIG. 8 is a flow chart showing the steps of a method for reading a memory cell of a memory according to an embodiment of the invention. [Description of main component symbols] 100: Memory cell 110a: first data storage area 110b · second data storage area 102: substrate 104: source/drain region 108, 112: insulating layer 22 201040969 29888twf.doc/n 110 charge trapping layer 114 conductor gate 200 Memory device 202 memory 204 controller 206 column decoder 208 row decoder 210 detection circuit 212 analog to digital converter 402 first threshold voltage distribution 404 second threshold voltage distribution 406 third threshold voltage distribution 602, 604: threshold voltage Distribution group B〇-Bm+i. Bit line D; l, D2: voltage difference Dr: reference voltage difference 〇S501-S5n, S701-S703, S801-S815: step w0-wn: word line 23