201040717 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種記憶體裝置之管理方法，特別關 於一種可優化快閃記憶體裝置之讀寫操作性能之方法。 【先前技術】 快閃記憶體（flash memory)為一種特殊種類的非揮發性 (nonvolatile)記憶體，其可儲存資料以及被電性抹除。以快 閃記憶體為基礎之儲存裝置具有低功率耗損，並且與以磁 碟記憶體為基礎的儲存裝置相比，具有相對小的尺寸。因 此，快閃記憶體裝置目前為一些手持電子計算裝置中經常 被使用的記憶體裝置，例如數位相機、手機或個人數位助 理（personal digital assistants，PDA)等。 在磁碟記憶體裝置中，新的資料可覆寫舊的資料。然 而，在快閃記憶體裝置中，若要更新先前儲存的資料，必 須先將一區塊(block)範圍進行抹除，即，快閃記憶體裝置 的讀取與寫入操作的單位可以是以頁（page)或區段（sector) 為基礎，而抹除操作的最小單位為區塊。因此，抹除操作 通常比寫入與讀取操作需要更多的時間。此外，由於區塊 的大小遠大於頁與區段，即使區塊内不需被寫入的部分也 要同時被抹除。 傳統技術中改善讀寫操作性能的方法為透過介質管 理層，使用映射的方式，當需要修改某一區塊内儲存的 資料時’在糸統内取得另·一個可用區塊（通常稱此區塊 為log區塊），用以儲存該區塊之修改紀錄，如此一來， 每當需要修改該區塊之資料時，僅需將修改資料儲存至 VTU09-0009/0608-A41979TWf / 4 201040717 的log區塊’即可避免必須抹除一整 =資料内容，必須自w區塊的末端 (丽）％區塊内所儲存的資料，這樣—來，择加 多不必要的資料讀取操作，更降低了讀取的速曰度。許 因此’需要-種新的快閃記憶體管理方法 閃記憶體裝置之讀寫操作性能，使得 ^ 操作速度可大幅地被提升。 體裝置之4寫 〇 【發明内容] 用以3本之一實施例，—種快閃記憶體管理方法， :憶體裝置，其中該快閃記憶體裝置配置 、射區塊、至少一修改區塊以及至少一快 包括.接收包含一寫入邏輯位址與一既定資料之 ’匕 令’用以寫入該既定資料至該快閃記憶體裝以及t 其中當對應於該寫入邏輯位址::映 〇經被使用’則寫入該既定資料於該修改區塊之一空白頁， =塊ί據邏輯位址由該快取區塊讀取對:於該修 改q塊之一快取頁至—隨機存取記憶體裝置 =憶體裝置内依序讀取該快取頁之資料棚位以= 白頁於該修改區塊内之位置資訊，其中該快取 = 取頁具有複數資料攔位用以依序儲存該修 = 白，所寫入之資料所對應之該位置資訊;以及 貝訊寫入該既定資料於該修改區塊之該空白“ 根據本發明之另一#/ 。 貫施例種快閃記憶體管理方 VTU09-0009/0608-A41979TWf / 〇 。 201040717 法，用以管理一快閃記憶體裝 配置至少一映射區塊、至少二夂，其中該快閃記憶體裝置 塊，包括：接收包含一讀取邏=改區塊以及至少一快取區 該快閃記憶體裝置之一百靖％ D位址之一讀取指令用以由 只項取—g乐— 於該讀取邏輯位址之該映射區土足疋資料；以及判斷對應 其中當對應於該讀取邏輯位^之〜頁疋否已經被使用。 經被修改過，則於對應於該映=讀映射區塊之頁的資料已 該既定資料，包括：根據該讀取區崠之該修改區塊中讀取 取對應於該修改區塊之一°快°取邏輯位址由該快取區塊讀 置，於該隨機存取記憶體裝、^頁至一隨機存取記憶體裝 欄位以獲得對應於該讀取邏内依序讀取該快取頁之資料 -位置資訊，其中該快取區，之頁於該修改區塊内之 位用以依序儲存該修改區塊各快取頁具有複數資料攔 對應之該位置資訊；以及依掳非空白頁所寫入之資料所 該頁讀取該既定資料。 位置資訊於該修改區塊之 根據本發明之另一實施例，一 快閃記憶體、-隨機存取記憶體:置::機包:: 記憶體配置至少-映射區冑 乂及處理盗。快閃 快取區塊。處理_接至該快，f，修改區塊以及至少-體裝置，接收包含-錢體與賴機存取記憶 令，當對應於該寫人邏輯=位址與既定資料之一寫入指 使用’則根據該寫入邏輯位丨之該映射區塊之一頁已經被 修改區塊之一快取頁至該址由該快取區塊讀取對應於該 機存取記憶體裝置内依序存取記憶體裝置，並於該隨 修改區塊内之一空白貢之位讀取該快取頁之内容以獲得該 VTU09-0009/0608-A41979TWf / 置^ 5凡’以及依據該位置資訊 201040717 寫入該既^資祕姉㈣狀Μ 塊之各快取頁具有複數資料攔位用以儲取區 之各非空白頁所寫人之資料所對應之該修改區塊 根據本發明之另-實施例一 快閃記憶體、-隨機存取記憶體裝置以:機=包:- :=Τ一映射區塊、至少-修改區=至= 快取£塊。處理器耦接至 ^ Ο201040717 VI. Description of the Invention: [Technical Field] The present invention relates to a method of managing a memory device, and more particularly to a method for optimizing read and write performance of a flash memory device. [Prior Art] Flash memory is a special kind of nonvolatile memory that can store data and be erased electrically. Flash memory-based storage devices have low power consumption and are relatively small in size compared to disk memory based storage devices. Therefore, flash memory devices are currently used in some handheld electronic computing devices, such as digital cameras, cell phones, or personal digital assistants (PDAs). In the disk memory device, new data can overwrite old data. However, in the flash memory device, in order to update the previously stored data, a block range must be erased first, that is, the unit of the read and write operations of the flash memory device can be Based on a page or sector, the smallest unit of the erase operation is a block. Therefore, the erase operation usually takes more time than the write and read operations. In addition, since the size of the block is much larger than the page and the segment, even the portion of the block that does not need to be written is also erased at the same time. In the conventional technology, the method for improving the performance of the read and write operation is to use the mapping management mode through the medium management layer, and when the data stored in a certain block needs to be modified, an additional available block is obtained in the system (generally called this area). The block is a log block) for storing the modified record of the block, so that whenever the data of the block needs to be modified, only the modified data needs to be stored in VTU09-0009/0608-A41979TWf / 4 201040717 Log block 'can avoid having to erase a whole = data content, must be stored in the end of the w block (Li)% of the block, so - to add more unnecessary data read operations, It also reduces the speed of reading. Therefore, there is a need for a new flash memory management method. The read/write operation performance of the flash memory device enables the operation speed to be greatly improved. 4 writing device [invention] for one of the three embodiments, a flash memory management method, a memory device, wherein the flash memory device configuration, the shot block, at least one modified area And the block and the at least one fast include: receiving a command to write the logical address and a predetermined data to write the predetermined data to the flash memory device and t when corresponding to the write logical address :: Mirror is used to write 'the specified data to a blank page of the modified block, = block ο logical address is read by the cache block: one of the modified q block cache Page to - random access memory device = sequentially read the data store of the cache page in the memory device to = position information of the white page in the modified block, wherein the cache = the page has multiple data The block is used to sequentially store the repaired white, the location information corresponding to the written data; and the blank in which the predetermined data is written in the modified block, "another #/ according to the present invention. A case of flash memory management VTU09-0009/0608-A41979TWf / 〇. 201040717 For managing a flash memory device configuration, at least one mapping block, at least two, wherein the flash memory device block comprises: receiving a read logic = modified block and at least one cache area. One of the flash memory devices is a read command for reading from the item - g music - the mapping area of the logical address is read; and the corresponding one is corresponding to the The read logical bit ^~page has been used. After being modified, the data corresponding to the page corresponding to the map=read mapping block has the established data, including: the modification according to the read area The read in the block corresponds to one of the modified blocks. The logical address is read by the cache block, and the random access memory is loaded into the random access memory. Bits are used to obtain data-location information corresponding to the cache page sequentially reading the cache page, wherein the cache area, the page in the modified block is used to sequentially store the modified block The cache page has the location information corresponding to the plurality of data blocks; and the non-blank pages are written The page reads the predetermined data. The location information is in the modified block according to another embodiment of the present invention, a flash memory, a random access memory: set:: package:: memory Configuring at least - mapping area 处理 and handling thieves. Flash Cache block. Processing _ to the fast, f, modify the block and at least the body device, receiving the inclusion - money body and the device access memory command, when Corresponding to the write logic = address and one of the established data, the write refers to the use of 'the one of the mapped blocks according to the write logic bit 快 the page has been modified to cache the page to the address by the The cache block read corresponds to the sequential access memory device in the machine access memory device, and reads the content of the cache page in the blank block of the modified block to obtain the VTU09. -0009/0608-A41979TWf / Set ^ 5 凡 'and according to the location information 201040717 write the ^ 姊 姊 四 四 四 四 四 四 之 之 之 之 之 之 之 之 各 各 各 各 各 各 各 各 各 各 各 各 各 各 各 各 各 各 各 各 各 各 各 各 各 各 各 各The modified block corresponding to the data of the written person according to another embodiment of the present invention - flash memory , - random access memory device: = Pack machine: -: = Τ a mapping block, at least - to the modification area = £ = cache block. The processor is coupled to ^ Ο
體裝置，接收~入β 、 s μ體與該隨機存取記憶 體衮置魏包含一讀取邏輯位址之 於該讀取邏輯位置之該映射區 取才”田對應 、Ά m] ^ 射c塊之一頁的資料已經被修改 該讀取邏輯位址由該快取區塊讀取對應於該修 改£塊之-快取頁至該隨機存取 存取記憶體裝置㈣;^ 隨機 序讀取該快取頁之内容以獲得對應於 該讀取邏輯位址之該頁於該修改區塊内之一位置資訊，以 及依據該位置資訊於該修改區塊之該頁讀取該既定資料， 其中該&取區塊之各快取頁具有複數資料棚位用 以依序儲 予該修改ϋ塊之各非空白頁所寫人之資料所對應之該 資訊。 根據本發明之另—實施例，一種快閃記憶體管理方 法’用以管理一快閃記憶體裝置，其中該快閃記憶體裝置 配置至少一映射區塊、至少一修改區塊以及至少一快取區 塊。快閃s己憶體管理方法包括：接收一包含一邏輯位址之 存取指令，用以於該快閃記憶體裝置存取一既定資料；以 及當對應於該邏輯位址之該映射區塊之一頁不適於存取該 既定資料，則對與該映射區塊對應之該修改區塊進行存取 操作，包括：由該快閃記憶體裝置之該快取區塊讀取對應 VTU〇9-〇〇〇9/〇608-A41979TWf/ n 201040717 於該修改區塊之一快取頁至一隨機存取記憶體裳置，於該 隨機存取記憶體裝置内依序讀取該快取頁之内容以押得= 既定資料於該修改區塊内之存取位置資訊，其中該快取: 塊之各快取頁具有複數資料攔位用以依序儲存該修改區塊 之各非空白頁所寫入之資料所對應之該位置瞀却.、， 只机，以及依 據該存取位置資訊與該快閃記憶體裝置之修改區塊内存取 該既定資料。 【實施方式】 為使本發明之製造、操作方法、目標和優點能更明顯 易懂，下文特舉幾個較佳實施例，並配合所附圖式，詳 細說明如下： $ # 實施例： 第1圖係顯示根據本發明之一實施例所 統100’包括快閃記憶體1〇1、處理器1〇2以及 己 憶體裝置103 °處理器102根據接收到的指令以及;= 行既定之程式竭管理快閃記憶體101 施例，快閃記憶體1〇1 W|、，β目女 ^ 设月之貫 HA Α 是具有一次可抹除資 次可寫人資料之最小單位之特性之—種j體 裝置’例如NAND型或舰型快閃記憶體。快閃:己體 101可被配置至少-映射區塊、修改區塊以及快 其中對於NAND跡…Α &取&塊 、4 °己憶體而5，映射區塊、修改區塊 \ 、品土可分別包括複數頁（Page)，而對kN〇r型快 閃》己s ’映射區塊、修改區塊以及快取區塊可分別 已，複數H*k(seet〇i·)。,為了簡丨該見，本說明書將統一使 用頁」進行相關的描述，然而值得注意的是，其並非用 VTU09-0009/0608-A41979TWf / 201040717 以限定本發明的範圍，任何熟習此項技藝者，在不脫離本 發明之精神和範圍内，當可做些許的更動與潤飾，用以將 本發明之精神應用同時於各種快閃記憶體。 根據本發明之一實施例，映射區塊之各頁用以儲存原 始資料，並且映射區塊可具有至少一對應之修改區塊，用 以當原始資料需被更改時，於該修改區塊之各頁儲存原始 資料之更新内容，並且各修改區塊可對應於至少一快取區 塊之一頁，用以儲存修改區塊所寫入之資料之位置資訊。 右各負料攔位使用2 byte紀錄位置資訊 Ο 第2圖係顯示根據本發明之一實施例所述之快閃記憶體之 資料結構示意圖。如圖所示，快閃記憶體200可被配置複 數個快取區塊201、複數個映射區塊2〇2以及複數個修改 區塊203。快取區塊201之各頁分別包括一資料區域與一 冗餘區域’資料區域可包含複數資料攔位，用以依照對應 之修改區塊之頁順序儲存修改區塊的各非空白頁之位置資 訊。以256百萬位元組(MB)之快閃記憶體為例，可配置2〇48 個區塊，各區塊大小為128KB，並且各區塊可包含256頁（或 區段）’各頁之資料區域大小為512位元組(byte)，並具有 對應之16byte之冗餘區域。因此，根據本發明之一實施例， 之各頁之資料區域可分成256個資料欄位，足以完整紀錄 一修改區塊之各1之所有位置資訊，而快取區塊201The body device receives the ~in β, s μ body and the random access memory device, and includes a read logical address at the read logical position of the mapping region, and corresponds to the field, Ά m] ^ The data of one page of the c block has been modified. The read logical address is read by the cache block from the cache block corresponding to the modified block to the random access memory device (4); ^ random sequence Reading the content of the cache page to obtain location information of the page corresponding to the read logical address in the modified block, and reading the predetermined data according to the location information of the modified block Each of the cache pages of the & block has a plurality of data sheds for sequentially storing the information corresponding to the data of the non-blank pages of the modified block. According to the present invention - In an embodiment, a flash memory management method is configured to manage a flash memory device, wherein the flash memory device is configured with at least one mapping block, at least one modified block, and at least one cache block. The method of managing the memory includes: receiving one containing a logical bit And an access instruction for accessing a predetermined data to the flash memory device; and when a page corresponding to the logical address of the mapping block is not suitable for accessing the predetermined data, the mapping area is The accessing operation corresponding to the modified block includes: reading, by the cache block of the flash memory device, a corresponding VTU〇9-〇〇〇9/〇608-A41979TWf/n 201040717 in the modified area One of the blocks caches the page to a random access memory, and sequentially reads the contents of the cache page in the random access memory device to obtain the access of the predetermined data in the modified block. Position information, wherein the cache: each cache page of the block has a plurality of data intercepts for sequentially storing the location corresponding to the data written by each non-blank page of the modified block. And accessing the predetermined data according to the access location information and the modified block of the flash memory device. [Embodiment] In order to make the manufacturing, operation methods, objectives and advantages of the present invention more obvious, the following Several preferred embodiments, with the accompanying drawings The detailed description is as follows: $ # Embodiment: FIG. 1 shows a system 100' including a flash memory 1〇1, a processor 1〇2, and a memory device 103° according to an embodiment of the present invention. The received command and the == line of the program to manage the flash memory 101 instance, flash memory 1〇1 W|,, β目女^ 月月之贯 HA Α has one erasable power A device capable of writing the smallest unit of human data - such as a NAND type or a ship type flash memory. Flash: The body 101 can be configured to at least - map blocks, modify blocks, and fast for NAND Traces... Α & get & block, 4 ° mnemony and 5, map block, modify block \, quality soil can include multiple pages (Page), and kN〇r type flash 『s The mapping block, the modified block, and the cache block can be respectively H*k (seet〇i·). For the sake of brevity, this specification will use the same page for a detailed description. However, it is worth noting that it does not limit the scope of the present invention by VTU 09-0009/0608-A41979 TWf / 201040717, anyone skilled in the art. Changes and modifications may be made to the extent that the spirit of the present invention is applied to various flash memories without departing from the spirit and scope of the present invention. According to an embodiment of the present invention, each page of the mapping block is used to store the original data, and the mapping block may have at least one corresponding modified block, when the original data needs to be changed, in the modified block. Each page stores the updated content of the original data, and each modified block may correspond to one of the at least one cached block for storing the location information of the data written by the modified block. The right-hand negative block uses 2 bytes to record the position information. Ο Figure 2 is a schematic diagram showing the data structure of the flash memory according to an embodiment of the present invention. As shown, the flash memory 200 can be configured with a plurality of cache blocks 201, a plurality of map blocks 2〇2, and a plurality of modified blocks 203. Each page of the cache block 201 includes a data area and a redundant area, and the data area may include a plurality of data intercepts for storing the positions of the non-blank pages of the modified block according to the page order of the corresponding modified block. News. Taking 256 megabytes (MB) of flash memory as an example, 2 〇 48 blocks can be configured, each block size is 128 KB, and each block can contain 256 pages (or segments) 'each page The data area size is 512 bytes and has a corresponding 16 byte redundant area. Therefore, according to an embodiment of the present invention, the data area of each page can be divided into 256 data fields, which is sufficient to completely record all the position information of each of the modified blocks, and the cache block 201
’則快取區塊Ml ’而快取區塊201的冗 1之一快取區塊索引’ 201040717 中=射區塊2G2與修改區塊2G3之冗餘區域用以儲存該頁 ^貝料區域所寫人之資料所對應之㈣區塊編號與邏輯頁 編號（以下將作詳細介紹）。 ，據本發明之—實施例，當寫人快閃記憶體1〇1時， j器1G2接收包含—寫人邏輯位址與既定資料之一寫入 並根據該寫人邏輯位址取得對應之—邏輯區塊編號 ^及—邏輯頁編號腫。例如，假設寫人邏輯位址為 ，其中快閃記憶體101之一區塊包含8頁，並且一頁大 小為10 byte，則可得到邏輯區塊編號LBN為9〇除以卯 之商數，而邏輯頁編號LSN為9〇除以8〇之餘 大小所得到的數值，即在此範例中，lbn=1，lsn=L^ 此處理器102將接收到的既定資料存入第j個邏輯區塊之 第1頁。處理器1〇2進一步根據邏輯區塊編號L·取得對 應之一映射區塊，其中此映射區塊為快閃記憶體謝中實 際被配置之-物理區塊’用以儲存此邏輯區塊的原始資 料。當處理器1〇2判斷映射區塊中對應於此邏輯頁編號 LSN之一頁尚未被寫入時，處理器1〇2將既定資料寫入至u 該頁，並且當該頁已被寫入時，處理器1〇2進一步取得對 應於此映射區塊之一修改區塊，以及對應於此修改區塊之 !·夬取區塊，處理器1〇2將既定資料寫入至此修改區塊之 一空白頁，並且將既定資料之邏輯頁編號LSN寫入至此快 取區塊之一空白頁。 、 根據本發明之一實施例，處理器1〇2更進一步在隨機 存取記憶體裝置103内建立一邏輯至映射區塊對應表（第 一資訊表）、一物理區塊資訊表（第二資訊表）以及一快取區 VTU09-0009/0608-A41979TWf / 1〇 201040717 塊索引表（第三資訊表）。第3圖係顯示根據本發明之 施例所述之邏輯至映射區塊對應表3〇〇 貧 圖。根據本發明之-實施例，邏輯至映射 意 射區塊之-物理區塊編號’例如，對 Ο 〇 邏輯^塊，其映射區塊之物理區塊編號炎 Ox:。$ 4圖係顯示根據本發明之—實施例所述之物^ 區塊貝訊表彻之資料結構示意圖。根據本發明之一資^ ，’物理區塊資訊表_依照物理區塊編號之順序依二 =區塊:狀態資訊與其連結資訊。例如，物理： 編號為0之一物理區塊為-空閒區塊㈣，即，尚未被^ 用之區塊，其連結資訊則儲存下―個空靠 編號。物理區塊編號為2之一物理區塊為一映射$ =ΡΒ) ’其連結資訊㈣存對應之修改區塊 二 號__。物理區塊編號為3之-物理區塊為 =(聽），其連結資訊則儲存對應之快取頁之 : ::取=:::;rr對應於此修上 貝資訊。例如，對於同樣包含8百 =夬取區塊’快取區塊索引0x謝i可指示出快取頁位於系 置的第1個快取區塊⑴除以8之商數)的第3頁⑴除 =之餘數）。而物理區塊編號為6之一物理區塊為一快取 結f訊則儲存此快取區塊之快取區塊編 就第5a圖係顯不根據本發 r 表結構二 咖㈣糾-之祕㈣編號與第- 201040717 個工閒的决取頁（即’快取區塊的第一個空白頁）的頁編 號。如圖所示’假設㈣最大可配置4個快取區塊，並且 各快取區塊可包含8頁，職取區塊索引表500依序紀錄 這4個快取區塊的物理區塊編號與第—健白頁的編號。 根據本發明之-實施例’當—個快取區塊的各頁都被使用 過後才會配置下-個快取區塊。如第圖所示，編號〇 的决取區塊已被存滿資料，因此目前使用中的快取區塊為 編號1的快取區塊。 、第6圖係顯隸據本發明之-實關所述之快閃記憶 體管理方法流程圖。如圖所示，處理器1〇2首先接收包含 -寫入邏輯位址與一既定資料之一寫入指令，用以寫入該 既疋資料至-快閃記憶體裝置之—頁（步驟應）。接著， 當該頁已寫人資料時，處理器1G2取得對應於包含該頁之 -映射區塊之-修改區塊，以及配置對應於該修改區塊之 决取區塊(步驟S602)。最後，處理器1〇2寫入該既定資 料於該修改區塊之-空白頁，並且寫人包含該修改區塊之 該頁之位置資訊於該快取區塊之一空白頁（步驟⑽3)。 第7a 7b圖係顯示根據本發明之一實施例所述之快閃 記憶體之寫人操作之詳細流程圖。首先，處理器ι〇2根據 接收到的寫人心^取得寫人邏輯位址所對應之邏輯區塊編 號LBN與邏輯頁編號咖(步驟S7〇i)。接著，處理器1〇2 查詢邏輯錢㈣塊對縣以取得映龍塊的物理區塊編 號(步驟識）。接著’處理器而檢查此映射區塊中對應 於此邏輯頁紐LSN之一頁是否為空白頁(·步驟S703)。若 此頁為-空白頁’則處理器1〇2將既定資料寫入此頁（步驟 VTU09-0009/0608-A41979TWf / 201040717 S704)。若此頁已存有資料’則處理器ι〇2依據物理區塊資 訊表查詢映射區塊是否有對應的修改區塊（步驟S705)。若 此映射區塊沒有對應的修改區塊，則處理器102為此映射 區塊分配一修改區塊（步驟S706)。接著，處理器ι〇2將既 疋資料寫入此修改區塊的第一頁（步驟S707)，並且分配快 取區塊之一頁給此修改區塊（步驟S708)，用以紀錄此既定 賓料之位置資訊(例如，邏輯頁編號LSN)，並且最後更新'The cache block M1' and one of the redundant blocks of the cache block 201 is cached. 201040717 Medium = Redundant area of the block 2G2 and the modified block 2G3 is used to store the page area The block number and logical page number corresponding to the data of the person to be written (detailed below). According to the embodiment of the present invention, when writing the flash memory 1〇1, the j1G2 receives the write-to-write logical address and one of the established data and writes according to the write logical address. - Logical block number ^ and - Logical page number is swollen. For example, suppose the writer logical address is, where one block of the flash memory 101 contains 8 pages, and the page size is 10 bytes, then the logical block number LBN is 9 〇 divided by the quotient of 卯, The logical page number LSN is a value obtained by dividing 9 〇 by the size of 8 ,, that is, in this example, lbn=1, lsn=L^, the processor 102 stores the received data into the jth logic. Page 1 of the block. The processor 1〇2 further obtains a corresponding mapping block according to the logical block number L·, wherein the mapping block is actually configured for the flash memory, and the physical block is used to store the logical block. Source material. When the processor 1〇2 determines that one of the mapped blocks corresponding to the logical page number LSN has not been written, the processor 1〇2 writes the predetermined data to the page, and when the page has been written At the same time, the processor 1〇2 further obtains a modified block corresponding to one of the mapping blocks, and corresponding to the modified block of the modified block, the processor 1〇2 writes the predetermined data to the modified block. One of the blank pages, and the logical page number LSN of the given material is written to one of the blank pages of the cache block. According to an embodiment of the present invention, the processor 1〇2 further establishes a logic-to-map block correspondence table (first information table) and a physical block information table (second in the random access memory device 103). Information table) and a cache area VTU09-0009/0608-A41979TWf / 1〇201040717 block index table (third information table). Figure 3 is a diagram showing the logic-to-map block correspondence table 3 贫 poverty map according to the embodiment of the present invention. According to an embodiment of the present invention, the physical block number of the logical-to-mapped block is 'for example, the physical block number of the mapped block is Ox:. The $4 figure shows a schematic diagram of the structure of the material according to the embodiment of the present invention. According to one aspect of the present invention, the physical block information table _ is in accordance with the order of the physical block number = block: status information and its link information. For example, physical: a physical block numbered 0 is a free block (four), that is, a block that has not been used, and its link information stores a number of free numbers. The physical block number is 2, one physical block is a map $=ΡΒ) ’, and its link information (4) corresponds to the modified block number 2 __. The physical block number is 3 - the physical block is = (listen), and the link information is stored in the corresponding cache page: :: fetch =:::; rr corresponds to the repair information. For example, for the same page containing 8 hundred = capture block 'cache block index 0x thank i can indicate that the cache page is located in the first cache block (1) divided by 8 quotient) page 3 (1) The remainder except =). The physical block number is 6 and the physical block is a cached node. The cache block of the cache block is stored in the cached block. The 5a figure is not based on the structure of the second table. The secret (4) number and the number of pages - 201040717 work and leisure (ie the first blank page of the cache block). As shown in the figure, assuming that (four) a maximum of four cache blocks can be configured, and each cache block can contain eight pages, the job block index table 500 sequentially records the physical block numbers of the four cache blocks. The number with the first-white page. According to the embodiment of the present invention, when each page of a cache block is used, the next cache block is configured. As shown in the figure, the numbered block is filled with data, so the currently used cache block is the number 1 cache block. Figure 6 is a flow chart showing the method of managing the flash memory according to the present invention. As shown, the processor 1〇2 first receives a write-write logical address and a write command of a predetermined data for writing the data to the page of the flash memory device (steps should be ). Next, when the page has written the profile, the processor 1G2 takes the modified block corresponding to the mapped block containing the page, and configures the decision block corresponding to the modified block (step S602). Finally, the processor 1〇2 writes the predetermined data to the blank page of the modified block, and the writer includes the location information of the page of the modified block to a blank page of the cache block (step (10) 3) . 7a-7b is a detailed flow chart showing the write operation of the flash memory according to an embodiment of the present invention. First, the processor ι 〇 2 obtains the logical block number LBN and the logical page number corresponding to the write logical address according to the received write heart ^ (step S7 〇 i). Next, the processor 1〇2 queries the logical money (four) block to the county to obtain the physical block number of the Yinglong block (step identification). Next, the processor checks whether a page corresponding to the logical page line LSN in the mapping block is a blank page (step S703). If the page is a - blank page, the processor 1 〇 2 writes the predetermined data to this page (step VTU09-0009/0608-A41979TWf / 201040717 S704). If the page has stored data, the processor ι2 queries whether the mapped block has a corresponding modified block according to the physical block information table (step S705). If the mapping block does not have a corresponding modified block, the processor 102 allocates a modified block for this mapping block (step S706). Next, the processor ι〇2 writes the data to the first page of the modified block (step S707), and allocates one page of the cache block to the modified block (step S708), for recording the predetermined Location information of the guest (for example, logical page number LSN), and last updated
〇 物理區塊資訊表（參考第4圖）與快取區塊索引表（參考第 5a、5b圖）中映射區塊、修改區塊以及快取區塊的相關資訊 (步驟 S709)。 ° 另一方面，若此映射區塊已有對應的修改區塊，則處 理器102依據物理區塊資訊表中映射區塊的連結資訊取俨 修改區塊所對應的快取頁的快取區塊索引（步驟S7l〇)接 著，處理器1〇2再根據快取區塊索引查詢快取區塊索= 表，以取得此快取頁所對應的快取區塊的物㈣ = 驟S7H)。接著，處理器102將此快取頁的内容载入隨機^ 取記憶體裝置1〇3(步驟S712)。接著，處理器102操5 隨機存取記憶體裝置103中，自快取頁 ，、作於 曆（visit)快取頁所儲存的資料，找出 百 倒序遍 中，第-個未被使用的空白資料襴位的索引，以: 取頁所對應之修改區塊的第一個可使用之办白此块 (步驟則），並根據此位置資訊將岐資^人修 所對應的空白頁（步驟S7U)。接著，處理器收將此^ 資料的位置貧訊(例如，邏輯頁編號LSN)寫入至 疋 VTU09-0009/0608-A41979TWf/ 機存取記憶體ΐ置1G3之快取頁的下—個空白欄位，^ 201040717 將,被更新過的快取頁資料更新至快閃記憶體101内之快 取區塊的下一個空白頁（步驟S715)。最後，處理器102更 新物理區塊資訊表（參考第4圖）與快取區塊索引表（參考第 5a、51)圖）中映射區塊、修改區塊以及快取區塊的相關資訊 (步驟 S716)。 第a 圖係顯示根據本發明之一實施例所述之快閃 記憶體之寫入操作之示意圖。值得注意的是，圖式中的虛 線用以區隔分別位於快閃記憶體1〇1與隨機存取記憶體裝 置103之資料’其中虛線的右侧用以顯示快閃記憶體101 内的資料結構。如上述，假設處理器102接收到的寫入邏 輯位址為90’其中寫入快閃記憶體1〇1之一區塊包含8頁， 並且一頁大小為10 byte，則可得到邏輯區塊編號LBN為 90除以80之商數’而邏輯頁編號LSN為90除以80之餘 數再除以頁大小所得到的數值，即在此範例中，LBN=1， LSN-1，因此處理器1〇2必須將接收到的既定資料存入第丄 個邏輯區塊之第1頁。接著，如第8a圖所示，、處理器1〇2 根據邏輯區塊編號(LBN=1)查找邏輯至映射區塊對應表 801中索引1的資料欄位内容，得到對應之映射區塊之物 理區塊編號。其令，根據本發明之一實 位為空，代表此邏輯區塊尚未分配對應之映射=貝= =102 J分配映射區塊給此邏輯區塊。若該資料攔位不為 二，代表此邏輯區塊已分配有對應之映射區塊，例如，在 此實施射，對應之映射區塊之物㈣塊編號為 此.映射區塊實際配置為第3個物理區塊。處理 根據邏輯頁編號卿喝存取映射區塊 理=^ VTU09-0009/0608-A41979TWf/ v ^ lEE % 201040717 第1頁，並且判斷此頁是否已被使用。根據本發明之一相关 The information about the mapped block, the modified block, and the cached block in the physical block information table (refer to FIG. 4) and the cache block index table (refer to FIGS. 5a and 5b) (step S709). On the other hand, if the mapping block already has a corresponding modified block, the processor 102 takes the cached area corresponding to the cached page corresponding to the modified block according to the link information of the mapped block in the physical block information table. Block index (step S7l) Next, the processor 1〇2 queries the cache block according to the cache block index to obtain the cache block corresponding to the cache page (4) = step S7H) . Next, the processor 102 loads the contents of the cache page into the random access memory device 1〇3 (step S712). Next, the processor 102 operates the random access memory device 103, the self-cached page, and the data stored in the visit cache page to find out the first and the last unused. The index of the blank data field is as follows: The first one of the modified blocks corresponding to the page can be used to white the block (step), and according to the location information, the blank page corresponding to the location is Step S7U). Then, the processor receives the location information (for example, the logical page number LSN) of the data to be written to the next blank of the cache page of the VTU09-0009/0608-A41979TWf/machine access memory device 1G3. The field, ^ 201040717, updates the updated cache page data to the next blank page of the cache block in the flash memory 101 (step S715). Finally, the processor 102 updates the information about the mapped block, the modified block, and the cached block in the physical block information table (refer to FIG. 4) and the cache block index table (refer to FIG. 5a, 51) ( Step S716). Figure a is a diagram showing a write operation of a flash memory according to an embodiment of the present invention. It should be noted that the dotted line in the figure is used to separate the data located in the flash memory 1〇1 and the random access memory device 103 respectively, wherein the right side of the dotted line is used to display the data in the flash memory 101. structure. As described above, it is assumed that the write logical address received by the processor 102 is 90', wherein one block of the write flash memory 1〇1 contains 8 pages, and the page size is 10 bytes, then the logical block can be obtained. The number LBN is 90 divided by the quotient of 80' and the logical page number LSN is 90 divided by the remainder of 80 and divided by the page size, ie in this example, LBN=1, LSN-1, so the processor 1〇2 must store the received data in the first page of the third logical block. Next, as shown in FIG. 8a, the processor 1〇2 searches for the data field content of the index 1 in the mapping block correspondence table 801 according to the logical block number (LBN=1), and obtains the corresponding mapping block. Physical block number. Thus, in accordance with one aspect of the present invention, the real bit is empty, indicating that the logical block has not been assigned a corresponding mapping = Bay = = 102 J allocation mapping block to this logical block. If the data interception is not two, it means that the logical block has been assigned a corresponding mapping block. For example, in this implementation, the corresponding mapping block object (four) block number is for this. The mapping block is actually configured as the first 3 physical blocks. Processing According to the logical page number, please access the mapping block. == VTU09-0009/0608-A41979TWf/ v ^ lEE % 201040717 Page 1 and judge whether this page has been used. According to one of the inventions
施例，處理器102可根據此頁之冗餘區域中所儲存的L 與LSN判斷此頁是否已被使用，若無紀錄LBN與Lsn 則處理器102可直接將資料寫入該頁。另一方面，若此， 之冗餘區域已紀錄LBN與LSN，代表此頁之資料頁 使用，如圖所示之映射區塊8〇3之第！頁，其中被破 棚位代表該欄位已被使用。因此，處理器102接著根= Ο 〇 到的物理區塊編號查找物理區塊資訊表8〇2中索弓丨3、知 料欄位内容’其中物理區塊資訊表8()2如上述包=資 連結資訊兩攔位’狀態欄位用以紀錄此物理 與 區塊(FB)、快取區塊(CB)、映射區塊(琴）或修改= (M〇B)，而連結資訊如上述分卿以儲存此物理區= 結資訊。鋪本發明之-實_，若賴資訊為空 此映射區塊内所儲存的資料尚未被修改過，處理器⑽ 配置-修改區塊以及-快取區塊，湘此修改區塊之一= 白頁儲存在本次寫人操作要被儲麵既定#料，並 取區塊之-空白頁儲存此既定資料所 編號 。另一方面，當連結資訊不為空例如第'頁:= :’處理器搬由物理區塊資訊表802中得知映射區塊對 應之修改區塊之物職塊職為4。 尾對 物理=資3器8:2根據修改區塊之物理區塊編號查找 物虹塊資訊表8〇2内對應的欄位，得到修改區塊之連姓 育訊。如上述’修改區塊之連結資訊儲存對應之快取頁: ::取區塊索引。處理器1〇2接著根據快取區塊索引得到 塊之位置=#訊，如上述，在此實施例中，快取區塊 VTU09-0009/0608-A41979TWf / ^ «=· 1 ^ 201040717 ，處理講因此得知對應於此修改區塊之快取 頁位於糸統配置的第！個快取區塊⑴除以 3頁（11除以8之餘數）。請參考第8b圖， ^ -步根據快取區塊索引表8G9取得此快^器102可進 區塊的物理區塊編號’得知系統配置的第/對應的快取 取區塊編號為”所對應的物理區塊編號為2固:取區塊(快 接著可存取絲置的第1錄轉塊8。5的;『二102 注意的是，如上述，快取區塊Μ餘區域同樣會 紀錄對應之修改區塊之物理區塊編號，例如㈣ 與斷的冗餘區域(右側攔位）可儲存對應之修改區塊之物 理區塊編號’用以顯示出各頁之資料區域所儲 訊屬於哪個修改區塊。根據本發明之—實施例，當處理^ 102根據快取區塊索引找到對應之快取 ° 102將快取頁_之内容載人隨機存取㈣體裂置^ 15For example, the processor 102 can determine whether the page has been used according to the L and LSN stored in the redundant area of the page. If there is no record LBN and Lsn, the processor 102 can directly write the data to the page. On the other hand, if this, the redundant area has been recorded LBN and LSN, which represents the data page of this page, as shown in the mapping block 8〇3! The page, which was broken by the shed, represents that the field has been used. Therefore, the processor 102 then searches for the physical block information table 8〇2 in the physical block number of the root block=2, and the content of the knowledge field, where the physical block information table 8()2 is as described above. = The link information of the two blocks 'status field is used to record the physics and block (FB), cache block (CB), map block (qin) or modify = (M〇B), and the link information The above division is to store this physical area = knot information. The invention of the invention - the actual _, if the information is empty, the data stored in the mapping block has not been modified, the processor (10) configuration - modify the block and - cache block, one of the modified blocks = The white page is stored in this writing operation to be saved by the storage surface, and the block-blank page stores the number of the established data. On the other hand, when the link information is not empty, for example, the 'page:=:' processor moves from the physical block information table 802 to know that the block of the modified block corresponding to the map block is 4. Tail to the physical = 3 3 8: 2 according to the physical block number of the modified block to find the corresponding field in the object block 8 〇 2, get the modified block of the surname. For example, the cache page corresponding to the link information storage of the above-mentioned modified block: :: Take the block index. The processor 1〇2 then obtains the location of the block according to the cache block index=#, as described above, in this embodiment, the cache block VTU09-0009/0608-A41979TWf / ^ «=· 1 ^ 201040717 , processing Therefore, it is known that the cache page corresponding to this modified block is located in the system configuration! The cache block (1) is divided by 3 pages (11 divided by the remainder of 8). Please refer to FIG. 8b, ^ - step according to the cache block index table 8G9 to obtain the physical block number of the block that can be entered into the block 102 'learn the system configuration of the corresponding / corresponding cache block number is " The corresponding physical block number is 2 solid: take the block (faster then access the first record block of the wire set 8. 5; "2 102 note that, as mentioned above, cache the remaining area of the block Similarly, the physical block number of the corresponding modified block will be recorded. For example, (4) and the redundant area of the break (the right side block) can store the physical block number of the modified block to display the data area of each page. Which modified block the storage belongs to. According to the embodiment of the present invention, when the processing 102 finds the corresponding cache according to the cache block index, the content of the cache page is loaded by the random access (four) body split ^ 15
j實施例中，由於是要將資料寫^閃㈣H 此處理器102自快取頁806之資料尾端倒序 頁806之内容，如第8c圖所示，處理器丨 州⑴叭取 处垤器1〇2發現最後一筆 被儲存之邏輯頁編號LSN位於快取頁8〇6 ^ 〕弟5個搁位〇 因此，處理器102得知修改區塊内下—個可使 為第ό頁。 二貝 值得注意的是’在本發明之實施例中，由於快取頁_ 之内容=被載入隨機存取記憶體裝置1〇3,因此處理器ι〇2 可快速得知修改區塊内下一個可使用之空白頁 傳統技術巾必須在快閃記憶體巾倒序遍轉改區塊的内^ 以找出下-個空白頁等的技術相比’本發明所提出之快： VTU09-0009/0608-A41979TWf / 16 ' 201040717 s己憶體f理方法實際上僅需存 之快取頁），以及修改區塊之 塊之一頁（即，上述 快閃記憶體之寫入速度。 顯然地可大幅度地提升 明參考至第8d圖，由於處理器 807(物理區塊4)内下一個可使用之知修改區塊 處理器1〇2接著將既定資料寫入該；2 6頁，因此 區域寫人這筆既定㈣的邏輯頁 、'該頁的冗餘 编號LBN，圓本-、 ' ’ (以及邏輯區塊 Ο Ο 編號圖未不）。此外，請參考回第 器102已在遍層過程中得知快取頁_ ’由於處理 欄位為第6個攔朽l @ 〇 低1可被使用之 襴位為第6個攔位，如第8e圖中％出的箭頭 102接者將這筆既定資料的邏輯頁編號咖曰：： 入隨機，取記憶體裝置1〇3之快取頁_第6個寫==被载 值传注意的是，由於實際上快取區塊8〇 快閃記憶體内，因此處理器搬接著將隨機 :穿 置103内被更新之快取頁8〇6資 ^隐體裝 理斤换WTT , 貝竹馬入至決取區塊805(物 ⑽2)的下一個空白頁。根據本發明之一實施例，處理 器102根據快取區塊索引纟，得知快取區塊8〇5的下一 個空白頁為第4頁，因此處理器1G2如第^圖所示將被更 新之快取頁806資料寫入至快取區塊805(物理區塊2)的第 4頁，並且將快取區塊索引表8〇9中此快取區塊的第一空 白頁=貝訊更新為5。此外，修改區塊所對應之快取區塊索 引變成12 ’因此處理器ι〇2最後於物理區塊資訊表8〇2内 將修改區塊807所對應之快取區塊索引更新成12。 第9圖係顯示根據本發明之另一實施例所述之快閃記 憶體管理方法流程圖。首先，處理器1〇2接收包含一讀取 VTU09-0009/0608-A41979TWf / 201040717 邏輯位址之-神齡’並鱗冑取 ，之一快取區塊索⑽驟_)。接著，處=== f夫取區塊索引載入快取區塊之複數資料襴位所儲存= 置資訊至-隨機存取記憶體裝置（㈣s9G2)。 器102於隨機存取記憶體裝置内自快㈣塊之 = 端倒序尋找讀取邏輯位址所對應之—位置資訊，、以 取邏輯位址最近儲存之位置資訊(步驟s狗。最後，t 器搬根據取得之位置資訊存取讀取邏輯位 = =)塊内所儲存之對應於讀取邏輯位址之資料= 第10圖係顯示根據本發明之一實施例所述之快閃記 體之讀取操作之詳細絲圖。首先，處理器1G2根據讀取 指令之讀取邏輯位址取得邏輯區塊編號LBN與邏輯頁編號 LSN(步驟S1001)。接S ’處理器1〇2查詢邏輯至映射區^ 對應表以取得映射區塊的物理區塊編號（步驟S100幻。接 著，處理器102檢查此映射區塊中對應於此邏輯頁編號 LSN之一頁是否為空白頁（步驟sl〇〇3)。若是，處理器丄⑽ 返回空白資料（步驟S10〇4)。若否，處理器1〇2依據物理區 塊資訊表查詢映射區塊是否有對應的修改區塊（步驟 S1005)。若此映射區塊沒有對應的修改區塊，則處理器ι〇2 直接返回此頁所儲存之資料（步驟S1006)。若此映射區塊有 對應的修改區塊，則處理器1〇2依據物理區塊資訊表中映 射區塊的連結資訊取得修改區塊所對應的快取頁的快取區 塊索引（步驟S1007)。接著，處理器102再根據快取區塊索 引查詢快取區塊索引表’以取得此快取頁所對應的快取區 VTU09-0009/0608-A41979TWf / ι〇 201040717 塊的物理，塊編號(步驟sl〇〇8)e接著，處理器撤將此快 ，頁^内容載人隨機存取記憶體裝置1G3 s接 者，處理器102操作於隨機存取記憶難置103中，自Ϊ 取，之㈣尾^倒序遍層（visit)快取頁所儲存的資料，尋找 出取新-筆對應於此編號lsn之 此邏輯頁編號咖之攔位之索引（步驟si 2 ㈣此索㈣取修改區塊帽應於 = Ο ❹ LSN之最新—筆資料並返回（步驟sum)。 號 二1Η/圖係顯示根據本發明之—實施例所述之快 閃記憶體之讀取操作之示意圖。假設處理： 函=1，邏輯頁編物叫。接著，如第山圖所 理器102根據邏輯區塊編號(LBN=1)查找邏輯至映射： 對應表801中索引1的資料攔位内容，得到對應之 理區塊編號。其中’根據本發明之-實施例，、若； 資料爛位為空，代表此邏輯區塊尚未分配對應之映3 塊’處理器102無法找到有效之資料便可接^、°° 果咏若該資料攔位不為空，代表此邏輯區塊 有= 之映射區塊，例如，在茈眘^ 刀亂虿對應 理巴㈣心,r f應之映射區塊之物 4編號為3 ’代表此映射區塊實際配置為第3個物理 區塊。處理器102接著根據邏輯頁 個物理 塊謝(物理區塊3)之第i 麵映射區 用。根據本發明之一實施例，處理器二 ==儲存的LBN與LSN _此頁是 ： l::=!：rsN’代f未咐，處理器⑽ 201040717 可返回空資料。另-方面，若此頁之冗餘區域已記錄LBN 與LSN代表此頁之資料區域已被使用，如圖所示之映射 區塊803之第1頁’其中被填滿的攔位代表該攔位已被使 用因此處理器102接著根據得到的物理區塊編號查找 物理區塊資訊表802中索引3的資料欄位内容。根據本發 明之一實施例，若映射區塊之連結資訊為空，代表此映射 區塊内所儲存的資料尚未被修改過，即，映射區塊内所儲 存的資料為有效的，處理器102可直接讀取並返回映射區 塊内所儲存的資料。另一方面，當連結資訊不為空，代表 此映射區塊内所儲存的資料已被修改過，即，映射區塊内 所儲存的資料為無效的。因此，處理器1〇2進一步透過物 理區塊資訊表802中得知映射區塊所對應之修改區塊之物 理區塊編號為4。 接著，處理器102根據修改區塊之物理區塊編號查找 物理區塊資訊表802内對應的欄位，得到修改區塊之連結 資訊。如上述，修改區塊之連結資訊儲存對應之快取頁之 一快取區塊索引，例如在此實施例中，快取區塊索引為12。 接著，處理器102根據快取區塊索引得知對應於此修改區 塊之快取頁位於系統配置的第丨個快取區塊（12除以8之商 數）的第4頁（12除以8之餘數）。請參考第llb圖，處理器 102可進一步根據快取區塊索引表809取得此快取頁所對 應的快取區塊的物理區塊編號，得知系統配置的第1個快 取區塊（快取區塊編號為1)所對應的物理區塊編號為2。處 理器102接著可存取系統配置的第1個快取區塊的第 4頁，並且將此快取頁808之内容載入隨機存取記憶體裳 VTU09-0009/0608-A41979TWf / 20 201040717 置 103。 快取=器1〇2自快取頁808之資料尾端倒序遍曆 =容’以尋找出最後-筆存有碁_ 取抑體=，由於快取頁8〇8之内容已被載入隨機存 因此處理器102不需遍層配置於快閃 :快取頁，即可得知修改區塊内最新存有 Ο提出之換門Γ的位置。因此’與傳統技術相比’本發明所 憶體之讀取^體管理方法顯然地可大幅度地提升快閃記 你S 、又。再者，雖然本實施例中，處理器102是 始倒序遍層隨機存取記憶體裝置103中快取頁的 二=位元，㈣_也可以從頭端開始順序遍曆該快取 二：料攔位7G來獲得需要存取的頁在該修改區塊中的位 置育訊。 如第lie圖所不’處理器1()2發現最後_筆存有 〇 ^料位於快取頁_的第6個欄位。因此，處理器ι〇2 改區塊的第6頁儲存著對應於邏輯位址為9〇的最 换:斗最後’如第lld圖所示，處理器102存取修改區 5 〇7(物理區塊4)的第6頁之資料區域，並返回讀取的資 料0 根據本發明之-實施例，快取區塊的數量可根據計算 '罢統的需求而決&。例如’對於一快閃記憶體裝置，可 Λ，、 亚依序分配快取區塊編號（例如， :’並且處理器102於快取區塊初始化時，可藉由遍曆 區塊之冗舰域所儲存之位置資喊立出快取區塊。 VTU〇9-〇〇〇9/〇6〇g.A41979TWf / 21 201040717 處理器102接& 1 =第域r存:資：含與：^ =二 =4至映射 f根據本發明之-實施例，：了：區 關:導:快取區壤所储存的資料產生=正常 容是否正確，例如 各，取£塊所儲存的内 置貝訊(即，邏輯頁編號)以及各快取頁之冗餘：存的位 的修改區塊之物理區塊編號，比對該快取頁之各介所儲存 是否與此修改區塊之各頁的冗餘區域所儲存資訊 相符。若符合則保留此快取區塊，若不符合編號 處理器_取出下一個預留二資料時’ 圖與第5b圖所示），並且、/λ °使用（如第5a _所不）並且當所有已被使用的快取區摊、去， 系統規定的最大可用快取區塊數量時，例如，若 達到 示之快取區塊索引表501中4個快取區塊的第一個^所 皆紀錄為系統最大頁數8時，處理器1〇2直接抹除== 取區塊，以釋放出有效的空間。 斤有快 本領域一般技術人員可以瞭解，雖然於之前描 將讀取操作與寫入操作分開說明的，但是本發跑是 入操作的實質特徵是相同的。當邏輯位元址所對應之^寫 區塊之資料不能直接進行存取時’即在進行寫人操作時$ 射區塊的該頁已存儲有資料或是在進行讀取操作時、 塊的該頁資料並不是最新的，處理器需要通過映:區 VTU09-0009/0608-A41979TWf / 22 ° 鬼的 201040717 資訊來獲取與映射區塊相對應之修改區塊 的位置資訊或是與該邏輯位址相對應的:個空白頁 訊’進而核夠高效而準確地完成既定 的位置資 操作。 、的冩入或讀取 此外’當系統對快閃記憶體執行合 處理器搬可根據各修改區塊之冗餘區 ^^作時， 塊編號LBN與邏輯頁編號LSN判斷修 子之邏輯區In the embodiment, since the data is to be flashed (four) H, the processor 102 reads the content of the page 806 from the data end of the cache page 806, as shown in FIG. 8c, the processor 丨州(1) 1〇2 finds that the last stored logical page number LSN is located on the cache page 8〇6 ^ 〕 brother 5 places, so the processor 102 knows that the next block in the modified block can be the third page. It is worth noting that in the embodiment of the present invention, since the content of the cache page _ is loaded into the random access memory device 1〇3, the processor ι〇2 can quickly know the modified block. The next available blank page of the traditional technical towel must be in the reverse of the flash memory towel to change the block to find the next - blank page, etc. compared to the technology proposed by the present invention: VTU09-0009 /0608-A41979TWf / 16 ' 201040717 s _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The bright reference can be greatly improved to the 8th figure, since the next available processor in the processor 807 (physical block 4) modifies the block processor 1〇2 and then writes the predetermined data into the page; The area writes the logical page of the established (four), 'the redundancy number LBN of the page, the circle-, ' ' (and the logical block Ο 编号 number map is not). In addition, please refer back to the device 102 has been In the process of traversing the layer, I know that the cache page _ 'because the processing field is the sixth block l @ 〇 low 1 can be used The niche is the 6th block. For example, the arrow 102 in the 8e figure shows the logical page number of the given data:: Random, take the memory device 1〇3 cache page_第The 6 writes == are recorded by the load value. Because the cache block is actually flashed in the flash memory, the processor will move randomly: the cached page 8 is updated. The hidden body replaces the WTT, and the next step is to enter the next blank page of the block 805 (object (10) 2). According to an embodiment of the present invention, the processor 102 learns fast according to the cache block index. The next blank page of the block 8〇5 is the fourth page, so the processor 1G2 writes the updated cache page 806 data to the cache block 805 (physical block 2) as shown in FIG. Page 4, and the first blank page of the cache block in the cache block index table 8〇9 is updated to 5. In addition, the cache block index corresponding to the modified block becomes 12 ' The processor 〇2 finally updates the cache block index corresponding to the modified block 807 to 12 in the physical block information table 8〇2. FIG. 9 shows another according to the present invention. A flowchart of a flash memory management method according to an embodiment. First, the processor 1〇2 receives one of the logical addresses of the VTU09-0009/0608-A41979TWf/201040717 and the scale is taken. Cache block (10) __. Then, the === f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f The device 102 searches for the location information corresponding to the read logical address in the random access memory device in the reverse order of the (four) block, to obtain the location information recently stored by the logical address (step s dog. Finally, t The device moves to read the logical bit according to the obtained location information ==) the data stored in the block corresponding to the read logical address = FIG. 10 shows the flash memory according to an embodiment of the present invention. A detailed silk map of the read operation. First, the processor 1G2 obtains the logical block number LBN and the logical page number LSN based on the read logical address of the read command (step S1001). The S 'processor 1 查询 2 queries the logic to the mapping area ^ correspondence table to obtain the physical block number of the mapping block (step S100 phantom. Then, the processor 102 checks the mapping block corresponding to the logical page number LSN. Whether a page is a blank page (step sl1). If so, the processor 丄(10) returns blank data (step S10〇4). If not, the processor 1〇2 queries whether the mapping block has a block according to the physical block information table. Corresponding modified block (step S1005). If the mapping block does not have a corresponding modified block, the processor ι〇2 directly returns the data stored on the page (step S1006). If the mapping block has corresponding modification In the block, the processor 1〇2 obtains the cache block index of the cache page corresponding to the modified block according to the link information of the mapping block in the physical block information table (step S1007). Then, the processor 102 further The cache block index query cache block index table 'to obtain the cache area corresponding to the cache area VTU09-0009/0608-A41979TWf / ι〇201040717 block physical, block number (step sl8) e Then, the processor withdraws this fast, page ^ content The human random access memory device 1G3 s is connected to the processor 102, and the processor 102 operates in the random access memory 103, and the (4) tails are used to cache the data stored in the page to find out Take the new-pen corresponding to the index of the logical page number of this number lsn (step si 2 (four) this cable (four) take the modified block cap should be = Ο ❹ LSN's latest - pen data and return (step sum) Figure 2 shows a schematic diagram of the read operation of the flash memory according to the embodiment of the present invention. Assume that the processing: the function = 1, the logical page is called. Then, as the second figure processor 102: Find a logical-to-map according to the logical block number (LBN=1): Correspond to the data block content of the index 1 in the table 801, and obtain the corresponding block number. Wherein the data according to the present invention, if; The rotten bit is empty, indicating that the logical block has not been assigned the corresponding map 3 'The processor 102 can't find the valid data can be connected ^, ° ° If the data block is not empty, it means the logical block has = the mapping block, for example, in the cautious ^ knife 虿 虿 虿 理 ( 四 四The object 4 of the mapping block of rf should be numbered 3' to represent that the mapping block is actually configured as the third physical block. The processor 102 then according to the logical page, the physical block (the physical block 3), the i-th surface For the mapping area, according to an embodiment of the present invention, the processor 2 == stored LBN and LSN _ this page is: l::=!: rsN' generation f is not 咐, the processor (10) 201040717 can return null data. - Aspect, if the redundant area of this page has been recorded, LBN and LSN represent the data area of this page has been used, as shown in the first page of mapping block 803 as shown in the figure, where the filled block represents the block. It has been used so that the processor 102 then looks up the data field contents of index 3 in the physical block information table 802 based on the obtained physical block number. According to an embodiment of the present invention, if the link information of the mapping block is empty, the data stored in the mapping block has not been modified, that is, the data stored in the mapping block is valid, and the processor 102 is The data stored in the mapping block can be directly read and returned. On the other hand, when the link information is not empty, the data stored in the map block has been modified, that is, the data stored in the map block is invalid. Therefore, the processor 1〇2 further learns through the physical block information table 802 that the physical block number of the modified block corresponding to the mapping block is 4. Then, the processor 102 searches for a corresponding field in the physical block information table 802 according to the physical block number of the modified block, and obtains the link information of the modified block. As described above, the link information of the modified block stores a cache block index of the cache page corresponding to the cache information. For example, in this embodiment, the cache block index is 12. Next, the processor 102 learns, according to the cache block index, that the cache page corresponding to the modified block is located on the fourth page of the system configuration (the quotient of 12 divided by 8) (12 Take the remainder of 8). Referring to FIG. 11b, the processor 102 may further obtain the physical block number of the cache block corresponding to the cache page according to the cache block index table 809, and learn the first cache block configured by the system ( The physical block number corresponding to the cache block number is 1) is 2. The processor 102 can then access page 4 of the first cache block of the system configuration, and load the contents of the cache page 808 into the random access memory VTU09-0009/0608-A41979TWf / 20 201040717 103. Cache = device 1 〇 2 from the cache page 808 data end traversal traversal = capacity 'to find the last - pen storage 碁 _ 取 body =, because the cache page 8 〇 8 content has been loaded Therefore, the processor 102 does not need to be configured in the flash layer: the cache page can be used to know the location of the newly changed threshold in the modified block. Therefore, the method of reading the body of the present invention can obviously greatly improve the flash memory. Moreover, in the embodiment, the processor 102 is the second=bit of the cache page in the reverse random access random access memory device 103, and the (4)_ may also sequentially traverse the cache from the head end. Block 7G to get the location of the page that needs to be accessed in the modified block. As shown in the lie diagram, processor 1() 2 finds that the last _ pen has the sixth field in the cache page _. Therefore, the sixth page of the processor ι〇2 block stores the most corresponding to the logical address of 9〇: the last [as shown in the 11th, the processor 102 accesses the modified area 5 〇 7 (physical The data area of page 6 of block 4), and returning the read data 0. According to the embodiment of the invention, the number of cache blocks can be determined according to the calculation of the requirements of the "transition". For example, for a flash memory device, the cache block number can be assigned sequentially (for example, : ' and the processor 102 can traverse the block when the cache block is initialized. The location of the domain is stored in the cache block. VTU〇9-〇〇〇9/〇6〇g.A41979TWf / 21 201040717 Processor 102 is connected & 1 = domain r deposit: capital: containing and: ^ = two = 4 to map f according to the present invention - embodiment::: area: guide: data stored in the cache area = normal capacity is correct, for example, each block, the built-in shell stored in the block The information (ie, the logical page number) and the redundancy of each cache page: the physical block number of the modified block of the stored bit, compared with the pages of the cached page and whether the page of the modified block is stored The information stored in the redundant area matches. If it is met, the cache block is reserved. If it does not match the number processor _ take the next reserved data, the figure is shown in Figure 5b, and /λ ° is used. (as in 5a _ not) and when all the cache areas that have been used are spread, go, the system specifies the maximum number of available cache blocks For example, if the first page of the four cache blocks in the cache block index table 501 is recorded as the maximum number of pages 8 of the system, the processor 1〇2 directly erases the == block. To free up effective space. It is known to those skilled in the art that although the reading operation and the writing operation have been separately described before, the essential features of the present operation are the same. When the data of the write block corresponding to the logical bit address cannot be directly accessed, that is, when the write operation is performed, the page of the block block has stored data or is in the process of reading, the block The information on this page is not up-to-date. The processor needs to obtain the location information of the modified block corresponding to the mapped block or the logical bit through the mapping: VTU09-0009/0608-A41979TWf / 22 ° Ghost 201040717 Corresponding to the address: a blank page message 'in turn to complete the efficient location and operation accurately and accurately. Intrusion or reading In addition, when the system performs the processor swapping on the flash memory according to the redundant area of each modified block, the block number LBN and the logical page number LSN determine the logical area of the repair.
是否依照映射區塊之資料順序被寫人資料二域 各頁的更新資料依序被寫人修改區塊時，“ 接抹除映射區塊，並且改為配置修改區塊作為映射區塊直 另H當㈣區塊之各頁的更新資料依序未被寫入修 改區塊時，處理器102可取得-空閒區塊，將修改區塊與 映射區塊之有效資料合併至空閒區塊，抹除映射區塊與修 改區塊，並且配置此空閒區塊作為新的映射區塊。 本發明雖以較佳實施例揭露如上，然其並非用以限定 本發明的範圍，任何熟習此項技藝者，在不脫離本發明之 精神和範圍内，當可做些許的更動與潤飾，因此本發明之 保護範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 . 第1圖係顯示根據本發明之〜實施例所述之計算機系 統。 第2圖係顯示根據本發明之〜實施例所述之快閃記憶 體之資料結構示意圖。 第3圖係顯示根據本發明之〜實施例所述之邏輯至映 • · 射區塊對應表之資料結構示意圖。 VTU09-0009/0608-A41979TWf / 23 201040717 第4圖係顯示根據本發明之一實施例所述之物理區塊 資訊表之資料結構。 第5a-5b圖係顯示根據本發明之一實施例所述之快取 區塊索引表之資料結構示意圖。 第6圖係顯示根據本發明之一實施例所述之快閃記憶 體管理方法流程圖。 第7a-7b圖係顯示根據本發明之一實施例所述之快閃 記憶體之寫入操作之詳細流程圖。 第8a-8e圖係顯示根據本發明之一實施例所述之快閃 記憶體之寫入操作之示意圖。 第9圖係顯示根據本發明之另一實施例所述之快閃記 憶體管理方法流程圖。 第10圖係顯示根據本發明之一實施例所述之快閃記憶 體之讀取操作之詳細流程圖。 第lla-lld圖係顯示根據本發明之一實施例所述之快 閃記憶體之讀取操作之示意圖。 【主要元件符號說明】 100〜計算機系統； 101〜快閃記憶體； 102〜處理器； 103〜隨機存取記憶體裝置； 200〜快閃記憶體； 201〜快取區塊； 202〜映射區塊； 203〜修改區塊； VTU09-0009/0608-A41979TWf / 24 201040717 300、801〜邏輯至映射區塊對應表； 400、802〜物理區塊資訊表； 500、501、809〜快取區塊索引表； 803〜映射區塊； 804、805〜快取區塊； 806、808〜快取頁； 807〜修改區塊； LBN〜邏輯區塊編號； LSN〜邏輯頁編號。Whether the update data of each page of the data field is written in the order of the data of the mapping block in the order of the person who edits the block, "except the mapping block, and the configuration modification block is used as the mapping block. When the update data of each page of the (four) block is not sequentially written into the modified block, the processor 102 may obtain the free block, and merge the valid data of the modified block and the mapped block into the free block, In addition to mapping blocks and modifying blocks, and configuring the free blocks as new mapping blocks. The present invention has been disclosed in the preferred embodiments as above, but is not intended to limit the scope of the present invention, and anyone skilled in the art The scope of protection of the present invention is defined by the scope of the appended claims, without departing from the spirit and scope of the invention. The figure shows a computer system according to the embodiment of the present invention. Fig. 2 is a view showing the structure of the flash memory according to the embodiment of the present invention. Fig. 3 is a view showing the structure of the flash memory according to the present invention. Schematic diagram of the data structure of the logical block mapping table of the embodiment. VTU09-0009/0608-A41979TWf / 23 201040717 FIG. 4 shows a physical block information table according to an embodiment of the present invention. 5A-5b is a data structure diagram of a cache block index table according to an embodiment of the present invention. FIG. 6 is a view showing a flash memory according to an embodiment of the present invention. A flowchart of a method for managing a volume. Figures 7a-7b are detailed flowcharts showing a write operation of a flash memory according to an embodiment of the present invention. Figures 8a-8e show an embodiment of the present invention. FIG. 9 is a flow chart showing a method for managing a flash memory according to another embodiment of the present invention. FIG. 10 is a diagram showing implementation of a flash memory according to another embodiment of the present invention. Detailed flowchart of the reading operation of the flash memory as described in the example. The 11a-lld diagram shows a schematic diagram of the reading operation of the flash memory according to an embodiment of the present invention. 】 100~ meter Machine system; 101~ flash memory; 102~ processor; 103~ random access memory device; 200~ flash memory; 201~ cache block; 202~ map block; 203~ modified block; VTU09-0009/0608-A41979TWf / 24 201040717 300, 801 ~ logical to mapping block correspondence table; 400, 802 ~ physical block information table; 500, 501, 809 ~ cache block index table; 803 ~ mapping block 804, 805~ cache block; 806, 808~ cache page; 807~ modify block; LBN~ logical block number; LSN~ logical page number.
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