201039629 六、發明說明： 【發明所屬之技術領域】 本發明係有關影像感測器，特別是關於一種具增強動 態範圍之影像感測器的讀出系統及方法。 【先前技術】 半導體影像感測器（例如電荷耦合元件（CCD)或互 補金屬氧化半導體（CMOS)感測器）普遍使用於照相機 或攝影機中，用以將可見光之影像轉換為電子信號，便於 後續之健存、傳輸或顯示。 對於影像感測器的讀出（readout)系統，其動態範 圍（dynamic range )通常會受到類比至數位轉換器（ADC ) 之線性比例（linear scale )的限制。傳統解決方法之一係 藉由增加ADC之解析度來增強其動態範圍。然而，此方法 會增加成本及等待時間（latency)。另一種傳統解決方法 係結合長曝光影像（以得到較暗信號）及短曝光影像（以 得到較亮信號）來增強其動態範圍。然而，此方法複雜且 耗時。 201039629 鑑於傳統影像感測器的讀出系統無法有效且經濟地增 強其動態範圍，因此亟需提出一種快速且不複雜的影像感 測器讀出系統。 【發明内容】 鑑於上述，本發明的目的之一在於提出一種具增強動 ! •態範圍之影像感測器讀出電路，其具有簡單架構且操作快 〇速。 根據本發明實施例，像素電路包含至少具第一增益之 第一放大器（例如像素放大器）及具第二增益之第二放大 器（例如源極隨耦器），用以放大影像感測器的信號。讀出 電路包含至少第一讀出次電路（例如第一 CDS電路）及第 二讀出次電路（例如第二CDS電路），用以分別讀出第一 放大器的輸出及第二放大器的輸出。於一實施例中，使用 一加法器將第一讀出次電路的輸出及第二讀出次電路的輸 出予以相加。 【實施方式】 5 201039629 第一圖顯示本發明實施例之具增強動態範圍的影像感 測器讀出系統。影像感測器可以是（但不限定為）電荷耦 合元件（CCD)或互補金屬氧化半導體（CMOS)感測器’ 用以將可見光之影像轉換為電子信號。本實施例之讀出系 統可應用於數位影像處理裝置中，例如（但不限定為）照 相機或攝影機。 在本實施例之像素電路ίο中，光二級體1〇〇的信號 於像素電路10中被至少二放大器所放大，亦即：具第一 增益gl之第一放大器102A及具第二增益g2之第二放大 器102B。其中，第一增益gi異於第二增益g2。例如’ 本實施例中的第一增益gl係大於第二增益g2。第一放大 器102A的輸出S1及第二放大器i〇2B的輸出S2藉由一 讀出電路12而被讀出。該讀出電路12包含至少二讀出次 電路’亦即：第一讀出次電路120A及第二讀出次電路 120B，其分別接收輸出si及S2。第一讀出次電路120A 的輸出A及第二讀出次電路120B的輸出B可以經由一加 法器14而相加，其分別具有權重W1及W2，因而得到相 加結果為wiA+W2B。根據第一圖所示的實施例，由於光二 級體100之信號係由不同路徑以不同增益而被讀出，因此 其操作會類似於傳統結合長曝光影像及短曝光影像的效 201039629 果，但是架構遠較傳統技術來得簡單。藉此，讀出系统的 動態範圍可以有效地增進且較為經濟。 、 第二圖顯示本發明實施例讀出系統（第一圖）的細部 電路圖。在本實施例中，像素電路1〇主要包含一重置電 晶體RST、一源極隨耦器SF及一傳輸電晶體τχ。為簡化 起見，圖式中的電晶體及其控制信號則使用相同的符號。 0於圖式中，當重置電晶體RST被開啟時，可用以將光二級 體D重置到一個重置參考電壓。當源極隨耦器SF被開啟 時，可用以缓衝光二級體D的影像信號。當傳輸電晶體τχ 被開啟時，可用以傳送光二級體D的像素影像信號。 像素電路10還包含一 RSTD電晶體，其連接於一參 考電壓VCM〇與迴授電容Cf 一極板之間。迴授電容Cf的另 Q 一極板則連接至源極隨耦器SF的閘極。NRSTD電晶體連 接於第一輸出S1與迴授電容Cf/RSTD電晶體接點之間。 在本實施例中，對電晶體Bias_nl、Bias_n2、 Bias_pl、Bias_p2施以適當的偏壓或者調整其適當的元 件尺寸’用以提供二電壓輸出，亦即：第一輸出S1及第 二輸出S2。其中，第一輸出S1係由像素電路10之像素 放大器所提供，而第二輪出S2則是由像素電路10之源極 7 201039629 隨耦器SF所提供。在本實施例中，像素放大器具有增益 gl，其大於源極隨耦器SF之增益g2。 繼續參閱第二圖，第一關聯雙重取樣（correlated double sampling，CDS)電路 120A 接收第一輸出 S1， 而第二CDS電路120B則接收第二輸出S2。第一 CDS 電路 120A 包含第一取樣-保持-重置信號 (sample-and_hold-reset_signal，SHR)電晶體 SHR一1 及第一取樣-保持-影像信號 (sample-and-hold-image一signal, SHS )電晶禮 SHS-1。第一 SHR電晶體SHR_1及第一 SHS電晶體 SHS_1分別連接至第一 SHR電容Cshrj及第一 SHS電 容CSHs_i。其中，於重置期間，第一 SHR電晶體SHR_1 被開啟以進行取樣並保持重置信號於第一 SHR電容 Cshr_i ;於積分期間’第一 SHS電晶體SHS_1被開啟以 進行取樣並保持影像信號於第一 SHS電容Cshs 1。類似的 情形’第二CDS電路120B包含第二SHR電晶體SHR_2 及第二SHS電晶體SHS一2。第二SHR電晶體SHR_2及 第二SHS電晶體SHS—2分別連接至第二SHR電容Cshr_2 及第二SHS電容Cshs_2。其中，於重置期間，第二shR 電晶體SHR_2被開啟以進行取樣並保持重置信號於第二 SHR電容CSHR_2 ;於積分期間，第二SHS電晶體SHS_2 201039629 被開啟以進行取樣I仅 #保持影像信號於第二SHS電容 CSHS_2。 在本實施例中，筮 u 卑〜SHR電容Cshrj的輸出Qrl於 節點14A處電性耦接扒曾 曰给 第二SHS電容Cshsj的輸出Qs2, 且第一 SHS電容CSHq上 v 接於第二讓電容Cs輸出Qsl於節點14B處獅 〇 ❹ 節點⑽的輸出U:二出= (亦即，(^QS2)。力、: 成去節點14A的輸出 示如下： 如法器14的輸出可以表示 (Qsi + Qr2)- (Qrl + Qs2)^(〇 n \4-(r\ i-fQrl-QslJl + I + iQ^-Q^81"^11 {Qr2'^ 上述表示式的第〜項相於一 第二項則相關於第二咖電路⑽電路12〇A’而 係因為像素電路10之像〜項的負號） 為反相，而第二項的正：二g第一輪出S1與其輸入 的第二輸出32與其‘為(同+相。，疋因為源極_器即 第三圊顯示第二 本發明實施例之操作:::::的時序圖。第_顯示 9 201039629 於操作時’重置電晶體RST首先於步驟41中被開啟 (3〇) °在此同時，控制信號RSTD (其係延長重置控制 ^號RST )也同時變為主動（active )。接下來’於步驟 42中’以主動第二SHR信號SHR—2 (31)及第二SHr 電晶體來取樣第二輸出節點S2的第二重置信號，並接著 使其保持於第二SHR電容CSHR_2中。同樣的，以主動第 一 SHR信號SHR一 1 (32)及第一 SHR電晶體來取樣第 一輸出節點S1的第一重置信號，並接著使其保持於 SHR電容Cshr」中。 接著，於步驟43中，開啟傳輸電晶體TX (33)。接 下來’於步驟44中，以主動第二SHS信號SHS—2 (34) 及第二SHS電晶體來取樣第二輸出節點S2的第二影像信 號，並接著使其保持於第二SHS電容Cshs_2中。同樣的， 以主動第一 SHS信號SHS_i (35)及第一 SHS電晶體 來取樣第一輸出節點S1的第一影像信號，並接著使其保 持於第一 SHS電容CSHS1中。 第一 SHR電容cSHR1的輸出Qrl和第二SHS電容 Cshs_2的輸出Qs2於節點14A處各依其權重（weightings) 作電性耦接。上述之權重可藉由調整可調（adjustable) SHR或SHS電容而得到。類似的情形，第一 SHS電容 201039629201039629 VI. Description of the Invention: [Technical Field] The present invention relates to image sensors, and more particularly to a readout system and method for an image sensor having an enhanced dynamic range. [Prior Art] Semiconductor image sensors (such as charge coupled devices (CCD) or complementary metal oxide semiconductor (CMOS) sensors) are commonly used in cameras or cameras to convert visible light images into electronic signals for subsequent Health, transfer or display. For image sensor readout systems, the dynamic range is typically limited by the analog to digital scale of the digital converter (ADC). One of the traditional solutions is to increase the dynamic range of the ADC by increasing the resolution of the ADC. However, this approach increases cost and latency. Another traditional solution is to combine long-exposure images (to get darker signals) and short-exposure images (to get brighter signals) to enhance their dynamic range. However, this method is complicated and time consuming. 201039629 In view of the fact that the conventional image sensor readout system cannot effectively and economically increase its dynamic range, it is urgent to propose a fast and uncomplicated image sensor readout system. SUMMARY OF THE INVENTION In view of the above, it is an object of the present invention to provide an image sensor readout circuit having an enhanced dynamic range with a simple architecture and fast operation. According to an embodiment of the invention, the pixel circuit includes a first amplifier (eg, a pixel amplifier) having at least a first gain and a second amplifier (eg, a source follower) having a second gain for amplifying a signal of the image sensor . The readout circuitry includes at least a first readout secondary circuit (e.g., a first CDS circuit) and a second readout secondary circuit (e.g., a second CDS circuit) for respectively reading the output of the first amplifier and the output of the second amplifier. In one embodiment, an adder is used to add the output of the first readout secondary circuit and the output of the second readout secondary circuit. [Embodiment] 5 201039629 The first figure shows an image sensor readout system with enhanced dynamic range according to an embodiment of the present invention. The image sensor can be, but is not limited to, a charge coupled device (CCD) or a complementary metal oxide semiconductor (CMOS) sensor' used to convert an image of visible light into an electrical signal. The readout system of the present embodiment can be applied to a digital image processing device such as, but not limited to, a camera or a video camera. In the pixel circuit of the embodiment, the signal of the photodiode 1 is amplified by the at least two amplifiers in the pixel circuit 10, that is, the first amplifier 102A having the first gain gl and the second gain g2. Second amplifier 102B. The first gain gi is different from the second gain g2. For example, the first gain gl in this embodiment is larger than the second gain g2. The output S1 of the first amplifier 102A and the output S2 of the second amplifier i〇2B are read by a readout circuit 12. The readout circuit 12 includes at least two readout subcircuits, i.e., a first readout secondary circuit 120A and a second readout secondary circuit 120B, which receive outputs si and S2, respectively. The output A of the first readout sub-circuit 120A and the output B of the second readout sub-circuit 120B can be added via an adder 14, which has weights W1 and W2, respectively, and thus the result of the addition is wiA+W2B. According to the embodiment shown in the first figure, since the signal of the photodiode 100 is read out with different gains by different paths, the operation is similar to the effect of the conventional combination of the long exposure image and the short exposure image 201039629, but The architecture is much simpler than traditional technology. Thereby, the dynamic range of the readout system can be effectively enhanced and economical. The second figure shows a detailed circuit diagram of the readout system (first figure) of the embodiment of the present invention. In this embodiment, the pixel circuit 1A mainly includes a reset transistor RST, a source follower SF, and a transfer transistor τ. For the sake of simplicity, the transistors in the figure and their control signals use the same symbols. In the figure, when the reset transistor RST is turned on, it can be used to reset the photodiode D to a reset reference voltage. When the source follower SF is turned on, it can be used to buffer the image signal of the photodiode D. When the transmission transistor τ χ is turned on, it can be used to transmit the pixel image signal of the photodiode D. The pixel circuit 10 further includes an RSTD transistor connected between a reference voltage VCM〇 and a feedback capacitor Cf. The other Q plate of the feedback capacitor Cf is connected to the gate of the source follower SF. The NRSTD transistor is connected between the first output S1 and the feedback capacitor Cf/RSTD transistor contact. In the present embodiment, the transistors Bias_nl, Bias_n2, Bias_pl, Bias_p2 are appropriately biased or their appropriate component sizes are adjusted to provide a two-voltage output, i.e., a first output S1 and a second output S2. The first output S1 is provided by the pixel amplifier of the pixel circuit 10, and the second round S2 is provided by the source 7 201039629 of the pixel circuit 10 with the follower SF. In the present embodiment, the pixel amplifier has a gain gl which is greater than the gain g2 of the source follower SF. Continuing with the second diagram, a first correlated double sampling (CDS) circuit 120A receives a first output S1 and a second CDS circuit 120B receives a second output S2. The first CDS circuit 120A includes a first sample-and-hold-reset signal (SHR) transistor SHR-1 and a first sample-and-hold-image signal (sample-and-hold-image-signal, SHS) ) Electro-Crystals SHS-1. The first SHR transistor SHR_1 and the first SHS transistor SHS_1 are connected to the first SHR capacitor Cshrj and the first SHS capacitor CSHs_i, respectively. Wherein, during the reset period, the first SHR transistor SHR_1 is turned on to sample and maintain the reset signal in the first SHR capacitor Cshr_i; during the integration period, the first SHS transistor SHS_1 is turned on to sample and maintain the image signal. The first SHS capacitor Cshs 1. A similar situation 'the second CDS circuit 120B includes the second SHR transistor SHR_2 and the second SHS transistor SHS-2. The second SHR transistor SHR_2 and the second SHS transistor SHS-2 are connected to the second SHR capacitor Cshr_2 and the second SHS capacitor Cshs_2, respectively. Wherein, during reset, the second shR transistor SHR_2 is turned on to sample and maintain the reset signal in the second SHR capacitor CSHR_2; during integration, the second SHS transistor SHS_2 201039629 is turned on for sampling I only #保持The image signal is at the second SHS capacitor CSHS_2. In this embodiment, the output Qrl of the 筮u 〜~ SHR capacitor Cshrj is electrically coupled to the output Qs2 of the second SHS capacitor Cshsj at the node 14A, and the first SHS capacitor CSHq is connected to the second Capacitor Cs outputs Qsl at node 14B at the output of the Griffin node (10) U: two out = (ie, (^QS2). Force,: The output of the node 14A is shown as follows: If the output of the controller 14 can be expressed ( Qsi + Qr2)- (Qrl + Qs2)^(〇n \4-(r\ i-fQrl-QslJl + I + iQ^-Q^81"^11 {Qr2'^ The first term of the above expression is A second term is related to the second coffee circuit (10) circuit 12A' because the negative of the image-to-item of the pixel circuit 10 is inverted, and the positive of the second term: two g is the first round of S1 and The input second output 32 is the same as the 'same + phase. 疋 because the source _, ie, the third 圊 shows the timing diagram of the operation of the second embodiment of the invention:::::. _ display 9 201039629 When the 'reset transistor RST is first turned on in step 41 (3〇) ° at the same time, the control signal RSTD (which extends the reset control ^ RST) also becomes active (active). In step 42 The second reset signal of the second output node S2 is sampled by the active second SHR signal SHR-2 (31) and the second SHr transistor, and then held in the second SHR capacitor CSHR_2. Similarly, active The first SHR signal SHR-1 (32) and the first SHR transistor sample the first reset signal of the first output node S1 and then hold it in the SHR capacitor Cshr". Next, in step 43, the first signal is turned on. Transmit transistor TX (33). Next, in step 44, the second image signal of the second output node S2 is sampled by the active second SHS signal SHS-2 (34) and the second SHS transistor, and then It is held in the second SHS capacitor Cshs_2. Similarly, the first image signal of the first output node S1 is sampled by the active first SHS signal SHS_i (35) and the first SHS transistor, and then held in the first In the SHS capacitor CSHS1, the output Qrl of the first SHR capacitor cSHR1 and the output Qs2 of the second SHS capacitor Cshs_2 are electrically coupled at the node 14A according to their weightings. The above weights can be adjusted by adjustment (adjustable) ) SHR or SHS capacitors are obtained. In a similar situation, SHS capacitance 201 039 629
CsHS_l的輸出Qsl和第二SHR電容CsHR_2的輸出Qr2於 節點14B處各依其權重作電性耦接。接著，藉由加法器 14將節點14B的輸出（亦即，Qsl+Qr2)減去節點14A 的輸出（亦即，Qrl + Qs2 )(步驟45 )。 根據第二圖至第四圖所示的本發明實施例，由於光二 級體D之信號係由不同路徑以不同增益而被讀出，因此其 操作會類似於傳統結合長曝光影像及短曝光影像的效果， 〇 但是架構較傳統技術來得簡單。藉此，讀出系統的動態範 圍可以有效地增進且較為經濟。 以上所述僅為本發明之較佳實施例而已，並非用以限 定本發明之申請專利範圍；凡其它未脫離發明所揭示之精 神下所完成之等效改變或修飾，均應包含在下述之申請專 Q 利範圍内。 【圖式簡單說明】 第一圖顯示本發明實施例之具增強動態範圍的影像感測器 讀出系統。 第二圖顯示本發明實施例讀出系統（第一圖）的細部電路 圖。 11 201039629 第三圖顯示第二圖相關信號的時序圖。 第四圖顯示本發明實施例之操作步驟流程圖。 【主要元件符號說明】 10 像素電路 100 光二級體 102A 第一放大器 102B 第二放大器 12 讀出電路 120A 第一讀出次電路/第一 CDS電路 120B 第二讀出次電路/第二CDS電路 14 加法器 14A、14B 相加節點 30-35 信號時序的時間點 41-45 流程步驟 A、B 讀出電路的輸出 gl、g2 增益 SI、S2 放大器的輸出 wl、w2 權重 RST 重置電晶體 SF 源極隨耦器 TX 傳輸電晶體 12 201039629 D 光二級體 RSTD RSTD電晶體 NRSTD NRSTD電晶體 cf 迴授電容 Vcm〇 參考電壓 Bias_nl ' » Bias_n2、Bias_pl、Bias_p2 偏壓電晶體 SHR_1 第一 SHR電晶體 SHR 2 ❹ SHS_1 第二SHR電晶體 第一 SHS電晶體 SHS_2 第二SHS電晶體 〇SHR_l 第一 SHR電容 CsHR_2 第二SHR電容 〇SHS_l 第一 SHS電容 CsHS_2 第二SHS電容 〇 Qrl Qsl 第一 SHR電容之輸出 第一 SHS電容之輸出 Qr2 第二SHR電容之輸出 Qs2 第二SHS電容之輸出 13The output Qs1 of CsHS_1 and the output Qr2 of the second SHR capacitor CsHR_2 are electrically coupled at their respective nodes 14B according to their weights. Next, the output of node 14B (i.e., Qsl + Qr2) is subtracted by adder 14 from the output of node 14A (i.e., Qrl + Qs2) (step 45). According to the embodiment of the present invention shown in the second to fourth figures, since the signal of the photodiode D is read out with different gains by different paths, the operation is similar to the conventional combination of the long exposure image and the short exposure image. The effect, oh, but the architecture is simpler than traditional technology. Thereby, the dynamic range of the readout system can be effectively enhanced and economical. The above description is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention; all other equivalent changes or modifications which are not departing from the spirit of the invention should be included in the following Apply for a special Q range. BRIEF DESCRIPTION OF THE DRAWINGS The first figure shows an image sensor readout system with enhanced dynamic range in accordance with an embodiment of the present invention. The second figure shows a detailed circuit diagram of the readout system (first figure) of the embodiment of the present invention. 11 201039629 The third diagram shows the timing diagram of the signals related to the second diagram. The fourth figure shows a flow chart of the operation steps of the embodiment of the present invention. [Description of Main Element Symbols] 10 Pixel Circuit 100 Optical Secondary Body 102A First Amplifier 102B Second Amplifier 12 Readout Circuit 120A First Readout Secondary Circuit / First CDS Circuit 120B Second Readout Secondary Circuit / Second CDS Circuit 14 Adder 14A, 14B Add node 30-35 Signal timing time point 41-45 Flow step A, B Readout circuit output gl, g2 Gain SI, S2 Amplifier output wl, w2 Weight RST Reset transistor SF source Polar follower TX transmission transistor 12 201039629 D Optical diode RSTD RSTD transistor NRSTD NRSTD transistor cf feedback capacitor Vcm〇 reference voltage Bias_nl ' » Bias_n2, Bias_pl, Bias_p2 bias transistor SHR_1 first SHR transistor SHR 2 ❹ SHS_1 Second SHR transistor First SHS transistor SHS_2 Second SHS transistor 〇SHR_l First SHR capacitor CsHR_2 Second SHR capacitor 〇SHS_l First SHS capacitor CsHS_2 Second SHS capacitor 〇Qrl Qsl Output of the first SHR capacitor Output of a SHS capacitor Qr2 Output of a second SHR capacitor Qs2 Output of a second SHS capacitor 13