201039407 - 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種供金屬-絕緣體·金屬電容 (metal-insulator-metal capacitor，以下簡稱為MMC)使用的多層結構 • 的製法，特別是關於一種供具有高電容量密度之雙MMC(double MMC)結構使用的多層結構的製法。 ° 【先前技術】 電容元件常用於如射頻 IC(radio frequency integrated circuits， RFIC)或單晶微波 ic (monolithic microwave integrated eircuits，MMip 等積體電路中做為電子被動元件。常見之電容結構如金氧半導體 (MOS)電容、p-n接面電容以及MIM電容。其中，MIM電容在某些 應用中可提供較優於MOS電容及p-n接面電容之電性，這是由於 MOS電容及p-n接面電容皆會受限於其本身結構的問題，操作時半 G 導體電極產生空乏層(dePleti〇nlayer)，導致其頻率特性被限制。相 較之下’ MIM t料哺供較佳的辦及溫度細雜(frequency and temperature characteristics)。此外，MIM電容可在金屬内連線階 段形成，也降低了與CMOS前段製程整合的困難度或複雜度。 結構上’ MIM電容包括一電容絕緣層，例如PECVD介電層， 其係設置在下電極以及上電極之間。應電容往往需要佔據晶片相 '田大的面積而為了達到增加電路積集度以降低成本，MIM電容必 201039407 •須朝高電容量密度(capacitancedensity)發展，才能增加電路密度。美 國專利第6,977，198麟種MIM f容結敎純法，以將單位 電容值增大一倍，而該種結構或被稱為雙MMC結構。如第1圖所 不’ MIM電容結構10包含有一第一金屬層^，一第二金屬層μ • 設於第-金屬層12上方，並藉由—第—電容介電層13與第一金屬 . 層12電性絕緣。第三金屬層16設於第二金屬層14上方，並藉由一 第二電容介電層15與第二金屬層η電性絕緣。第三金屬層16上則 〇 覆有一頂蓋層(哪㈣的22，其可為氮化石夕或氧化石夕所構成。上述 MIM電容結構1〇係設於一沈積於基底1〇〇上的金屬層間介電層 中。上述MIM電容結構10之第一金屬層12、第一電容介電^ 13 與第二金屬層14構成一第一電容結構(Ci)，而第二金屬層14、第二 電容介電層15與第三金屬層16則構成—第二電容結構 電容結構10之第一金屬層12係經由一穿過金屬層間介電層12〇之 金屬導孔(via) 31與弟一端點線路(flrst terminai) 42電連接，第二金 ◎ 屬層14係經由一穿過金屬層間介電層12〇之金屬導孔32與第二端 點線路(second terminal)44電連接，而第三金屬層16則經由一穿過 金屬層間介電層120以及設於第三金屬層16上之頂蓋層(⑶口丨吵沈) 22之金屬導孔33與第一端點線路42電連接。換言之，第一金屬層 12與苐二金屬層16係為電性相連，形成第一金屬層12與第三金屬 層16上下將第二金屬層14夾住之類似三明治構造。 然而’在上述結構的第一金屬層的組成及製法上，仍可期待改 ' 良’以獲知具有更兩崩潰電壓(breakdown voltage of double MMC， 201039407 . BVD)及更長的時間相依介電層崩潰(time dependent dielectric breakdown，TDDB)壽命的雙 MMC 結構。 【發明内容】 本發明的一目的是提供一種製造供金屬-絕緣體_金屬電容使用 . 之多層結構之方法，如此用以製得的雙MMC結構的崩潰電壓更 高，且TDDB壽命更長。 〇 依據本發明的製造供金屬-絕緣體_金屬電容使用之多層結構之 方法，包括：提供一基底；於基底上形成一底電極板層，其中，於 25至4〇〇 C的溫度下進行一第一及一第二物理氣相沉積(physical vapor deposition ’ PVD)製程’以形成包括一鈦層及一氮化欽層於欽 層上的一鈦/氮化鈦(Ti/TiN)層做為底電極板層的頂部抗反射層(t〇p ARC) ’於頂部射層上形成一第一電容介電層；於一第一電容介 t層上形成-中間電極板層；於中間電極板層上形成—第二電容介 電層’及於第二電容介電層上形成—頂電極板層。 本發明係於製造底電極板層的頂部抗反射層時，以25至400¾ :二度進4 PVD製程以形成Ti/TiN層，如此於其上形成的介電層 幸又平π ^祕度小，製得的雙MMC能夠具有較高的崩潰電壓及 較長的TDDB壽命’但不影響電容值。 【實施方式】 6 201039407 «第2圖的程圖說明依攄本發明的製造供 驟I七供一基底，其可為任何在 例如r半導體_成於其地圓:::== 上形成-底電極板層，其中，於25至·。c的溫度下進行一第 第-PVD_ ’ _成包括—鈦層及—氮化 T刪層做為底電極板層的頂部抗反射層。詳言之，底電= 由多層結構所形成’因為本發明 _ 0疋 ϋ射Μη 〜之—在於底電極板層的頂部 抗反射層的形成，所以在頂部抗反射層下面的層為何種 要是適用做為電容的電極板且能與頂部抗反射層形= 好堆璺的夕層結構的材質均可以使用。 下文中更明確敘述底電極板層的形成。底電極板層的下声可為 金屬，或是可藉由例如先於基板上形成—則叫，做為_，再 於此Ti/TiN層上形成-層鋁(Α1)層而形成。Ti/TiN層的形成可㈣ 例如在室溫下利用PVD製程先形成一層鈦層，再於鈦層上形成1層 統鈦層而達成，然後，於此·N層上形成銘層，此可藉由例如 進订PVD製程而達成’溫度可為例如峨。即，此·_層 ^構成底電極板層的下層。_，進行頂部抗反射層的製作。頂^ 2反射層為鈦層與氮化鈦層堆疊而成的多層結構，以ρν〇製程製 但製程溫度特別是設定於25至侧。c，先於姆上藉由^ 衣程進行鈦層的沉積’再於此鈦層上藉由pvD製程進行氮化欽層的 沉積，而形成Τ1/™層’射各層厚度魏據後難針要使用的 201039407 •光波長來決定，_在後續進行高密度電容的製作而形細案化光 阻層的製程中達成抗反射的效果。 /' 之後，進行步驟3,於頂部抗反㈣上形成―第—電容介電層， 也就是，於頂部抗反射層的氮化鈦層上形成一介電層，例如，一 〇N〇 Ο ❹ mtride’UVSiN)層(具有好的紫外光透光率，可適用於有利用紫外光 照射晶片表面以抹除晶粒内龍(UVe職财的產品）、或p腦 層（即，電漿增強CVD製得的氧化物層）。 。當底電極板的頂部抗反射層(也就是鈦/氮化鈦層说在朋至 C、尤其是25〇至赋的溫度下形成時，使用〇n〇層、腦n 層、或醜層做為第-電容介電層，均可獲得 電容值的雙MMC裝置。 。。的、!St頂部抗反射層(也就是鈦/氮化鈦層)是在25至15〇 ^皿訂形成時，較佳使用〇N〇層及w謝層做為第—電容介 包曰k樣的多層結構做成的電容仍具有高BVD及高電容，但若 MPEOX層做騎—電容介電層’所得咖將下降。 然後進行步驟4，於—第—電容介鶴 ===麵細_，娜軸電 、下層的第-電容介電層形成良好堆叠的多層結構的話均 8 201039407201039407 - VI. Description of the Invention: [Technical Field] The present invention relates to a method for manufacturing a multilayer structure for metal-insulator-metal capacitor (MMC), in particular A method of fabricating a multilayer structure for use in a dual MMC (double MMC) structure having a high capacitance density. ° [Prior Art] Capacitance components are commonly used as electronic passive components in integrated circuits such as radio frequency integrated circuits (RFIC) or monolithic microwave integrated eircuits (MMip). Common capacitor structures such as gold oxide Semiconductor (MOS) capacitors, pn junction capacitors, and MIM capacitors. Among them, MIM capacitors provide better electrical properties than MOS capacitors and pn junction capacitors in some applications, due to both MOS capacitors and pn junction capacitors. It will be limited by its own structure. When operating, the half-G conductor electrode produces a depletion layer (dePleti〇nlayer), which causes its frequency characteristics to be limited. In contrast, 'MIM t feeds better and temperature is fine. In addition, the MIM capacitor can be formed during the metal interconnection phase, which also reduces the difficulty or complexity of integration with the CMOS front-end process. Structurally, the MIM capacitor includes a capacitor insulating layer such as PECVD dielectric. a layer, which is disposed between the lower electrode and the upper electrode. The capacitance is required to occupy a large area of the wafer phase in order to increase the circuit product. In order to reduce the cost, the MIM capacitor must be 201039407 • It must be developed towards high capacitance density (capacitance density) to increase the circuit density. US Patent No. 6,977,198 MIM f capacitance 敎 pure method to increase the unit capacitance value Double, and the structure is referred to as a double MMC structure. As shown in FIG. 1, the MIM capacitor structure 10 includes a first metal layer ^, and a second metal layer μ is disposed above the first metal layer 12, And electrically insulated from the first metal layer 12 by the first capacitor dielectric layer 13. The third metal layer 16 is disposed over the second metal layer 14 and is provided by a second capacitor dielectric layer 15 and a second The metal layer η is electrically insulated. The third metal layer 16 is covered with a cap layer (which is 22), which may be formed by nitriding or oxidizing stone. The above MIM capacitor structure 1 is provided in a deposition layer. In the inter-metal dielectric layer on the substrate 1 , the first metal layer 12 , the first capacitor dielectric 13 and the second metal layer 14 of the MIM capacitor structure 10 form a first capacitor structure (Ci), and The second metal layer 14, the second capacitor dielectric layer 15 and the third metal layer 16 form a second capacitor The first metal layer 12 of the capacitor structure 10 is electrically connected to the first terminal line (first terminai) 42 via a metal via 31 passing through the inter-metal dielectric layer 12, and the second gold layer 14 The first metal layer 16 is electrically connected to the second terminal 44 via a metal via 32 passing through the inter-metal dielectric layer 12, and the third metal layer 16 is provided through the inter-metal dielectric layer 120. The metal via 33 on the cap layer (3) of the third metal layer 16 is electrically connected to the first terminal line 42. In other words, the first metal layer 12 and the second metal layer 16 are electrically connected to form a sandwich-like structure in which the first metal layer 12 and the third metal layer 16 sandwich the second metal layer 14 up and down. However, in the composition and manufacturing method of the first metal layer of the above structure, it is still expected to change 'good' to know that there are two breakdown voltages (breakdown voltage of double MMC, 201039407. BVD) and a longer time dependent dielectric layer. A dual MMC structure of time dependent dielectric breakdown (TDDB) lifetime. SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of fabricating a multilayer structure for use with a metal-insulator-metal capacitor, such that the double MMC structure produced has a higher breakdown voltage and a longer TDDB lifetime. A method of fabricating a multilayer structure for use in a metal-insulator-metal capacitor according to the present invention, comprising: providing a substrate; forming a bottom electrode layer on the substrate, wherein the layer is formed at a temperature of 25 to 4 ° C a first and a second physical vapor deposition 'PVD process' to form a titanium/titanium nitride (Ti/TiN) layer comprising a titanium layer and a nitride layer on the seed layer a top anti-reflective layer (t〇p ARC) of the bottom electrode layer forms a first capacitive dielectric layer on the top shot layer; a middle electrode layer on the first capacitor dielectric layer; and an intermediate electrode plate A second capacitor dielectric layer is formed on the layer and a top electrode layer is formed on the second capacitor dielectric layer. The invention is used for manufacturing the top anti-reflective layer of the bottom electrode layer, and adopts a process of 25 to 4003⁄4: 2 degrees to form a Ti/TiN layer, so that the dielectric layer formed thereon is flat and π ^ secret Small, the resulting dual MMC can have a higher breakdown voltage and a longer TDDB lifetime 'but does not affect the capacitance value. [Embodiment] 6 201039407 «The diagram of Fig. 2 illustrates the manufacture of the substrate according to the present invention, which can be formed on any substrate, for example, r semiconductor - formed on its ground circle:::== The bottom electrode plate layer, wherein, at 25 to ·. A first -PVD_' is formed at a temperature of c to include a titanium layer and a nitride layer as a top anti-reflection layer of the bottom electrode layer. In detail, the bottom electricity = formed by the multilayer structure 'because the present invention _ 0 疋ϋ Μ ～ ～ is in the formation of the top anti-reflective layer of the bottom electrode layer, so what is the layer under the top anti-reflective layer? It can be used as the electrode plate of the capacitor and can be used with the top anti-reflective layer shape = good stacking layer structure. The formation of the bottom electrode layer is more clearly described below. The underlying sound of the bottom electrode layer may be metal or may be formed by, for example, forming on the substrate, as _, and forming a layer of aluminum (Α1) on the Ti/TiN layer. The formation of the Ti/TiN layer can be achieved, for example, by forming a titanium layer by a PVD process at room temperature and then forming a titanium layer on the titanium layer, and then forming a layer on the N layer. The temperature can be, for example, 峨 by, for example, a predetermined PVD process. That is, this layer _ constitutes the lower layer of the bottom electrode layer. _, the production of the top anti-reflection layer. The top 2 reflective layer is a multi-layered structure in which a titanium layer and a titanium nitride layer are stacked, and is manufactured by a ρν〇 process, but the process temperature is particularly set at 25 to the side. c, prior to the deposition of the titanium layer by the coating process, and then the deposition of the nitride layer on the titanium layer by the pvD process, and the formation of the thickness of the layer 1/TM layer To use the 201039407 • Light wavelength to determine, _ in the subsequent high-density capacitor fabrication and shape of the photoresist layer to achieve anti-reflection effect. /', after step 3, a "first" capacitor dielectric layer is formed on the top anti-reflection (four), that is, a dielectric layer is formed on the titanium nitride layer of the top anti-reflection layer, for example, a 〇N〇Ο Mt mtride 'UVSiN) layer (with good UV light transmittance, can be applied to irradiate the surface of the wafer with ultraviolet light to erase the grain inner dragon (product of UVe business), or p brain layer (ie, plasma) Enhancing the oxide layer produced by CVD). When the top anti-reflective layer of the bottom electrode plate (that is, the titanium/titanium nitride layer is formed at a temperature of from Cang to C, especially 25 〇 to Fu, use 〇n The 〇 layer, the brain n layer, or the ugly layer is used as the cascode dielectric layer, and the double MMC device with the capacitance value can be obtained. The top anti-reflection layer (that is, the titanium/titanium nitride layer) is When 25 to 15 〇 ^ 皿 皿 皿 皿 , , 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 电容 电容 电容 电容 电容 电容 电容 电容 电容 MP MP MP MP MP MP The layer is made to ride - the capacitor dielectric layer 'the resulting coffee will drop. Then proceed to step 4, in the - the first capacitor - = = = face fine _, Na axis, the lower layer of the first A dielectric layer formed, then a good stacked multilayer structure are 8,201,039,407
PVD =成例如金屬層’其可為例如画層。其可利_ 然後，進行步驟5,於中間電極板層上形成一第 並無特別限制，只要是適用做為電容的介電層Μ 用、=板層能夠形成良好堆疊的多層結構的話均可使 般為了錢上的便利，使用與第―電容介電層相同的材料。 ❹ ❹ 然後進行步驟6，於第二電容介騎场成 =材:伽_，只要是適用做為電容二並1 與下層的第二電容介電層形成良好堆疊的多層結構的話均可使用， 例如金屬層，射為例如™層，可姻例如咖製程形成。 依據本發明的方法形成的多層結構如第3圖所示， 底聊上’㈣爛綱_⑽、f物層52/中 第：1容侧56、及亀朗58。底電極板 曰“括由下而上的下層6G及頂部抗反射層62。頂部抗反射層 62可包括由下而上的鈦層63及氮化鈦層糾。下層6〇則可進一步二 湖如由下而上的鈦層、氮化鈦層、及紹層。各層厚度可依㈣而 定，並沒有制限制。於本發明之—較佳具體實施例中，做為 極板層的Ti/TiN/A贿iN層的各層厚度可分別為例如2〇〜挪埃 H)〇〜300埃、1500〜5_埃、2〇〜2〇〇埃、及1〇〇〜_埃丨第一電容 介電層的厚度可為例如300〜_埃；中間電極板層的厚度可為例2 9 201039407 -1000〜_矣；第二電容介電層的厚度可為例如埃；及頂 電極板層的厚度可為例如誦〜膽埃。但本發觀不侷限於此， 各層厚度可依裝置所需而定。 上述多層結構表面上可再形成一頂蓋層，厚度可為例如 1000〜2_埃。此多層結構可適舰為如第4騎示的具有高密度 的雙MMC結構，例如藉由f知的微影、_、與填人插塞等製程 而製仔。此電容結構形成於基底雇上及金屬層間介電層⑽中。 底電極板70、第-電容介電層72、及中間電極㈣構成一下電容 (C3)結構；中間電極板74、第二電容介電層％、及頂電極板％構 成-上電容(C4)、结構。又，其中一部分的辟極板7〇上覆蓋著一剩 餘厚度的第-電容介電層72，一部分的中間紐板％上覆蓋著一 剩餘厚度㈣二電容介電層。金屬導孔31穿過金屬層間介電層 120及剩餘厚度的第-電容介電層72，以將底電極板㈣第一端點 線路42電連接；金屬導孔32穿過金屬層間介電層12〇及剩餘厚度 的第二電容介電層76，以將中_極板74與第二端點線路44電連 接；金屬導孔33穿過金屬層間介電層m及頂蓋層66將頂電極板 78與第-端點線路42電連接。如此，底電極板％與頂電極板％ 係為電性相連’形成底電極板7〇與了膽碰78上下將中間電極板 74夾住賴似三明治構造。底電極板—般利科導财置的金屬内 連線的第三詹金屬線(Metal 3)製做。第一端點線路42與第二端點線 路44通常利用金屬内連線的帛四層金屬、線(硫㈤句製作。 201039407 ' ‘則試依據本發明的方法製得的多層結構的性質，對上述的 ⑽、腦N、P服介電層的表面進行針孔測試，續察多層結 .構的表面⑽造度。針孔試驗是將晶圓試片浸泡於NH4〇h㉟h处水 溶液中，達L5小時，然後於400ΐ下進行12分鐘的退火(_—), 然後以光學顯微鏡觀察膜的表面。晶圓試片如下述製造：在p型石夕 晶圓上塗覆-5_埃厚度的PE職氧化物_行賴增強化學 氣相沉積而由TEOS㈣的氧化物膜），然後依序沉積遍埃的銘 〇層，及50埃的欽層與500埃的氮化鈦層形成的頂部抗反射層，再個 別沉積裝置所需厚度的ΟΝΟ、UVSiN、及PEOX電容介電層於頂部 抗反射層上。如此可觀察到，當頂部抗反射層是在励。c的溫度； 形成時，針孔密度會較頂部抗反射層在3〇(rc下形成時的針孔密度 稍高。此在PEOXf容介電層上的情形尤其明顯，也就是說，當頂 部抗反射層是在100°C的溫度下形成時，ΡΕ〇χ電容介電層表面的 針孔密度特別的高。介電層與底電極板的粗链介面將顯著降低崩潰 電壓。PVD = into, for example, a metal layer 'which may be, for example, a picture layer. Then, the step 5 is performed on the intermediate electrode plate layer without any particular limitation, as long as it is suitable for the dielectric layer of the capacitor, and the plate layer can form a well-stacked multilayer structure. For the convenience of money, the same material as the first capacitor dielectric layer is used. ❹ ❹ Then proceed to step 6, in the second capacitor, the field: gamma, as long as it is suitable for the capacitor diode 1 and the lower layer of the second capacitor dielectric layer to form a good stack of multi-layer structure, can be used, For example, a metal layer, such as a TM layer, can be formed, for example, by a coffee process. The multilayer structure formed by the method of the present invention is as shown in Fig. 3, and the bottom layer is '(4) 纲 _ (10), f layer 52 / middle: 1 side 56, and 亀 58. The bottom electrode plate 曰 "includes the bottom layer 6G and the top anti-reflection layer 62. The top anti-reflection layer 62 may include a titanium layer 63 and a titanium nitride layer from bottom to top. The lower layer 6 可 may further two lakes. The bottom layer is a titanium layer, a titanium nitride layer, and a layer. The thickness of each layer may be determined according to (4), and there is no limitation. In the preferred embodiment of the present invention, Ti as a plate layer The thickness of each layer of the /TiN/A bribe iN layer can be, for example, 2 〇 to No. H) 〇 ~ 300 Å, 1500 〜 5 Å, 2 〇 ~ 2 〇〇, and 1 〇〇 ~ _ 丨 first The thickness of the capacitor dielectric layer may be, for example, 300 Å Å; the thickness of the intermediate electrode layer may be Example 2 9 201039407 -1000 〜 矣; the thickness of the second capacitor dielectric layer may be, for example, angstrom; and the top electrode layer The thickness of the layer may be, for example, 1000~2_. The thickness of each layer may be determined according to the needs of the device. The top layer of the multilayer structure may be further formed with a cap layer, and the thickness may be, for example, 1000~2_ The multi-layer structure can be a high-density double MMC structure as shown in the fourth riding, for example, by lithography, _, and filling plugs. The capacitor structure is formed on the substrate and the inter-metal dielectric layer (10). The bottom electrode plate 70, the cascode dielectric layer 72, and the intermediate electrode (4) constitute a lower capacitor (C3) structure; the intermediate electrode plate 74, The second capacitor dielectric layer %, and the top electrode plate % constitute an upper capacitor (C4), structure. Further, a part of the anode plate 7 is covered with a remaining thickness of the cascode dielectric layer 72, a part of The intermediate plate is covered with a remaining thickness (four) of two capacitor dielectric layers. The metal via 31 passes through the inter-metal dielectric layer 120 and the remaining thickness of the cascode dielectric layer 72 to the first end of the bottom electrode plate (four) The point line 42 is electrically connected; the metal via 32 passes through the inter-metal dielectric layer 12 and the remaining thickness of the second capacitor dielectric layer 76 to electrically connect the middle plate 74 to the second end line 44; The hole 33 electrically connects the top electrode plate 78 and the first terminal line 42 through the inter-metal dielectric layer m and the cap layer 66. Thus, the bottom electrode plate % is electrically connected to the top electrode plate % to form a bottom electrode The plate 7 〇 and the biliary bump 78 sandwich the intermediate electrode plate 74 into a sandwich-like structure. The third-metal wire (Metal 3) of the metal interconnect of the board-like franchise is made. The first end line 42 and the second end line 44 usually use a metal interconnect of the 帛 four-layer metal. , line (sulphur (five) sentence production. 201039407 ' ' Then test the properties of the multilayer structure prepared according to the method of the present invention, perform pinhole test on the surface of the above (10), brain N, P dielectric layer, continue to examine the multilayer knot The surface of the structure (10). The pinhole test is to soak the wafer test piece in an aqueous solution at NH4〇h35h for L5 hours, then annealed at 1400° for 12 minutes (_—), and then observe the film with an optical microscope. The surface of the wafer is manufactured as follows: a p-type Shi Xi wafer is coated with a thickness of -5 angstroms of PE oxide oxide _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Depositing the enamel layer of the enamel, and the top anti-reflective layer formed by the 50 angstrom layer and the 500 angstrom titanium nitride layer, and the thickness of the yttrium, UVSiN, and PEOX capacitor dielectric layers of the individual deposition device are applied to the top. On the reflective layer. It can be observed that when the top anti-reflective layer is in the excitation. The temperature of c; when formed, the pinhole density will be slightly higher than the top anti-reflective layer at 3 〇 (the pinhole density when formed under rc. This is especially the case on the PEOXf dielectric layer, that is, when the top When the antireflection layer is formed at a temperature of 100 ° C, the pinhole density on the surface of the tantalum capacitor dielectric layer is particularly high. The thick chain interface of the dielectric layer and the bottom electrode plate will significantly reduce the breakdown voltage.
G 將依據本發明的方法製得的多層結構應用於如第4圖所示的雙 MMC，測定錢潰電壓及電容，以_失敗率(⑶咖金制咖)(％) 對雙MMC的崩潰電壓(2BVDMMC)(單位：伏特)作圖，及以累積 失敗率(％)對雙MMC電容(2CMMC)(單位：师乍圖，結果各如第5 圖及第6圖所示。當介電層為而沉層時，頂部抗反射層的製作溫 度(例如300 C或100 C)並不會對崩潰電壓有不良影響，但是當介電 -層為PEQX料，若於勘。(：製造頂部抗反射層的話，崩潰電壓下 11 201039407 - 降。並且，介電層為UVSiN層時，電容值較高。 第7圖顯示使用依據本發明的方法製得的多層結構製造如第4 圖所示的雙MMC裝置，其封裝級可靠度的TDDB (pLR_TDDB)測 試對晶圓級可靠度的BVD(WLR-BVD)測試的作圖。所使用的電容 介電層為PEOX層。Vg+表示正電壓施加在金屬内連線的第四層金 觸(製成第-及第二端點_ 42及44)上，應力歧㈣ess eurrent) Ο 由細層金屬層流向第三層金屬層。vg—表示正電壓施加在金屬内 連線的第三層金屬層(即’底電極板層)上，應力電流由第三層金屬 層流向第四層金屬層。由圖中可看出，當頂部抗反射層是在高溫下 例如3〇(TC製成時，所得雙罐C電容在TDDB壽命及BVD都相對 較高，而溫度漸低至例如KKTC時，所得雙MMC電容的TDDB壽 命及BVD相對較低。 可 蚊前技齡較之，發明人舰在製造頂部抗反㈣時，依據 後續的電容介電層材料選用適當的pvD製程溫度，這樣的多層 所製得的雙匿結構，可具有較高则及較長的勘B壽命°。 以上所述僅為本發明之較佳實施例，凡依本發明申請專 所做之均錢化與修飾，皆闕本發明之涵蓋範圍。 国 【圖式簡單說明】 第1圖顯示一習知的雙MMC結構。 12 201039407 -第2圖顯不依據本發明的製造供金屬-絕緣體-金屬電容使用的多層 結構的方法的流程圖。 第3圖顯示依據本發明的方法製得的多層結構。 $ 4圖顯示使用本發明的方法製得的多層、结構製得的雙MMC結構。 第5及6圖分別顯示使用依據本發明的方法製得的多層結構以製得 雙MMC，分別測定其崩潰電壓及電容所得的作圖。G. The multilayer structure prepared according to the method of the present invention is applied to the double MMC as shown in Fig. 4, and the collapse of the voltage and the capacitance, and the failure rate ((3) coffee maker) (%) for the collapse of the double MMC Voltage (2BVDMMC) (in volts) is plotted, and cumulative failure rate (%) vs. double MMC capacitor (2CMMC) (unit: 乍 diagram, results are shown in Figure 5 and Figure 6. When dielectric When the layer is a sinking layer, the fabrication temperature of the top anti-reflective layer (for example, 300 C or 100 C) does not adversely affect the breakdown voltage, but when the dielectric-layer is a PEQX material, if it is inspected. In the case of the anti-reflection layer, the breakdown voltage is 11 201039407 - and the capacitance value is higher when the dielectric layer is the UVSiN layer. Figure 7 shows the fabrication of the multilayer structure produced by the method according to the present invention as shown in Fig. 4. The dual-MMC device, its package-level reliability TDDB (pLR_TDDB) test plots for wafer-level reliability BVD (WLR-BVD) testing. The capacitor dielectric layer used is the PEOX layer. Vg+ indicates positive voltage application. On the fourth layer of gold contact in the metal interconnect (made of the first and second endpoints _ 42 and 44), the stress differential (four) ess eurrent) Ο Flowing from the thin metal layer to the third metal layer. vg—represents that a positive voltage is applied to the third metal layer of the metal interconnect (ie, the bottom electrode layer), and the stress current flows from the third metal layer to the fourth layer. Layer metal layer. As can be seen from the figure, when the top anti-reflective layer is made at a high temperature such as 3 〇 (TC made, the resulting double-tank C capacitor is relatively high in TDDB lifetime and BVD, and the temperature is gradually lowered to, for example, At KKTC, the TDDB lifetime and BVD of the resulting double MMC capacitors are relatively low. Compared with the pre-mosquito technology, the inventor's ship uses the appropriate pvD process temperature according to the subsequent capacitor dielectric layer material when manufacturing the top anti-reverse (4). The double-densation structure produced by such a plurality of layers can have a higher and longer B life. The above is only a preferred embodiment of the present invention, and the average cost of the application according to the present invention is And the modifications are all covered by the present invention. [Simplified description of the drawings] Figure 1 shows a conventional double MMC structure. 12 201039407 - Figure 2 shows the manufacture of metal-insulator-metal capacitors according to the present invention. Flowchart of the method of using the multilayer structure. Figure 3 A multilayer structure made in accordance with the method of the present invention is shown. Figure 4 shows a multilayer, structurally produced double MMC structure made using the method of the present invention. Figures 5 and 6 show the use of the method according to the present invention, respectively. The multilayer structure was used to produce dual MMC, and the resulting breakdown voltage and capacitance were measured.
第7圖顯不使用依據本發明的方法製得的多層結構以製得雙MMC 〇 蚪，封裝級可靠度的TDDB測試對晶圓級可靠度的BVD測試的作 圖。 【主要元件符號說明】 1 ' 2 ' 3 ' 4、5、6 步驟 12 第一金屬層 14 第二金屬層 16 第三金屬層 31 金屬導孔 33 金屬導孔 44 第二端點線略 52 第一電容介電層 56 第二電容介電層 60 下層 63 鈦層 10 電容結構 13 第一電容介電層 15 第二電容介電層 22 頂蓋層 32 金屬導孔 42 第一端點線路 底電極板層 54 中間電極板層 58 頂電極板層 62 頂部抗反射層 13 201039407 64 氮化鈦層 66 頂蓋層 70 底電極板 72 第一電容介電層 74 中間電極板 76 第二電容介電層 78 頂電極板 100 基底 120 金屬層間介電層 Ci 第一電容結構 C2 第二電容結構 C3 下電容結構 c4 上電容結構 ❹ 14Figure 7 shows the use of a multilayer structure fabricated in accordance with the method of the present invention to produce a dual MMC 蚪, package-level reliability TDDB test for wafer level reliability BVD testing. [Main component symbol description] 1 ' 2 ' 3 ' 4, 5, 6 Step 12 First metal layer 14 Second metal layer 16 Third metal layer 31 Metal via hole 33 Metal via hole 44 Second end point line 52 A capacitor dielectric layer 56 a second capacitor dielectric layer 60 a lower layer 63 a titanium layer 10 a capacitor structure 13 a first capacitor dielectric layer 15 a second capacitor dielectric layer 22 a cap layer 32 a metal via 42 a first end line bottom electrode Plate layer 54 intermediate electrode plate layer 58 top electrode plate layer 62 top anti-reflection layer 13 201039407 64 titanium nitride layer 66 top cover layer 70 bottom electrode plate 72 first capacitor dielectric layer 74 intermediate electrode plate 76 second capacitor dielectric layer 78 top electrode plate 100 substrate 120 metal interlayer dielectric layer Ci first capacitor structure C2 second capacitor structure C3 lower capacitor structure c4 upper capacitor structure ❹ 14