201037597201037597
【發明所屬之技術領域】 一本發明係有關於一種音頻/視頻信號處理器，更有關於 一種具有雙晶片之音頻/視頻信號處理器。 【先則技術】 ^頻/視頻播放裝置，例如電視機或電腦，可根據來自 2入/類比調諧器（或是混合調諧器（hybrid tuner))或者 來^各種介面之類比與數位信號來顯示影像且播放聲音， 而這二；丨面例如有Djub連接器、色差輸入端（⑶ mpUt)、以及複合式輸入端（C VB S ) /S輸入端子（S - Video )。 因此，在一播放裝置中，用來處理來自輸入/類比調諧器（或 是混合調諧器（hybrid tuner))或者來自各種介面之類比 與數位信號的音頻/視頻信號處理器，必須以球閘陣列封裝 (ball grid array，BGA)方式來製造，以達到較多數量的 接腳，但是卻增加了成本。 【發明内容】 本發明提供一種音頻/視頻信號處理器，其包括第一晶 • S曰 片、匯流排、以及第二晶片。第一晶片透過至少一輪入輸 出介面來接收具有顯示與聲音資訊之至少一輸入信號，且 轉換輸入信號以產生一轉換信號。匯流排連接第一晶片。 第二晶片透過匯流排接收轉換信號，且處理轉換信號以產 生顯示與聲音信號來顯示與播放。第一晶片舆第二晶片以 相同之封裝方式來包裝，且第二晶片以比第一晶片更為高 階的製程來製造。在一些實施例中，此封裝方夫是方形扁 4 201037597 平封裝（quad flat package ’ QFP )方式，且第二晶片以90nm 製程來製造，第一晶片以〇.18um製程來製造。 在一些實施例中，第二晶片包括第一處理模組、第二 處理模組、第三處理模組、以及記憶體。第一處理模組處 理來自第一晶片之轉換信號以產生一處理後視頻信號與一 處理後音頻信號。第二處理模組與第三處理模組分別處理 轉換信號之處理後音頻信號與處理後視頻信號，以產生影 像與聲音信號，用以顯示與播放。此記憶體由第一處理器 〇 與第三處理器來存取。 在一些實施例中，第一晶片包括解調變單元以及轉換 單元。解調變單元接收一數位信號以作為輸入信號，並產 生轉換信號給第二晶片。轉換單元接收一類比信號以作為 輸入信號，並產生轉換信號給該第二晶片。第一晶片更包 括介面控制單元與處理裝置。介面控制單元控制處理裝置 去透過匯流排接收來自解調變單元之轉換信號、來自解調 變單元之轉換信號進行解擾亂舆解密，且將已解擾亂與解 Ο 密之轉換信號透過介面控制單元傳送至第二晶片。 【實施方式】 為使本發明之上述目的、特徵和優點能更明顯易懂， 下文特舉一較佳實施例，並配合所附圖式，作詳細說明如 下。 第1圖係表示根據本發明實施例之音頻/視頻信號處理 器。參閱第1圖，音頻/視頻信號處理器1包括兩個晶片10 及11以及匯流排12。晶片10支援音頻/視頻信號處理器之 ♦ 類比部分，包括音頻/視頻信號無線收發器、視頻信號解調 5 201037597 變^類比-數位轉換器、數位-類比轉換器等等。晶片η 士支援曰？/視頻信號處理器之數位部分，包括視頻解碼 器、:頻^號處理器、視頻信號處理器等等。晶片10及 11之每一者具有複數接腳，且晶片10透過匯流排12來連 接晶_片11。 參閱第1圖’晶片1包括數位電視（DTV)解調變單 元 20a 類比數位轉換（anai〇g_t〇_dighai c〇nverting，adC) 單兀2〇b、SIF/PIF類比數位轉換（SIF/PIF ADC )單元20c、 〇向解析多媒體影音介面（High Definition Multimedia Interface，HDMI)接收單元2〇d、視頻數位類比轉換 (digital-to-analog，DAC)單元20f、以及音頻類比數位轉 換/數位類比轉換（ADC/DAC)單元20g。晶片1〇接收來 自不同輸入/輸出介面且具有影像與聲音資訊的類比或數 位信號，這些不同的輸入/輸出介面包括混合調諧器（hybrid tuner) T20、色差輸入端（comp〇nent _此）T2i、D-Sub 連接器T22、複合式輸入端（CVBS ) /S輸入端子（s_vide〇 ) 〇 T23、HDMI連接器T24、以及天線T25。晶片1〇也可輸出 數位信號至SCART-OUT端T26。 參閱第2圖’晶片10之第一部份接腳p 1透過匯流排 連接至晶片11。晶片10之第二部份接腳P2是給ADC單 元20b來連接至色差輸入端T21、D-Sub連接器T22、及 CVBS/S-Video輸入端T23。此外，晶片1〇之第三部份接 腳P3是給SIF/PIF ADC單元20c來連接至混合調諸器 T20，晶片10之第四部份接腳P4是給SIF/PIF ADC單元 20使用，晶片10之第五部份接腳P5是給視頻DAC單元 201037597 2沉連接至SCART-OUT端T26,且晶片10之第六部份接 腳P6是給HDMI接收單元2〇d來連接至HDMI連接器 T24曰曰片1〇之剩餘接腳將根據系統需求而配置給其他應 用。在此貫施例中，晶片1〇之第一至第六部分接腳 的位置僅為一個範例。在一些實施例中，給晶片〗〇來使用 而連接至晶片11的接腳以及連接混合調错器T2〇、色差輸 入端 Τ21、D-Sub 連接器 Τ22、CVBS/S-Video 輸入端 Τ23、 HDMI連接器T24、以及的接腳之位置與排列根據電路設計 〇 與系統需求來決定。 回來參閱第1圖，在晶片1〇中，ADC單元20b接收來 自類比輸入端之類比信號，例如來自色差輸入端Τ21、 D-Sub連接器T22、以及CVBS/S_Video輸入端T23之信 號，並將此類比信號轉換為一數位信號，以作為一對應轉 換信號。ADC單元20b透過匯流排12將此對應轉換信號 傳送至晶片11。SIF/PIF ADC單元20c接收來自混合調諧 器T20之類比信號，並產生一數位信號以作為一對應轉換 © 信號。SIF/PIF ADC單元20c也透過匯流排12將此對應轉 換信號傳送至晶片11。DTV解調變器20a接收來自數位輸 入端之數位信號，例如來自混合調諧器T20或天線T25之 數位信號’並產生轉換資料串流以作為一對應轉換信號。 20c。DTV解調變器20a也透過匯流排12將此對應轉換信 號傳送至晶片11。在一實施例中，混合調諧器T20可接收 類比與數位信號。在其他實施例中，ADC單元20d可接收 來自專用類比調諧器之類比信號，而DTV解調變器20a可 接收來自專用類比調諧器之數位信號。 7 201037597 片^包括處理模組21與22以及音頻處理模h 處理早U包括音頻解碼單元遍、解^^3。 片10之轉換>f§號中的視頻作合日 自日日BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to an audio/video signal processor, and more particularly to an audio/video signal processor having a dual chip. [First-class technology] FM/video playback devices, such as TVs or computers, can be displayed according to analogy and digital signals from 2 input/analog tuners (or hybrid tuner) or various interfaces. The image and the sound are played, and the two sides are, for example, a Djub connector, a color difference input terminal ((3) mpUt), and a composite input terminal (C VB S ) / S input terminal (S - Video). Therefore, in a playback device, an audio/video signal processor for processing analog/digital signals from an input/analog tuner (or hybrid tuner) or from various interfaces must be a ball gate array. A ball grid array (BGA) method is used to achieve a larger number of pins, but at an increased cost. SUMMARY OF THE INVENTION The present invention provides an audio/video signal processor including a first chip, a bus bar, and a second wafer. The first chip receives at least one input signal having display and sound information through at least one wheel-in output interface, and converts the input signal to generate a conversion signal. The bus bar is connected to the first wafer. The second wafer receives the converted signal through the bus bar and processes the converted signal to produce a display and sound signal for display and playback. The first wafer and the second wafer are packaged in the same package, and the second wafer is fabricated in a higher order process than the first wafer. In some embodiments, the package is a square flat 4 201037597 quad flat package 'QFP' mode, and the second wafer is fabricated in a 90 nm process, the first wafer being fabricated in a 〇.18um process. In some embodiments, the second wafer includes a first processing module, a second processing module, a third processing module, and a memory. The first processing module processes the converted signal from the first wafer to produce a processed video signal and a processed audio signal. The second processing module and the third processing module respectively process the processed audio signal and the processed video signal of the converted signal to generate image and sound signals for display and playback. This memory is accessed by the first processor 〇 and the third processor. In some embodiments, the first wafer includes a demodulation unit and a conversion unit. The demodulation unit receives a digital signal as an input signal and generates a conversion signal to the second wafer. The conversion unit receives an analog signal as an input signal and generates a conversion signal to the second wafer. The first wafer further includes an interface control unit and a processing device. The interface control unit controls the processing device to receive the converted signal from the demodulation unit through the bus bar, the converted signal from the demodulation unit to perform descrambling and decryption, and the de-scrambled and de-embedded conversion signal is transmitted through the interface control unit. Transfer to the second wafer. The above described objects, features and advantages of the present invention will become more apparent from the following description. Figure 1 is a diagram showing an audio/video signal processor in accordance with an embodiment of the present invention. Referring to FIG. 1, the audio/video signal processor 1 includes two wafers 10 and 11 and a bus bar 12. The chip 10 supports an analog/audio signal processor ♦ analogy, including audio/video signal radio transceivers, video signal demodulation 5 201037597 analog analog-to-digital converters, digital-to-analog converters, and the like. Wafer η support? The digital portion of the video signal processor, including the video decoder, the frequency processor, the video signal processor, and the like. Each of the wafers 10 and 11 has a plurality of pins, and the wafer 10 is connected to the wafer 11 through the bus bar 12. Refer to Figure 1 'Wafer 1 includes digital TV (DTV) demodulation unit 20a analog-to-digital conversion (anai〇g_t〇_dighai c〇nverting, adC) Single 兀2〇b, SIF/PIF analog-to-digital conversion (SIF/PIF ADC) unit 20c, high-resolution multimedia interface (HDMI) receiving unit 2〇d, digital-to-analog (DAC) unit 20f, and audio analog-to-digital conversion/digital analog conversion (ADC/DAC) unit 20g. The chip 1 receives analog or digital signals from different input/output interfaces and has image and sound information. These different input/output interfaces include a hybrid tuner T20 and a color difference input (comp〇nent_this) T2i , D-Sub connector T22, composite input (CVBS) / S input terminal (s_vide 〇) 〇 T23, HDMI connector T24, and antenna T25. The chip 1〇 can also output a digital signal to the SCART-OUT terminal T26. Referring to Fig. 2, the first portion of the pad 10 of the wafer 10 is connected to the wafer 11 through the bus bar. The second partial pin P2 of the chip 10 is connected to the ADC unit 20b to the color difference input terminal T21, the D-Sub connector T22, and the CVBS/S-Video input terminal T23. In addition, the third portion of the chip P3 is connected to the SIF/PIF ADC unit 20c to the mixer T20, and the fourth portion of the chip 10 is used for the SIF/PIF ADC unit 20. The fifth part of the pin 10 of the chip 10 is connected to the SCART-OUT terminal T26 for the video DAC unit 201037597 2, and the sixth part of the pin P6 of the chip 10 is connected to the HDMI receiving unit 2〇d to the HDMI connection. The remaining pins of the T24 chip will be configured for other applications according to system requirements. In this embodiment, the positions of the first to sixth partial pins of the wafer 1 are only an example. In some embodiments, the chip is used to connect to the pins of the wafer 11 and to the hybrid mixer T2, the color difference input terminal 21, the D-Sub connector Τ22, the CVBS/S-Video input terminal 、23, The position and arrangement of the HDMI connector T24 and the pins are determined according to the circuit design and system requirements. Referring back to FIG. 1, in the chip, the ADC unit 20b receives analog signals from the analog input, such as signals from the color difference input terminal Τ21, the D-Sub connector T22, and the CVBS/S_Video input terminal T23, and Such a ratio signal is converted into a digital signal as a corresponding conversion signal. The ADC unit 20b transmits the corresponding conversion signal to the wafer 11 through the bus bar 12. The SIF/PIF ADC unit 20c receives the analog signal from the hybrid tuner T20 and generates a digital signal as a corresponding conversion © signal. The SIF/PIF ADC unit 20c also transmits the corresponding conversion signal to the wafer 11 through the bus bar 12. The DTV demodulation transformer 20a receives a digital signal from a digital input, such as a digital signal ' from the hybrid tuner T20 or antenna T25' and produces a converted data stream as a corresponding converted signal. 20c. The DTV demodulator 20a also transmits this corresponding conversion signal to the wafer 11 via the bus bar 12. In an embodiment, hybrid tuner T20 can receive analog and digital signals. In other embodiments, ADC unit 20d can receive analog signals from a dedicated analog tuner, while DTV demodulation transformer 20a can receive digital signals from a dedicated analog tuner. 7 201037597 The film includes the processing modules 21 and 22 and the audio processing module h. The processing of the early U includes the audio decoding unit and the decoding. The video in the conversion of slice 10 >f§ is the date of the day
單元20b或SIF/PLF ADC單/田日日 接收來自ADC 碼單元鳥對接收之轉換^ C之轉換信號時，視續解 信號。解交錯單元解 產生視頻解妈 ❹ Ο 換為循序掃描模式，其中===，錯掃猫模式轉 ::=r。視頻二 === 翠視頻加強單元一低雜 所呈現之料的尺寸钱簡=麵解敬號 =使需求在外部顯示面板上顯示影像。在掃描模式轉 =視頻加強、以及尺寸或解析度調整後，處理模組21產 .=#ϋ給騎面板。音轉補組23也接收來自觀 單兀 20b 或 SIF/Pip αγϊγ ® _ _ ADC早兀2〇c之轉換信號時，並對轉 、:之曰頻資料進行解調變/解碼以產生音頻解碼信 就二ff碼信號則被傳送 哭二=姑收來自_調變單元20a*HDMI連接 換i紅號^ ’晶片11之處理模組22則處理此轉 曰頻與聲頻資料，處理模組22因此產生一處理後 210b 理後视頻信號料至解交錯單元 ==加強單元2l〇C、以及調整單元·，以調整處 值〆^科'號所呈現之影像的品質且改變此影像的特徵數 錯早元2伽將處理後視齡號的交錯掃描模式轉 201037597 號所呈==3::頻二:單元210c提高處理後視頻信 林切田:像的寸切析度，以便根據顯示面板之規 =用，在外部顯示面板上顯示影像。處理模組22 Ο Ο 信聲產Γ彳1 ί給顯7^面板。處理模組2 2也根據接收之轉換 =45·—處理後音頻錢，並將此處理後音頻信號傳送 谁=處理池23。音頻處理模組23對處理後音頻信號 : '周變/解碼以產生音頻解碼信號。音頻解補號則被 ^至外。[5擴音模組。在_些實施例中，處理模組Μ包括 EG-2 ( Moving Picture Experts Gr〇up_2 )解碼單元。 根據上述晶）W0與U之位置，接收來自輸入輸出介 之旬號的單元/輸出信號至輸入輸出介面的單元以及處 理視頻資料與音頻㈣的單元，劃分在兩個晶片1()及η 上因此，晶片10與11都具有較少數量之接腳。晶片10 11都可以成本較低的方形扁平封裝（quad flat package， QFP)方式來包裝。此外，由於處理模組21與22以及音 頻處理模組23是用來處理數位信號，晶片u可以較小的 111氣·%來製造。晶片10則以〇.18um製程來製造。 參閱第1題，晶片11更包括控制模組24。當處理模組 21或22處理接收的轉換信號時，處理模組21及22則要 求去存取至少一記憶體。在此實施例中，以記憶體M2〇為 例來說明。控制模組24判斷處理模組21與22中之何者要 求去存取記憶體M20。當控制模組24判斷出處理模組21 要求存取記憶體M20時，其切換記憶體M2〇給處理·模組 來存取。同樣地，當控制模組24判斷出處理模組22要 201037597 求存取記憶體M2〇時，其切換記憶體M2〇給處理模組22 來存取。因此，記憶體M20係由處理模組21與22所共享。 控制模組24可適當地切換記憶體M20給處理模組21與22 中要求存取記憶體M20的記憶體。在此實施例中，記憶體 M20可以DDR-SDRAM來實施。 當音頻/視頻信號處理器1應用在歐洲電視系統時，晶 片10更包括共通介面（common interface，CI)控制單元 3〇 ’如第3圖所示。DTV解調變單元20a接收來自數位輸 Ο 入端之數位信號’例如來自混合調諧器T20或天線T20之 數位k號，並產生轉換資料串流以作為對應轉換信號。Dtv 解調變單元20a透過匯流排12的第一部份接腳ρι傳送此 轉換信號至處理裝置31。處理裝置31對此轉換信號進行 解擾亂與解密’且將經過解擾亂與解密的轉換信號以並列 方式傳送至晶片10的CI控制皁元30。CI控制單元3〇再 將將經過解擾亂與解密的轉換信號以序列方式傳送至晶片 11。晶片11之處理模組22接著對來自處理裝置31之轉換 Ο 信號執行上述操作。在此實施例中，處理裝置31是個人電 腦記憶卡國際協會（Personal Computer Memory CardUnit 20b or SIF/PLF ADC Single/Ten Day Receives the conversion signal from the ADC code unit bird-to-receive conversion ^ C. Deinterlace unit solution Generate video solution mom ❹ 换 Change to sequential scan mode, where ===, wrong sweep mode to ::=r. Video 2 === Cui Video Enhancement Unit A Low Miscellaneous Dimensions of the material presented. Jane = Face Dispatch = Makes the demand display on the external display panel. After scanning mode = video enhancement, and size or resolution adjustment, the processing module 21 produces .=#ϋ for the riding panel. The tone-transfer group 23 also receives the conversion signal from the watcher 20b or SIF/Pip αγϊγ _ _ ADC early 2〇c, and demodulates/decodes the data of the turn:: to generate audio decoding. The signal is sent to the second ff code signal, and the second is transmitted from the _ modulation unit 20a* HDMI connection to the i red number ^ 'the processing module 22 of the chip 11 handles the switching frequency and audio data, the processing module 22 Therefore, after processing 210b, the video signal is processed to the deinterlacing unit==the enhancement unit 2l〇C, and the adjustment unit·, to adjust the quality of the image presented by the value and change the feature number of the image. Wrong early 2 gamma will be processed after the age of the interlaced scan mode to 201037597 ==3:: frequency two: unit 210c improve the processing of video letter forest cut: the degree of resolution, so that according to the display panel Rule = Use to display the image on the external display panel. The processing module 22 Ο 信 信 Γ彳 1 ί gives the display panel. The processing module 2 2 also processes the audio money according to the received conversion = 45·, and transmits the processed audio signal to the = processing pool 23. The audio processing module 23 pairs the processed audio signal: 'Changing/Decoding to generate an audio decoded signal. The audio complement number is taken to the outside. [5 sound reinforcement module. In some embodiments, the processing module Μ includes an EG-2 (Moving Picture Experts Gr〇up_2) decoding unit. According to the positions of the above crystals W0 and U, the unit for receiving the unit/output signal from the input and output signals to the input/output interface and the unit for processing the video material and the audio (4) are divided on the two wafers 1() and η. Therefore, both wafers 10 and 11 have a smaller number of pins. The wafers 10 11 can be packaged in a lower cost quad flat package (QFP). In addition, since the processing modules 21 and 22 and the audio processing module 23 are used to process digital signals, the wafer u can be manufactured with a small amount of 111%. The wafer 10 is fabricated in a 〇.18um process. Referring to the first problem, the wafer 11 further includes a control module 24. When the processing module 21 or 22 processes the received conversion signal, the processing modules 21 and 22 request access to at least one memory. In this embodiment, the memory M2 is taken as an example for illustration. The control module 24 determines which of the processing modules 21 and 22 is required to access the memory M20. When the control module 24 determines that the processing module 21 requests to access the memory M20, it switches the memory M2 to the processing module to access. Similarly, when the control module 24 determines that the processing module 22 requests 201037597 to access the memory M2, it switches the memory M2 to the processing module 22 for access. Therefore, the memory M20 is shared by the processing modules 21 and 22. The control module 24 can appropriately switch the memory M20 to the memory of the processing modules 21 and 22 that requires access to the memory M20. In this embodiment, the memory M20 can be implemented in DDR-SDRAM. When the audio/video signal processor 1 is applied to a European television system, the wafer 10 further includes a common interface (CI) control unit 3'' as shown in FIG. The DTV demodulation unit 20a receives the digital signal 'from the digital input terminal', e.g., the digit k number from the hybrid tuner T20 or the antenna T20, and generates a converted data stream as a corresponding conversion signal. The Dtv demodulation unit 20a transmits the conversion signal to the processing device 31 through the first partial pin p of the bus bar 12. The processing device 31 descrambles and decrypts the converted signal and transmits the descrambled and decrypted converted signals to the CI control soap unit 30 of the wafer 10 in parallel. The CI control unit 3 then transmits the descrambled and decrypted converted signals to the wafer 11 in a sequential manner. The processing module 22 of the wafer 11 then performs the above operations on the converted Ο signal from the processing device 31. In this embodiment, the processing device 31 is a Personal Computer Memory Card (Personal Computer Memory Card).
International Association，PCMCIA)電路卡。 參閱第1及2圖，晶片10包括不同的輸入輸出介面， 以接收類比與數位信號，並包括不同的單元來傳送轉換信 號至晶片11。在晶片10中的一些單元可透過匯流排12之 相同部分傳送轉換信號至晶片11。例如，ADC單元20b與 HDMI接收早元20d共旱匯流排12之相同部分以在不同的 時間傳送各自的轉換信號。因此，聯繫晶片1 〇與11之匯 201037597 流排12的尺寸不需太大。此外，匯流排12可在相同時間 下傳送來自晶片10中相異單元的轉換信號，且音頻/視頻 信號處理器1因此可應用在具有的圖中畫（picture in graphic，PIG)模式顯示器。 在一些實施例中，音頻/視頻信號處理器1可操作在快 速存取模式下。當音頻/視頻信號處理器1開始操作時，晶 片10上的單元需要預先儲存在記憶體M20内之資料來初 始化。在此時，音頻/視頻信號處理器1進入快速存取模式， 〇 以並列方式將資料由記憶體M20傳送至晶片10。 本發明雖以較佳實施例揭露如上，然其並非用以限定 本發明的範圍，任何所屬技術領域中具有通常知識者，在 不脫離本發明之精神和範圍内，當可做些許的更動與潤 飾，因此本發明之保護範圍當視後附之申請專利範圍所界 定者為準。International Association, PCMCIA) circuit card. Referring to Figures 1 and 2, wafer 10 includes different input and output interfaces for receiving analog and digital signals, and includes different units for transmitting conversion signals to wafer 11. Some of the cells in the wafer 10 can transmit a conversion signal to the wafer 11 through the same portion of the bus bar 12. For example, the ADC unit 20b and the HDMI receive the same portion of the early 20d coexistence bus 12 to transmit the respective converted signals at different times. Therefore, contact the wafer 1 〇 and 11 sink 201037597 stream 12 size does not need to be too large. Further, the bus bar 12 can transfer the converted signals from the distinct cells in the wafer 10 at the same time, and the audio/video signal processor 1 can therefore be applied to a picture in graphic (PIG) mode display. In some embodiments, the audio/video signal processor 1 is operable in a fast access mode. When the audio/video signal processor 1 starts operating, the cells on the wafer 10 need to be pre-stored with data stored in the memory M20. At this time, the audio/video signal processor 1 enters the fast access mode, and the data is transferred from the memory M20 to the wafer 10 in a side by side manner. The present invention has been disclosed in the above preferred embodiments, and is not intended to limit the scope of the present invention. Any one of ordinary skill in the art can make a few changes without departing from the spirit and scope of the invention. The scope of protection of the present invention is therefore defined by the scope of the appended claims.
11 201037597 【圖式簡單說明】 第1圖係表示根據本發明一實施例之音頻/視頻信號處 理器； 第2圖係表示第1圖之音頻/視頻信號處理器與的介面 配置示意圖；以及 第3圖係表示根據本發明二實施例之音頻/視頻信號處 理器 【主要元件符號說明】 〇 〇 1〜音頻/視頻信號處理器； 10、11〜晶片； 12〜匯流排； 20a〜DTV解調變單元；20b〜ADC單元； 20c〜SIF/PIFADC單元；20d〜HDMI接收單元； 20f〜視頻DAC單元； 20g〜音頻ADC/DAC單元 21、22〜處理模組 24〜控制模組； 31〜處理裝置； 210b〜解交錯單元 210d〜調整單元； 23〜音頻處理模組； 30〜CI控制單元； 210a〜視頻解碼單元； 210c〜視頻加強單元； M20〜記憶體； P1...P2〜匯流排之第一至第六部分接腳； T20〜混合調諧器； T21〜色差輸入端； T22〜D-Sub連接器； T23〜複合式輸入端/S輸入端子； T24〜HDMI連接器； T25〜天線； T26〜SCART-OUT 端。 1211 201037597 [Simplified description of the drawings] Fig. 1 is a diagram showing an audio/video signal processor according to an embodiment of the present invention; Fig. 2 is a diagram showing an interface configuration of an audio/video signal processor of Fig. 1; 3 is a diagram showing an audio/video signal processor according to a second embodiment of the present invention. [Main component symbol description] 〇〇1~audio/video signal processor; 10, 11~chip; 12~bus; 20a~DTV demodulation Variable unit; 20b~ADC unit; 20c~SIF/PIFADC unit; 20d~HDMI receiving unit; 20f~video DAC unit; 20g~audio ADC/DAC unit 21,22~processing module 24~control module; 31~ processing Device; 210b~Deinterleave unit 210d~Adjustment unit; 23~Audio processing module; 30~CI control unit; 210a~Video decoding unit; 210c~Video enhancement unit; M20~memory; P1...P2~bus First to sixth partial pins; T20~mixing tuner; T21~color difference input; T22~D-Sub connector; T23~composite input/S input terminal; T24~HDMI connector; T25~antenna ; T26~SC ART-OUT side. 12