TW201036102A - Process equipment and O-ring thereof - Google Patents

Process equipment and O-ring thereof Download PDF

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Publication number
TW201036102A
TW201036102A TW99108125A TW99108125A TW201036102A TW 201036102 A TW201036102 A TW 201036102A TW 99108125 A TW99108125 A TW 99108125A TW 99108125 A TW99108125 A TW 99108125A TW 201036102 A TW201036102 A TW 201036102A
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Taiwan
Prior art keywords
ring
semiconductor process
shaped ring
groove
shaped
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TW99108125A
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Chinese (zh)
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TWI503920B (en
Inventor
Yo-Yu Chang
Hsu-Shui Liu
Steve C Huang
Jiun-Rong Pai
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Taiwan Semiconductor Mfg
Mfc Sealing Technology Co Ltd
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Application filed by Taiwan Semiconductor Mfg, Mfc Sealing Technology Co Ltd filed Critical Taiwan Semiconductor Mfg
Priority to TW099108125A priority Critical patent/TWI503920B/en
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Abstract

A semiconductor process equipment for applying a process upon a wafer comprises a susceptor and an O-ring. The susceptor comprises a susceptor body, a fluid supplying unit and a supporting element. The supporting element is disposed on the susceptor body. The wafer is disposed on the supporting element. The fluid supplying unit is disposed in the susceptor body providing a fluid. A groove is formed on a side surface of the susceptor where the susceptor body is connected to the supporting element. The O-ring is disposed in the groove.

Description

201036102 六、發明說明: 【發明所屬之技術領域】 用』=有關於一種0形環,特別係有關於-種應 用於+導體製程設備的〇形環。 【先前技術】 (雷將t照第1a、巧圖,其係顯示習知之半導體製程設備 為第:Γ)1 ’用以對一晶圓2實施製程。靡係 =a圖令的A部分放大圖。半導體製程設備丨包括一 日日座10、-延伸覆蓋元件2〇以及一 於腔體30之中。晶座10包括 :3〇曰曰庄1〇: =以Γ承載元件12,該承载元件12設於該晶 产體#f 晶圓2置於該承载元件12之上,該 载元二3設於該晶座本體11之中,並經過該承 成」 提供一流體3,其中,-溝槽14形 成於該晶座10之一晶座側面15 承载元们2的連接處。 之该曰曰座本體11與該 參照第lb圖,在習知技 與該承載元件=該晶座本體u 此流體3會經過此缝隙^ 、=属乳點)存在,因 ^ 價14處戌漏(在某此情、,?,縫 隙(漏氣點)會位在溝槽14 障况縫 圖’為避免流體3,習知==:第 :之中’以密封溝槽14。然:,==, 膠4會被電録子似彳而 Ύ ld圖’由於黏 失去其密封效果。此外,由㈣,口此在長期使用之後將 由於黏膠4的有效時間不確定, H-A34090CIPTWF/丨 emon 201036102 並無法定_強或更換,因此會影響整㈣程的良率。 【發明内容】 丰導即為了欲解決習知技術之問題而提供之一種 +導體衣程設備’用以對—晶圓實施製程,包括一晶座 :及0开v%。晶座包括—晶座本體、一流體供應單元 以及承載7L件’該承載元件設於該晶座本體之上,該 晶圓置於該承載元件之上,該流體供應單元設於該晶座 〇本體之中’並對該晶圓提供一流體,其中,一溝槽形成 H曰座之-晶座侧面±之該晶座本體與該承載元件的 連接處。0形環設於該溝槽之中。 在—實鉍例中’本發明之半導體製程設備更包括一 延伸覆蓋元件,該延伸覆蓋元件環繞該承載元件並與該 晶座側面之間維持一間距。 在Μ施例中,該溝槽具有一溝槽寬度,該〇形環 具有- 0_寬度’該〇形環寬度比該溝槽寬度的比值 〇介於1.00:1.20之間,例如1〇5〜115。 在κ施例中該溝槽具有一溝槽中心直徑,該〇 形環具有:0形環中心直徑,該〇形環中心直徑比該溝 槽中心直徑的比值介於〇 95〜1〇〇之間,例如〇·97〜 0.99。 在一貫施例中’ 1亥0形環的截面呈矩形。 在另-貫施例中’該〇形環具有一第一導角部以及 ―第二導角部’第—導角部形成於該0形環之-第-内 緣’第一‘角部形成於該〇形環之—第二内緣。該第一 0503-A34090CIPTWF/lemon 201036102 導角部位於—〇形環頂面,㈣形環頂面的徑向寬度比 該0形環之徑向寬度的比值介於G.7G〜0.90之間,例如 0.75〜0.88。該第二導角部位於一 〇形環底面,該〇形 環底面的徑向寬度比該〇形環之徑向寬度的比值介於 0.70〜0.90之間,例如〇75〜〇.88。 在一貫施例中,該〇形環的材質為橡膠,該承载元 件的材料為陶兗。 在一實施例中,該溝槽具有一溝槽底面以及一溝槽 側壁,其中,該溝槽底面的寬度大於該溝槽側壁的徑向 寬度。 在一實施例中,該流體經過該晶座本體以及該承载 元件之間的缝隙進入該溝槽,並由於該〇形環所密封。 本發明亦有關於一種〇形環,包括一 0形環本體以 及一第一導角部。該0形環本體的截面呈矩形、第一導 角部形成於該0形環本體之一第一内緣。 應用本發明之半導體製程設備(電漿蝕刻設備),由於 使用0形環密封溝槽,因此可防止流體洩漏。此外,由 於用0形環的品質較為一致,因此可準確的依據使用壽 命而定期更換。特別是,由於本發明實施例中採用截面 呈矩形的0形環’因此可適用於溝槽底面的寬度大於該 溝槽側壁的徑向寬度的情況,從而提供良好的密封效果。 此外,應用另一實施例之〇形環,由於〇形環具有 第一導角部以及第二導角部,因此可更順利的置入溝槽 之中而提供密封的效果。 在一實施例中,0形環具有一徑向寬度以及一垂直 0503-A34090CIPTWF/lem〇n 6 201036102 向厚度,其中,該徑向寬度與該垂直向厚度的比值介於 1 : 0.8〜1 : 4之間。 在另一實施例中,該〇形環具有一 〇形環本體以及 -肋,該0形環本體具有一内側面以及一外侧面,該内 側面接觸該溝槽之底部’該外側面與該内侧面相反,該 肋形成於該外側面之上。 【實施方式】 Ο 〇 參照第2a、2b圖,其係顯示本發明第一實施例之半 導體製程設備(㈣關設備)_,用輯—㈣2實施 製程。第2b圖係為第2affl中的A1部分放大圖。半導體 製程設備1〇0包括一晶座10、-延伸覆蓋元件20、一 Ο 形環(〇形,)110以及一腔體3〇。晶座1〇設於腔體 10包括一晶座本體u、-流體供應單元 曰Π元件12,該承載元件12設於該晶座本體 曰2置於該承載元件12之上,該流體供應 對二:提;座/體11之中’並經過該承載元件12 溝槽14形成於該晶座10之 ^本體11與該料 :處。該延伸覆盘元件20環繞該承 ::面15之間維持-間…形環η。設於該溝槽: 产^溝槽具有1槽寬度d1,該0形 裱110具有一 0形環寬度d2, 槽寬度cn的比值介於⑽〜…0形^度比該溝 •之間’例如1.05〜1.15。 0503-A34090CIPTWF/lemon 7 201036102 該溝,14具有一溝槽中心直徑該0形環n〇具有- 冗中’u直⑸2,該0形環中心直徑A比該溝槽中心直 徑|的比值^於0.95〜1.00之間,例如0.97〜0.99。 、在此實施例中’該〇形環11〇的截面呈矩形, 質為橡膠#此並未限制本發明,該〇形環11G的形狀 亦可隨該溝槽的形狀而對應修改。 在 只靶例中,該承載元件12的材料為陶瓷。該溝 槽Η具有-溝槽底面141以及—溝槽側壁⑷,i中, 該溝槽底面141㈣度Wb大於該溝槽側壁142的徑向 度Wr該机體3經過該晶座本體η以及該承载元件】之 之間的缝隙進入該溝槽14,並由於該〇形環ιι〇所密封。 應用本發明之半導體製程設備(電漿姓刻設傷),由於 使用Ο形壤密封溝槽,因此可防止流體沒漏。此外,由 :用形環的品質較為一致,因此可準確的依據使用壽 :而疋期更換。特別是,由於本發明實施例中採用截面 =形的0形環’因此可適用於溝槽底面的寬度大於該 溝槽側壁的徑向寬度的情況,從而提供良好的密封效果。 第3Α圖係顯示本發明第二實施例之〇形環㈣,在 本發明第二實施射,半導體製程設備其他元件的結構 同第一實施例。參照第3圖,〇形環12〇具有—第一導 :部121以及一第二導角部122。第一導角部ΐ2ι形成於 ^形環12〇之-第1緣。第二導角部122形成於該 〇形環no之一第二内緣。該第_導角部ΐ2ι位於一 〇 形!頂面i23,該0形環頂Φ i23白勺經向寬度w。t比該〇 形% 120之徑向寬度W。的比值介於〇 7〇〜〇 9〇之間,例 0503-A34090CTPTWF/lemon 8 201036102 ,ο·75〜〇,該第二導角部i22位於—〇形環底面 24’該0形%底面124的徑向寬度比該 -201036102 VI. Description of the invention: [Technical field to which the invention pertains] The use of 』= relates to a type 0 ring, in particular to a 〇-shaped ring applied to a +conductor process equipment. [Prior Art] (Ray will be according to the first 1a, the figure, which shows the conventional semiconductor process equipment as the first: Γ) 1 ' is used to implement a process for a wafer 2.靡 is a magnified view of part A of the aa plan. The semiconductor process equipment includes a day and day seat 10, an extended cover member 2A, and a cavity 30. The crystal holder 10 includes: 3 〇曰曰 1 〇: = Γ carrying member 12, the carrying member 12 is disposed on the crystal body #f wafer 2 is placed on the carrying member 12, the carrier 2 A fluid 3 is provided in the base body 11 and through the carrier, wherein the groove 14 is formed at the junction of the carrier side 2 of the crystal seat 10 on the side of the carrier. The squat body 11 and the reference lb diagram, in the conventional art and the carrier element = the pedestal body u, the fluid 3 will pass through the gap ^, = is a milk point), because the price is 14 Leakage (in some case,,?, the gap (leakage point) will be in the groove 14 barrier pattern 'to avoid fluid 3, conventional ==: the first: 'to seal the groove 14. , ==, Glue 4 will be stunned by the electro-recording Ύ ld figure 'Because the viscosity loses its sealing effect. In addition, by (4), the mouth will be uncertain after the long-term use due to the effective time of the adhesive 4, H-A34090CIPTWF /丨emon 201036102 There is no statutory _ strong or replacement, so it will affect the yield of the whole (four) process. [Summary of the Invention] The Fusion Guide is a kind of +conductor garment equipment provided for solving the problems of the prior art. The wafer implementation process includes a crystal holder: and 0% open. The crystal holder includes a crystal holder body, a fluid supply unit, and a 7L member. The carrier member is disposed on the crystal holder body. Above the carrier element, the fluid supply unit is disposed in the base of the base pad and provides a first-class wafer a body, wherein a groove forms a junction of the holder body of the H-seat-side of the crystal holder and the carrier member. The 0-ring is disposed in the groove. In the actual example, the invention The semiconductor process device further includes an extended cover member surrounding the load bearing member and maintaining a spacing from the side of the crystal holder. In an embodiment, the trench has a groove width, the bezel ring Having a =0 width 〇 the ratio of the width of the 〇 ring to the width of the groove 〇 is between 1.00:1.20, for example 1〇5~115. In the κ embodiment, the groove has a groove center diameter, The 〇-shaped ring has a center diameter of the 0-shaped ring, and the ratio of the center diameter of the 〇 ring to the center diameter of the groove is between 〇95 and 1 ,, for example, 〇·97~ 0.99. In the consistent example, '1 The cross section of the O-ring is rectangular. In another embodiment, the 〇-shaped ring has a first guiding portion and a second guiding portion. The leading-angle portion is formed in the O-ring. The inner edge 'first' corner is formed on the second inner edge of the ring-shaped ring. The first 0503-A34090CIPTWF/lemon 201036102 The portion is located at the top surface of the ring-shaped ring, and the ratio of the radial width of the top surface of the (four) ring to the radial width of the ring is between G.7G and 0.90, for example, 0.75 to 0.88. Located on the bottom surface of a ring-shaped ring, the ratio of the radial width of the bottom surface of the ring-shaped ring to the radial width of the ring-shaped ring is between 0.70 and 0.90, for example, 〇75~〇.88. In a consistent embodiment, The material of the ring is made of rubber, and the material of the bearing member is ceramic. In an embodiment, the groove has a groove bottom surface and a groove sidewall, wherein the groove bottom surface has a width larger than the groove sidewall Radial width. In one embodiment, the fluid enters the groove through the gap between the base body and the carrier member and is sealed by the beak ring. The invention also relates to a 〇-shaped ring comprising an O-ring body and a first lead. The O-ring body has a rectangular cross section, and the first lead portion is formed on one of the first inner edges of the O-ring body. With the semiconductor process equipment (plasma etching apparatus) of the present invention, since the groove is sealed by the O-ring, fluid leakage can be prevented. In addition, since the quality of the O-ring is relatively uniform, it can be accurately replaced depending on the service life. In particular, since the O-ring having a rectangular cross section is employed in the embodiment of the present invention, it is applicable to the case where the width of the bottom surface of the groove is larger than the radial width of the side wall of the groove, thereby providing a good sealing effect. Further, by applying the beak ring of another embodiment, since the beak ring has the first corner portion and the second corner portion, it can be smoothly placed into the groove to provide a sealing effect. In one embodiment, the O-ring has a radial width and a vertical 0503-A34090 CIPTWF/lem〇n 6 201036102 direction thickness, wherein the ratio of the radial width to the vertical thickness is between 1: 0.8 and 1: Between 4. In another embodiment, the stirrup ring has a ring body and a rib, the 0 ring body has an inner side and an outer side, the inner side contacting the bottom of the groove 'the outer side and the The rib is formed on the outer side opposite the inner side. [Embodiment] Ο 〇 Referring to Figures 2a and 2b, the semiconductor device ((4) device) of the first embodiment of the present invention is shown, and the process is implemented by the series-(4). Fig. 2b is an enlarged view of the A1 portion in the second aff1. The semiconductor process device 100 includes a crystal holder 10, an extended cover member 20, a meandering ring (110), and a cavity 3''. The crystal holder 1 is disposed on the cavity 10 and includes a crystal holder body u, a fluid supply unit 曰Π element 12, and the carrier element 12 is disposed on the pedestal body 曰2 disposed on the carrier element 12, the fluid supply pair 2: Lifting; in the seat/body 11' and passing through the carrier member 12, a groove 14 is formed in the body 11 of the crystal holder 10 and the material: The extended disk member 20 surrounds the carrier-like surface 15 to maintain a --shaped ring η. The groove is provided: the groove has a groove width d1, and the 0-shaped groove 110 has a 0-shaped ring width d2, and the ratio of the groove width cn is between (10) and 0. For example, 1.05~1.15. 0503-A34090CIPTWF/lemon 7 201036102 The groove, 14 has a groove center diameter. The 0-ring n〇 has a redundancy - 'u straight (5) 2, and the ratio of the center diameter A of the O-ring to the center diameter of the groove is Between 0.95 and 1.00, for example, 0.97 to 0.99. In this embodiment, the cross-section of the 〇-shaped ring 11〇 is rectangular and the quality is rubber. This does not limit the present invention, and the shape of the 〇-shaped ring 11G may be modified correspondingly according to the shape of the groove. In the target only example, the material of the carrier member 12 is ceramic. The trench Η has a trench bottom surface 141 and a trench sidewall (4), wherein the trench bottom surface 141 (four) degree Wb is greater than the radial extent Wr of the trench sidewall 142, the body 3 passes through the crystal holder body η and the The gap between the load bearing members enters the groove 14 and is sealed by the meandering ring. By using the semiconductor process equipment of the present invention (the plasma is wounded), since the crucible is used to seal the groove, the fluid can be prevented from leaking. In addition, the quality of the ring is relatively uniform, so it can be accurately based on the life: and replaced in the flood season. In particular, since the 0-ring of the cross-section shape is employed in the embodiment of the present invention, it is applicable to the case where the width of the bottom surface of the groove is larger than the radial width of the side wall of the groove, thereby providing a good sealing effect. Fig. 3 is a view showing a ring-shaped ring (four) of a second embodiment of the present invention. In the second embodiment of the present invention, the structure of other elements of the semiconductor process apparatus is the same as that of the first embodiment. Referring to Fig. 3, the ring 12 has a first guide portion 121 and a second guide portion 122. The first corner portion ΐ2ι is formed on the first edge of the ^-ring 12〇. The second lead portion 122 is formed at one of the second inner edges of the ring-shaped ring no. The first _ guide angle ΐ2ι is located in a ! shape! The top surface i23, the warp width w of the 0-shaped ring top Φ i23. t is greater than the radial width W of the chevron % 120. The ratio is between 〇7〇~〇9〇, for example, 0503-A34090CTPTWF/lemon 8 201036102, ο·75~〇, the second guiding portion i22 is located at the bottom surface 24' of the 〇-shaped ring. Radial width is better than this -

之=寬度w。的比值介於J 應用本發明第二實施例之◦形環,由於◦形環且有 第,部以及第二導角部,因此可更順利的置入溝槽 之中而提供密封的效果。 〇= width w. The ratio of J is the same as that of the second embodiment of the present invention. Since the beak ring has the first portion and the second corner portion, it can be smoothly placed into the groove to provide a sealing effect. 〇

第3Β圖係顯示本發明第三實施例之〇形環咖, 在本發明第三實施例中,半導體製程設備其他元件的結 構大致上同第—實施例。參照第3Β®,〇形環12〇,具有 V角4 121。導角部121 ’形成於該0形環120,之一内 緣。該導角部121,位於一 0形環底面124,然,亦可以 位於- Q形環頂面123。〇形環⑽,具有—徑向寬度% 、及垂直向厚度T。。在第三實施例中,該徑向寬度w。 /、該垂直向厚度TQ的比值,搭配溝槽尺寸,介於〗:0.8 4之間知'別是,第三實施例可適用於該徑向寬度 W。與該垂直向厚度丁。的比值介於1 : 2〜1 : 4之間的情 況。在此實施例中,僅需要單一個導角部121,,便可順 利完成組裝。 第3C圖係顯示本發明第四實施例之〇形環12〇,,, 在本發明第四實施例中,半導體製程設備其他元件的結 構大致上同第一實施例。參照第3C圖,〇形環12〇”具 有具有一 Ο形環本體128以及一肋125,該〇形環本體 128具有一内側面120以及一外側面127,該内側面126 接觸該溝槽之底部,該外側面127與該内側面126相反, 0503-A34090CIPTWF/lem〇n 9 201036102 該肋125形成於該外側面127之上。其中,該〇形環本 體128具有一本體徑向厚度w。(同前述之徑向厚度),該 肋具有-肋徑向厚度Wrib,該本體徑向厚度w。與該肋徑 向厚度^b的比值介於3:1〜12:1之間。在本發明第四實 轭例中,猎由肋125的設置,可加強〇形環12〇”的巧向 強度’防止Ο形環120”朝徑向發生撓曲。此外,在^ 施例中,透過適當設計該本體徑向厚度w。與該肋捏向^ 度Wrib的比值,可以同時提供充足的防挽曲以及密 :生並且’肋可幫助辨識外側面’避免組裝錯誤的情況 雖然本發明已以具體之較佳實施例揭露如上, 並非用以㈣本發明,任何熟習此項技藝者 = 本發明之精神和範圍内,仍可作虺 〇503-A3409〇aPTWF/Iem〇n 201036102 【圖式簡單說明】 第la圖係顯示習知之半導體製程設備; 第lb圖係為第la圖中的a部分放大圖; ^第1C圖係顯示習知技術之將黏膠填入溝槽之中的情 第Id圖係顯示黏膠被電漿粒子蝕刻而損耗的情形. 第2a圖係顯示本發明第一實施例之半導 二, 備; 展程設 Ο 第2b圖係為第2a圖中的A1部分放大圖; 第2c圖係顯示第一實施例中〇形環與半導體 備分離的情形; 〃 裏程設 第3A圖係顯示本發明第二實施例之〇形環. 第3B圖係顯示本發明第三實施例之〇形環;' 第3C圖係顯示本發明第四實施例之〇形環 '及 【主要元件符號說明】 〇 1、100〜半導體製程設備; 2〜 晶圓; 3〜流體; 黏膠; 10〜 晶座; 1卜 -晶座本體; 12〜 承載元件; 13- -流體供應單元; 14〜 溝槽; 141 〜溝槽底面; 142- 〜溝槽側璧; 15- i晶座側面; 110 、120、120,、120,、 - 0形環 s 121 〜第一導角部; 121, 〜導角部; 0503-A34090CIPTWF/!emon 11 201036102 122- “第二導角部; 123〜 0形環頂面; 124- -0形環底面; 125〜 肋; 126- -内側面; 127〜 外侧面; 128- -0形環本體。 0503-A34090CIPTWF/]emonFig. 3 is a view showing a dome-shaped ring coffee according to a third embodiment of the present invention. In the third embodiment of the present invention, the structure of other elements of the semiconductor process apparatus is substantially the same as that of the first embodiment. Referring to the third Β®, the 〇 ring 12〇 has a V angle of 4 121. The lead portion 121' is formed on one of the inner edges of the O-ring 120. The lead portion 121 is located on the bottom surface 124 of the 0-shaped ring. Alternatively, it may be located on the top surface 123 of the -Q ring. The 〇-shaped ring (10) has a radial width % and a vertical thickness T. . In the third embodiment, the radial width w. /, the ratio of the vertical thickness TQ, in conjunction with the groove size, between: 0.84, the third embodiment is applicable to the radial width W. With the vertical thickness of the diced. The ratio is between 1: 2~1: 4. In this embodiment, only a single lead portion 121 is required, and assembly can be smoothly performed. Fig. 3C is a view showing a ring-shaped ring 12 of the fourth embodiment of the present invention, and in the fourth embodiment of the present invention, the structure of other elements of the semiconductor process apparatus is substantially the same as that of the first embodiment. Referring to FIG. 3C, the ring-shaped ring 12'' has a ring-shaped ring body 128 and a rib 125. The ring-shaped ring body 128 has an inner side surface 120 and an outer side surface 127, and the inner side surface 126 contacts the groove. The bottom surface 127 is opposite to the inner side surface 126, 0503-A34090CIPTWF/lem〇n 9 201036102. The rib 125 is formed on the outer side surface 127. The bellows body 128 has a body radial thickness w. (same radial thickness as described above), the rib has a rib radial thickness Wrib, the body radial thickness w. The ratio of the rib radial thickness ^b is between 3:1 and 12:1. In the fourth embodiment of the invention, the arrangement of the ribs 125 enhances the sharpness of the 〇-shaped ring 12"" to prevent the Ο ring 120" from flexing in the radial direction. Further, in the embodiment, The radial thickness w of the body is appropriately designed. The ratio of the rib to the Wrib can provide sufficient anti-draping and denseness and the rib can help identify the outer side to avoid assembly errors. Although the present invention has been The above is disclosed in the preferred embodiment, and is not used in (4) the present invention, any cooked The skilled person = still within the spirit and scope of the present invention, can still be used as 虺〇503-A3409〇aPTWF/Iem〇n 201036102 [Simple description of the drawing] The first drawing shows the conventional semiconductor process equipment; An enlarged view of part a of the first drawing; ^1C shows the case where the adhesive is filled into the groove by the prior art, and the Id figure shows that the adhesive is etched by the plasma particles and is lost. 2a The figure shows the semi-conductor of the first embodiment of the present invention; the setting of the second step is the enlarged view of the part A1 in the second drawing; the second drawing shows the ring-shaped ring and the semiconductor in the first embodiment. In the case of separation; 〃 mile setting 3A shows a 〇 ring of the second embodiment of the present invention. Fig. 3B shows a 〇 ring of the third embodiment of the present invention; '3C shows the invention Four embodiments of the ring-shaped ring 'and the main component symbol description 〇 1, 100 ~ semiconductor process equipment; 2 ~ wafer; 3 ~ fluid; adhesive; 10 ~ crystal seat; 1 Bu-crystal seat body; Bearing element; 13- - fluid supply unit; 14~ groove; 141 ~ groove bottom; 142- ~ Groove side 璧; 15- i crystal seat side; 110, 120, 120, 120,, - 0 ring s 121 ~ first lead angle; 121, ~ lead angle; 0503-A34090CIPTWF/!emon 11 201036102 122- "Second guide portion; 123~0-ring top surface; 124--0-ring bottom surface; 125~ rib; 126--inner side; 127~ outer side; 128--0 ring body. 0503-A34090CIPTWF/]emon

Claims (1)

201036102 七、申請專利範圍· 1. 一種半導體製程設備’用以承载晶圓,包括: 一晶座本體、一流體供應單元以及一承載元件,該 承载元件設於該晶座本體之上並包含一用來承栽晶圓的 上表面以及一側面,該流體供應單元設於該晶座本體之 中用以對該承載元件上表面的晶圓提供一流體,一溝槽 形成該承載元件的侧面;以及 9 一 〇形環,設於該溝槽之中。 Ο ❹ 2.如申請專利範圍第1項所述之半導體製程設備, 其^包括-延伸覆蓋元件’該延伸覆蓋元件環繞該 疋件並與該晶座側面之間維持一間距。 上如甲請專利範圍第 -------Tf肢展径設備, 二中’該溝槽具有-溝槽寬度,該◦形環具有_ 0形产 見度該Q科、寬度比該溝槽寬度的比值介於 之間。 .u 1钱述之半導體製程設備, 形環中具t一溝槽中心直徑’該0形環具有-0 二中心直徑比該溝槽中心直徑的 其二==:所述之半導體製_, ”6’::請專利範圍第5項所述之半導體製程設備, 二第:緣環具有—第—導角部,形成於㈣形環之 如申涛專利範圍第6項所述之半導體製程設備, 0503-A34090ClPTWF/lem〇n 201036102 其中,該〇形環具有-第二導角部,形成於該〇形環之 一第二内緣。 义 8. 如申请專利_第7項所述之半導體製程設 其中’該第二導角部位於—〇形環底面,該〇形環底面 的徑向寬度比該〇形環之徑向寬度的比值介於〇7〇 0.90之間。 · 9. 如申請專利範圍第6項所述之半導體製程設備, 其中’該第一導角部位於一 〇形環頂面’該〇形環頂面 的徑向寬度比該〇形環之徑向寬度的比值介於〇7〇〜 0.90之間。 ’ 10·如ΐ請專利範圍第1項所述之半導體製程設 備,其中,該0形環的材質為橡膠。 11·如申請專利範圍第!項所述之半導體製程設 備,其中,該承載元件的材料為陶瓷。 12. 如中請專利範圍第!項所述之半導體製程設 備,其中’該溝槽具有一溝槽底面以及一溝槽側壁,其 中π亥溝槽底面的寬度大於該溝槽側壁的徑向寬度。 13. 如申請專利範圍第〗項所述之半導體製程設 備’其中’由該流體供應單元提供之該流體由該0形環 所密封。 14. 一種〇形環,包括: 二〇形環本體,該◦形環本體的截面呈矩形;以及 一第—導角部,形成於該〇形環本體之一第一内緣。 15. 如申請專利範圍第14項所述之〇形環,並中, 該0形環本體具有—第二導角部,形成於該〇形環本體 0503-A34090CIPTWF/lem〇n l/t 201036102 之 第二内緣 ^ 16.如申請專利範圍第15項所述之〇形環,甘士 f第二導角部位於一 0形環底面,該Q形環底面的W 寬度比該0形環之徑向寬度的比值介於G.7G〜〇9〇 :門° 1 7 L山山 之間。 今笛一請專利範圍第14項所述之0形環,其中, ;:二部位於一 〇形環頂面,該〇形環頂面的徑向 見又匕該Ο形環之徑向寬度的比值介於〇·7〇〜〇.列之間。201036102 VII. Patent Application Range 1. A semiconductor processing device 'for carrying a wafer, comprising: a crystal holder body, a fluid supply unit and a carrier member, the carrier member is disposed on the crystal holder body and includes a The fluid supply unit is disposed in the base body for providing a fluid to the wafer on the upper surface of the carrier member, and a groove is formed on a side surface of the carrier member; And a 9-ring ring is disposed in the groove.半导体 ❹ 2. The semiconductor process apparatus of claim 1, wherein the extended cover element surrounds the element and maintains a spacing from the side of the base. In the case of the first patent, please refer to the -------Tf limb-tracking device, the second of the 'the groove has a groove width, the ◦-shaped ring has _ 0 shape visibility, the Q section, the width ratio The ratio of the width of the groove is between. .u 1 described in the semiconductor process equipment, the ring has a t-trench center diameter 'the 0-ring has -2 two center diameter than the groove center diameter of the second ==: the semiconductor system _, "6':: Please refer to the semiconductor process equipment described in item 5 of the patent scope, the second: the edge ring has a - lead-angle portion, formed in the (four)-shaped ring, such as the semiconductor process described in the sixth paragraph of Shen Tao patent scope Apparatus, 0503-A34090ClPTWF/lem〇n 201036102 wherein the 〇-shaped ring has a second leading edge portion formed on one of the second inner edges of the 〇-shaped ring. Sense 8. As described in claim 7 The semiconductor process is characterized in that the second lead-angle portion is located on the bottom surface of the 〇-shaped ring, and the ratio of the radial width of the bottom surface of the 〇-shaped ring to the radial width of the 〇-shaped ring is between 〇7〇0.90. The semiconductor process apparatus of claim 6, wherein the first lead angle portion is located on a top surface of the dome ring, and a radial width of the top surface of the ring is larger than a radial width of the ring The ratio is between 〇7〇~0.90. '10·If you request the semiconductor described in the first paragraph of the patent scope The device of the present invention, wherein the material of the 0-ring is made of rubber. 11. The semiconductor process device of claim 2, wherein the material of the carrier member is ceramic. The semiconductor processing apparatus, wherein the trench has a trench bottom surface and a trench sidewall, wherein a width of the bottom surface of the trench is greater than a radial width of the sidewall of the trench. The semiconductor process device 'where the fluid supplied by the fluid supply unit is sealed by the O-ring. 14. A 〇-shaped ring comprising: a 〇 ring body having a rectangular cross section And a first lead-shaped portion formed on the first inner edge of the body of the stirrup ring. 15. The ring-shaped ring according to claim 14 of the patent application, wherein the 0-shaped ring body has - a second guiding portion formed on the second inner edge of the ring-shaped ring body 0503-A34090CIPTWF/lem〇nl/t 201036102. 16. The 〇-shaped ring as described in claim 15 of the patent application, the second guide of the cane f The corner is located on the underside of an O-ring. The ratio of the W width of the bottom surface of the Q-shaped ring to the radial width of the 0-shaped ring is between G.7G and 〇9〇: the gate is between 1 and 7 L. The present whistle is as described in item 14 of the patent scope. 0-shaped ring, wherein, ;: the two parts are located on the top surface of a ring-shaped ring, the radial direction of the top surface of the ring-shaped ring and the ratio of the radial width of the ring-shaped ring are between 〇·7〇~〇. between. 18.如申請專利範圍第14項所述之〇形 豆曰斯 為橡膠。 〃柯貝 19. 一種半導體製程設備,用以承載晶圓,包括: 一晶座本體、一流體供應單元以及一承載元件,該 承載元件設於該晶座本體之上並包含—时承載晶圓的〆 上表面以及一側面,該流體供應單元設於該晶座本體之 中用以對該承載元件上表面的晶圓提供一流體,一溝槽 形成該承載元件的側面;以及 一 〇形環,設於該溝槽之中,其中,該〇形環具有 一徑向寬度以及一垂直向厚度,其中,該徑向寬度與該 垂直向厚度的比值介於1 : 0.8〜1 : 4之間。 20.如申請專利範圍第19項所述之半導體製程設 備’其中,該徑向寬度與該垂直向厚度的比值介於1 : 2 〜1 : 4之間。 21. 如申請專利範圍第19項所述之半導體製程設 備,其中,該〇形環的截面呈矩形。 22. 如申請專利範圍第21項所述之半導體製程設 備’其中,該Ο形環具有一導角部,形成於該〇形環之 0503-A34090CIPTWF/Iemon 15 201036102 一内緣。 備 備 備 備 23. 如申請專利範圍第 ^ η 国第22項所述之半導體製程設 其中’該0形%僅具有單一之該導角部。 24. 如申請專利範圍筮 & 苐U項所述之半導體製程設 二如申,利範圍第22項所述之半導體製程設 2甘6.如中請專鄉圍第19項所述之半導體製程設 :、更包括-延伸覆蓋元件’該延伸覆蓋㈣環繞該 -----成祀^甲復 承載元件並與該晶座側面之間維持一間距 如申請專利範圍第19項所述之半導體製程設 備,其中,該Ο形環的材質為橡膠。 28.如申請專利範圍第19項所述之半導體製程設 備’其中’該承載元件的材料為陶竟。 29.如申請專利範圍第19項所述之半導體製程設 備,其中,由該流體供應單元提供之該流體由該〇形環 所密封。 ^ 30. —種半導體製程設備,用以承載晶圓,包括: 一晶座本體、一流體供應單元以及一承載元件,該 承載元件設於該晶座本體之上並包含一用來承載晶圓的 上表面以及一側面,該流體供應單元設於該晶座本體之 中用以對該承載元件上表面的晶圓提供一流體,一溝槽 形成該承載元件的側面;以及 一 〇形環,設於該溝槽之中’其中,該〇形環具有 一 〇形環本體以及一肋’該〇形環本體具有一内侧面以 〇503-A34090CIPTWF/lemon 201036102 及外侧φ該内側面接觸該溝槽之底部,該外側面與 該内侧面相反,該肋形成於該外側面之上。 /、 31.如申凊專利範圍第3〇項所述之半導體製程設 備,其中,該Ο形環具有一導角部,形成於該〇形環之 一内緣。 32·如中請專利範圍第31項所述之半導體製程設 備,其中,該Ο形環僅具有單一之該導角部。 33. 如申請專利範圍第31項所述之半導體製程設 ❸備,其中,該導角部位於一 〇形環底面。 34. 如中請專利範圍帛31項所述之半導體製程設 備,其中,該導角部位於一 〇形環頂面。 35. 如申請專利範圍第3〇項所述之半導體製程設 備,其更包括-延伸覆蓋元件’該延伸覆蓋元件環繞該 承載元件並與該晶座側面之間維持一間距。 36. 如申請專利範圍第3〇項所述之半導體製程設 備,其中,該Ο形環的材質為橡膠。 〇 37·如申請專利範圍第3〇項所述之半導體製程設 備,其中,該承載元件的材料為陶瓷。 38. 如申請專利範圍第3〇項所述之半導體製程設 備’其中,由誠體供應單元提供之該㈣由該〇形環 所密封。 39. 如申請專利範圍第3〇項所述之半導體製程設 備,其中,該〇形環本體具有一本體徑向厚度,节肋且 有一肋徑向厚度,該本體徑向厚度與該肋徑向厚产2 值介於3:1〜12:1之間。 又 〇503-A34090CIPTWF/lemon 201036102 40· 一種〇形環,包括: 一 0形環本體,該〇形環本體的截面呈矩形,具有 一内側面以及一外侧面;以及一肋,該肋形成於該外側 面之上。 /· 明y砣圍第40項所述之〇形環,其中, 該〇形環本體具有—本體 、 厚度,該本體徑向厚度m度,該肋具有一肋徑向 3:1〜12:1之間。 ” ~月^向厚度的比值介於 0503-A34090CIPTWF/lemon 1818. The filed soybean meal as described in claim 14 is rubber. 〃科贝19. A semiconductor process device for carrying a wafer, comprising: a crystal holder body, a fluid supply unit, and a carrier member disposed on the wafer holder body and containing a time-bearing wafer The upper surface of the crucible and a side surface, the fluid supply unit is disposed in the base body for providing a fluid to the wafer on the upper surface of the carrier member, a groove forming a side surface of the carrier member; and a ring-shaped ring Provided in the groove, wherein the ring has a radial width and a vertical thickness, wherein the ratio of the radial width to the vertical thickness is between 1: 0.8 and 1:4 . 20. The semiconductor process device of claim 19, wherein the ratio of the radial width to the vertical thickness is between 1:2 and 1:4. 21. The semiconductor process apparatus of claim 19, wherein the 〇-shaped ring has a rectangular cross section. 22. The semiconductor process device of claim 21, wherein the Ο-shaped ring has a lead-in portion formed at an inner edge of 0503-A34090CIPTWF/Iemon 15 201036102 of the 〇-shaped ring. Preparations 23. The semiconductor process described in Item 22 of the Patent Application No. 22, wherein the 0-shaped % has only a single such guide. 24. If the scope of the patent application 筮 & 苐 U is set in the semiconductor process, such as Shen, the semiconductor process described in item 22 of the profit range is set to 2. 6. Please refer to the semiconductor described in item 19 of the township. The process design includes: an extension cover member'. The extension cover (4) surrounds the assembly element and maintains a spacing between the side surface of the crystal holder and the 19th aspect of the patent application scope. A semiconductor process equipment, wherein the Ο-shaped ring is made of rubber. 28. The semiconductor process device of claim 19, wherein the material of the carrier member is ceramic. The semiconductor process apparatus of claim 19, wherein the fluid supplied by the fluid supply unit is sealed by the stirrup ring. ^30. A semiconductor processing device for carrying a wafer, comprising: a crystal holder body, a fluid supply unit, and a carrier member disposed on the crystal holder body and including a carrier for carrying the wafer The upper surface and a side surface, the fluid supply unit is disposed in the base body for providing a fluid to the wafer on the upper surface of the carrier member, a groove forming a side surface of the carrier member, and a 〇 ring, Provided in the groove, wherein the ring has a ring body and a rib. The ring body has an inner side surface 〇503-A34090CIPTWF/lemon 201036102 and an outer side φ the inner side contacts the groove The bottom of the groove is opposite to the inner side, and the rib is formed on the outer side. The semiconductor process device of claim 3, wherein the cymbal ring has a lead-in portion formed on an inner edge of the cymbal ring. 32. The semiconductor process device of claim 31, wherein the Ο-shaped ring has only a single one of the lead portions. 33. The semiconductor process tool of claim 31, wherein the lead portion is located on a bottom surface of a stirrup ring. 34. The semiconductor process device of claim 31, wherein the lead portion is located on a top surface of a ring. 35. The semiconductor process device of claim 3, further comprising an extended cover element that surrounds the load bearing element and maintains a spacing from the side of the base. The semiconductor process device of claim 3, wherein the Ο ring is made of rubber. The semiconductor process device of claim 3, wherein the material of the carrier member is ceramic. 38. The semiconductor process apparatus of claim 3, wherein the (four) provided by the honesty supply unit is sealed by the dome. 39. The semiconductor process apparatus of claim 3, wherein the ring body has a body radial thickness, a rib and a rib radial thickness, the body radial thickness and the rib radial The yield 2 value is between 3:1 and 12:1. 〇503-A34090CIPTWF/lemon 201036102 40. A 〇-shaped ring, comprising: an O-ring body having a rectangular cross section having an inner side surface and an outer side surface; and a rib formed on the rib Above the outer side. The 〇-shaped ring according to Item 40, wherein the 〇-shaped ring body has a body, a thickness, the body has a radial thickness of m degrees, and the rib has a rib radial direction of 3:1 to 12: Between 1. The ratio of ~ month to thickness is between 0503-A34090CIPTWF/lemon 18
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TWI467174B (en) * 2012-10-19 2015-01-01 Mfc Sealing Technology Co Ltd Method for inspecting seals
CN105895570A (en) * 2015-02-16 2016-08-24 麦丰密封科技股份有限公司 Improved seal for electrostatic chuck sidewall
TWI668057B (en) * 2017-09-18 2019-08-11 台灣積體電路製造股份有限公司 Semiconductor wafer cleaning apparatus

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US5636098A (en) * 1994-01-06 1997-06-03 Applied Materials, Inc. Barrier seal for electrostatic chuck
CN2197378Y (en) * 1994-06-14 1995-05-17 马建军 Multifunctional expanding rubber ring
JP4942471B2 (en) * 2005-12-22 2012-05-30 京セラ株式会社 Susceptor and wafer processing method using the same
CN201101429Y (en) * 2007-11-17 2008-08-20 广东新宝电器股份有限公司 Electric heating kettle seal ring

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Publication number Priority date Publication date Assignee Title
TWI467174B (en) * 2012-10-19 2015-01-01 Mfc Sealing Technology Co Ltd Method for inspecting seals
CN105895570A (en) * 2015-02-16 2016-08-24 麦丰密封科技股份有限公司 Improved seal for electrostatic chuck sidewall
TWI613753B (en) * 2015-02-16 2018-02-01 Improved seal for electrostatically adsorbing the side wall of the retainer
CN105895570B (en) * 2015-02-16 2018-11-02 麦丰密封科技股份有限公司 Improved seal for electrostatic chuck sidewall
TWI668057B (en) * 2017-09-18 2019-08-11 台灣積體電路製造股份有限公司 Semiconductor wafer cleaning apparatus
US10991570B2 (en) 2017-09-18 2021-04-27 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor wafer cleaning apparatus
US11854793B2 (en) 2017-09-18 2023-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor wafer cleaning apparatus

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