TW201034780A - Method and device of continuously wire-bonding between multiple terminals - Google Patents

Method and device of continuously wire-bonding between multiple terminals Download PDF

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Publication number
TW201034780A
TW201034780A TW098108999A TW98108999A TW201034780A TW 201034780 A TW201034780 A TW 201034780A TW 098108999 A TW098108999 A TW 098108999A TW 98108999 A TW98108999 A TW 98108999A TW 201034780 A TW201034780 A TW 201034780A
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TW
Taiwan
Prior art keywords
wire
solder joint
solder
bonding
line
Prior art date
Application number
TW098108999A
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Chinese (zh)
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TWI358337B (en
Inventor
Yen-Sheng Chou
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Powertech Technology Inc
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Application filed by Powertech Technology Inc filed Critical Powertech Technology Inc
Priority to TW098108999A priority Critical patent/TWI358337B/en
Publication of TW201034780A publication Critical patent/TW201034780A/en
Application granted granted Critical
Publication of TWI358337B publication Critical patent/TWI358337B/en

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Abstract

Disclosed are a method and a device of continuously wire-bonding between multiple terminals. A bonding wire is formed by wire-bonding, in turn comprising a ball bond on a first terminal, a first wire section formed between the first and second terminals, a folded wire section on the second terminal, a second wire section formed between the second and third terminals, and a stitch bond on the third terminal. The folded wire section has a first wire bond bonded on the second terminal and a second wire bond bonded on the first wire bond. Accordingly, it can solve the problem of damage or peeling on terminal's surface or between the connected interfaces of conventional multiple wires caused by wire-bonding impact, and it also increase the bonding strength and stability of the bonding wire.

Description

201034780 六、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體裝置之製造技術，特別係有關 於一種多焊點之間不截斷之連續打線方法與結構。 【先前技術】 近年來’為了能達到電子產品輕薄短小的要求，半導 體的後段製程都在進行三度空間（Three Dimensi()n ; 3D) 〇 的封裝’以期利用最少的面積來達到較高的密度或是記 憶體的容量等。現階段已發展出使用晶片堆疊（chip stacked)的方式來達成三度空間的封裝。 在一種習知的多晶片封裝技術中’可將複數個晶片相 互堆疊並設置於一晶片載體上，晶片上的焊墊不可被覆 蓋或阻礙，然後使用打線的製程（wire bonding process) 來使複數個晶片中相同訊號的焊墊電性連接至晶片載體 之同一接指，即具備多焊點之間串連之型態。打線形成 之焊線的電性連接品質與結構強度是非常重要的，這決 定了電子封裝產品之可靠度與運作效能。而目前的串連 方式是以多段式形成之焊線在同一焊墊上鍵合。在焊線 與焊線之間相接的鍵合界面若產生剝離（peeling)便會有 電性斷路問題，若避免剝離一昧地增加同一焊墊上打線 壓焊的次數與強度，越容易在焊墊表面造成損傷。 如第1圖所示，為習知一種多晶片打線結構之截面示 意圖。該多晶片打線結構1〇〇係包含一第一晶片1〇、複 數個第二晶片20、一第一焊線12〇、複數個第二焊線ι3〇 3 201034780 以及一晶片載體30。該晶片載體3〇係可為一印刷電路 板之類基板或一導線架（或稱引線框架）。該第一晶片1〇 與該些第二晶片20係為半導體材質並可以堆疊方式設 置於該晶片載體30上。該第一銲線12〇與該些第二焊線 1 3 0係以打線方式形成，用以分別電性連接該第一晶片 1 〇至該些第二晶片20以及該些第二晶片2〇之間或至該 該晶片載體30。 〇 該第一晶片10之主動面上係具有至少一焊墊，以做 為一第一焊點111，該些第二晶片2()主動面上係各具有 至少一焊墊21，在每一焊墊21上預先以打線工具（或可 稱乾嘴’ capillary)以放電燒球（electHcal spark)形成一結 線凸塊（stud bump)做為一第二焊點112，即第一次壓焊 在對應焊墊21上。之後，以打線方式形成該第一焊線 12〇，其一端壓焊在該第一焊點m(即該第一晶片1()之 焊塾）並拉線由該第一焊線120延伸至該第二焊點112， 並使該第一焊線120之另一端壓焊在該焊墊21上之第二 焊點112，再切斷焊線。此時，該第一焊線丨2 〇之一球 接。端121係接合在該第—焊點in，該第一焊線12〇 之一線尾端122係接合在該第二焊點112，即第二次壓 焊在對應焊墊2 1上。 接著，再打線形成至少—第二焊線130，在兩個第二 曰曰片20之間各形成有一球接合端131與一線尾端132, 第二焊線130之球接合端131係鍵合至該第一焊線12〇 之•玄線尾端122，並往更下方第二晶片2〇之該第二焊點 201034780 (〇°ping)，再第二焊線130之線尾端132鍵合 至：方第二晶μ 20之該第二焊點112。依晶片堆叠數目 重覆以上打線方式，直到最後的第二焊線130之一線尾 端132連接到該晶片載體之接指（即第三焊點113)， 而使§亥第一晶片10、贫此篦一丨H 斗 、 该些第一晶片20與該晶片载體3〇 © Ο 達成多段焊線之電性串連。如第2圖之放大圖所示，於 上述的習知打線方式中’位於其中一焊墊21之部位，要 先使例如結線凸塊之第二焊點112接合在該焊塾Μ，此 為第-次壓焊。該第—焊線12G之該線尾端接合在 第二焊.點112,此^第二次壓焊。該第二焊線13〇之一 球接合端m係壓焊在該第一焊線120之該線尾端122 與第二焊點112,此為第三次壓焊。目此，該焊墊21係 經過三次的打線壓焊次數，尤其是在第三次壓焊仍需要 有足夠的壓焊力，否則一旦在上方的該第二焊線13〇之 球接合端131產生剝離，便會造成整個串連的電性斷 路’但這卻會造成該焊墊21之表面容易產生損傷 (damage)，導致產品良率降低，影響電子封裝產品之可 靠度。此外，在以多段焊線串連的多焊點之間，其連接 之電性路徑會經過焊線尾頭壓焊形成之鍵合界面，當串 連的焊點數量越多’電流需要通過的鍵合界面也越多， 容易有訊號衰竭或延遲的現象。 【發明内容】 為了解決上述之問題，本發明之主要目的係在於提供 一種多焊點之間不截斷之連續打線方法與結構，可有效 201034780 且同時地解決因習知多段焊線串連所受到的打線衝擊而 在焊墊表面產生損傷與在習知分段 / 刀仅垾線間鍵合界面產生 剝離而引起電性斷路之問題。 本發明之次-目的係在於提供一種多焊點之間不載 斷之連續打線方法與結構’可增加連接在多焊點之間焊 線之黏著力與穩定度。 本發明之再"目的传尤机坦/u . Ο Ο 曰妁係在於棱供一種多焊點之間不截 斷之連續打線方法與結構，卽估由 傅即使串連的焊點數量越多， 電流需要通過的鍵合界面卻不會 个|嶒加龅減少訊號衰蝎 或延遲的現象。 本發月之再目的係在於提供一種多焊點之間不截 斷之連續打線方法與結構，能查 # 此違到在中間串連之焊點防 止斷線之緩衝功效。 本發明的目的及解沐甘。 、其技術問題疋採用以下技術方 案來實現的。本發明描千 發月揭不—種多焊點之間不截斷之連續 打線方法’主要包含以下步驟：首先，提供一第一焊點、 至v _一焊點以及一第三焊點。接著，打線形成一焊 線，該焊線係依序具有—球接合端、—第—線段、至少 -返折線部、-第二線段以及―線尾端，該球接合端係 接合至該第一焊點，兮給Β 1 坪點該線尾端係接合至該第三焊點，該 第-線段係形成於該第一焊點與該第二焊點之間，以一 體連接該球接合端與該返折線部，該返折線部係具有一 第一線壓焊點與—第-雄 弟一綠壓焊點，該第一線壓焊點係接 合至該第二焊點，马'笛-·4& Μ第一線壓焊點係接合至第一線壓焊 6 201034780 點，該第二線段係形成於該第二焊點與該第三焊點之 體連接該返折線部與該線尾端。本發明還揭示 月1’焱法形成之多焊點之間不截斷之連續打線結構。 ❹ ❹ 措施進—步實現。及解决其技術問題還可採用以下技術 塊在前述的連續打線方法中，該第二烊點係可為一凸 在前述的連續打線方法中， 並接合於中間堆叠晶片之焊塾上塊係可為-結線凸塊 上之在焊前:，的連續打線方法中’該第-焊點係可為-晶片 在前这:二第三焊點係可為一晶片載體上之接指。 在…連續打線方法中，該第一 載體上之接指， ^ J ^曰日片 塊。 °"第二焊點係可為一晶片焊墊上之凸 係可具有一緩 在前述的連續打綠 ^ 打線方法中，該返折線部 衝線弧。 衝線弧係可朝向該第 在前述的連續打綠 只玎踝方法中，該緩 —焊點。 (Au) 在前述的連續打線方法巾，該焊線之 材質係可包含金 在前述的連續打 線方去中，該返折線部係另可具有一 第三線壓焊點，其係接合 焊點之間的線段。 由以上技術方宰 茶了从看出，本發明之多 至在第一線壓焊點與第二線壓 焊點之間不截 7 201034780 斷之連續打線方法與結構，具有以下優點與功效： 一、 利用多焊點之間不截斷之連續打線技術作為其中之 一技術手段，可有效提高打線製程之工作效率，並 節省焊線燒結成球接合端之使用量。此外，由於淳 線為不截斷的連續串連多個焊點，在中間焊點 返折線部的第二線壓焊點即使斷裂也不會影響電性 品質，故能有效且同時地解決因習知多段焊線串連 ❹ 所受到的打線衝擊而在烊墊表面產生損傷與在習知 分段焊線間鍵合界面產生剝離而引起電性斷路之問 題。 二、 利用焊線之線段彎折形成在中間焊點上返折線部作 為其中之一技術手段，可增加焊線在中間焊點上之 黏著力與穩定度。 三、 利用一焊線串連多個焊點並以線段彎折方式在中間 焊點上形成返折線部作為其中之一技術手段，即使 〇 串連的焊點數量越多，電流需要通過的焊線與焊線 間鍵合界面卻不會增加’故能減少訊號衰竭或延遲 的現象。 四、 利用一焊線串連多個焊點並以線段彎折方式在中間 焊點上形成返折線部作為其中之一技術手段，返折 線部之第二線壓焊點可作為預斷緩衝作用，即使斷 開也不會影響電性連接品質，能達到在中間串連之 焊點防止斷線之緩衝功效。 【實施方式】 8 201034780 以下將配合所附圖示詳細說明本發明之實施例，然應 注意的是，該些圖示均為簡化之示意圖，僅以示意方法 來說明本發明之基本架構或實施方法，故僅顯示與本案 有關之元件與組合關係，圖中所顯示之元件並非以實際 實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例 與其他相關尺寸比例或已誇張或是簡化處理，以提供更 清楚的描述。實際實施之數目、形狀及尺寸比例為一種 Ο Ο 選置性之設計，詳細之元件佈局可能更為複雜。 依據本發明之第一具體實施例，一種多焊點之間不截 斷之連續打線方法舉例說明於第3Α至31圖之製程中元 件之截面示意圖。其中’使用前述方法形成的多焊點之 間不截斷之連續打線結構可見於第31圖。本發明之多焊 點之間不截斷之連續打線方法包含以下步驟：首先，如 第3Α至3F圖所示，提供一第—焊點2ιι、至少一第二 焊點2 12以及一第二焊點2 } 3。在本實施例中’該第一 焊點211係可為一最上層晶片（即第一晶片4〇)之焊塾（如 第3A圖所示），該焊塾之材質可包含銘或銅等金屬。而 -亥第—焊點213係可為一晶片載體上之接指，以提供 打打線連接之實施例說明。如第至3E圖所示，該 第一焊點212係可為a换 如， 、， j為凸塊，例如由打線形成之球接合端 並經旋即截斷之結線凸塊(stu“ump)，凸塊的硬度可小 ;焊墊並與焊線中非球接合端之部位（如中間線段之 線壓焊點或線尾端)建立出非平面接合的鍵合界面，故能 以增加焊線之接合強_命；& 食度與面積。在本實施例中，例如結 201034780 線凸塊之該第二焊點212係可接合於中間堆疊晶片（第 二晶片5.0)之焊墊51上。 如第3A圖所示，該第一晶片4〇與該些第二晶片5〇 係堆疊在該晶片載體60之上，其中該第一晶片4〇位於 最上層’該些第二晶片50係疊設於該第一晶片4〇與該 晶片載體60之間，該第二晶片5〇之數量係可增加並往 上堆疊，以達到較高之容量或達到較多之功能應用。更 〇 具體地，該第一晶片40與該些第二晶片50之主動面係 朝上並以階梯狀交錯排列，以使該第二晶片5〇之焊墊 51露出，故可完全黏晶堆疊作業之後在一次進行多焊點 之間不截斷之連續打線作業。該晶片載體6〇係可為一印 刷電路板、一導線架（L/F)、一電路薄膜或各種晶片載 體。此外，可利用已知黏晶材料，例如雙面黏性膠帶、 B階黏膠（B-stage adhesive)或是晶片貼附物質（Die Attach Material，DAM)，以黏貼該些晶片4〇、5〇之間與 © 黏貼最下方之該第二晶片5〇至該晶片載體6〇之上表 面。本實施例中，如第3E圖所示，該第一焊點211與該 些第一焊點2 1 2係排列在同一側向而有利於與該晶片載 體60之該接指（即第三焊點213)以打線方式達到電性連 接。 再如第3A圖所示，該第二焊點2丨2係利用一打線工 具（capillary)70通過放電燒球方式使焊線之露出端燒結 成一結線凸塊並焊接於該第二晶片5〇之焊墊51上。在 形成其中一第二晶片50之該第二焊點212之後，如第 10 201034780 3B與3C圖所示’相鄰第二晶片5〇之焊墊51上以打線 方式形成在一結線凸塊。如第3D與3E圖所示，依序在 後續每一第二晶片50之焊墊51上以打線方式各形成一 結線凸塊。故每一第二晶片50之焊墊51上皆設有一第 二焊點2 1 2。 接著，如第3F至31圖所示，打線形成—連續串連多 焊點之焊線220，該焊線220係為一種可弯折之金屬細 Q 線，通常其材質係可為金（Au)，或可為銅（Cu)或鋁（A1)。 該焊線220可不分段地串連多顆晶片4〇、5〇至該晶片載 體60的訊號傳遞與接地/電源路徑。該焊線22〇係依序 具有一球接合端22i、一第一線段222、至少一返折線部 223、一第二線段224以及一線尾端225(如第3H圖所 示）。在本實施例中，該焊線220係可為正向打 bonding)形成，此乃為由晶片至基板的打線操作。即在 打線接合時，該球接合端221係接合於晶片上焊墊，該 〇 線尾端225(或稱尾鍵合端或訂合式接合端，stitchb〇nd) 係接合於該晶片載體上接指。 如第3G圖所示，該球接合端221係接合至該第一焊 點211，該第一線段222係形成於該第一焊點211與該 第二焊點212之間，以一體連接該球接合端221與該返 折線部223。接著，以打線工具70牽引該焊線220不截 斷地往下接合相鄰該些第二晶片5〇上之結線凸塊（即其 中一第一焊點212)。並在該第二焊點212(即結線凸塊） 上係形成出一返折線部2 2 3，其係依照打線工具特定的 201034780 返復來回移動方式所形成，再往外拉出一線段。如第3h 圖所示，由於在本實施例中具有多顆中間堆疊之第二晶 片50,第二晶片50與第二晶片5〇之間可拉出一中間= 段229。如第31圖所示，重覆以上操作，在每一第二焊 點212上形成一返折線部223以及在該些第二晶片 之間可拉出一中間線段229。並再最後操作的第二焊點 212上，拉出該第二線段224,再使該線尾端225接合到 〇該第三焊點213，以完成本發明之多焊點之間不截斷之 連續打線結構200(如第31圖所示），而使該第一晶片4〇 與該些第二晶片50可電性連接至該晶片載體6〇。 如第4A圖所示，該返折線部223係具有一第一線壓 焊點226與一第二線壓焊點227，該第一線壓焊點 係接合至該第二焊點212，該第二線壓焊點227係接合 至第一線壓焊點226。該返折線部223可為s形曲折並 封閉之。較佳地，另可具有一第三線壓焊點227a，接合 © 至在第一線壓焊點226與第二線壓焊點227之間的線 段，以使該返折線部223為扁平狀。此外，一中間線段 229係一體連接該返折線部223並由該第二線壓焊點 往其它第二焊點212延伸。該返折線部223可增加該焊 線220之黏著力與穩定度，並提供作為防止線拉斷之緩 衝線段。具體而言，該返折線部223係可具有一緩衝線 弧228，該緩衝線弧228係位在該返折線部223之最高 點。如第31與4A圖所示，該緩衝線弧228係可朝向該 第一焊點211，以使後續的線段（如中間線段229或該第 12 201034780 二線段224)方便往相鄰第二焊點212或該第三焊點213 拉伸。該第二線段224係形成於該第二焊點212與該第 三焊點21 3之間’以一體連接該返折線部223與該線尾 端 225。 在其他變化例中’如第4B圖所示，該返折線部223 係可為在該第.一線段222做單一次往復弯折之後再壓焊 形成該第二線壓焊點227，故該返折線部223之形成係 ❹ 朝向該第一線段222，可藉以壓低該第一線段222之弧 南。之後’適當回復伸直後再往其它相鄰該第二焊點2 i 2 延伸，故該返折線部223可為往上突起的形曲折並為 封閉狀。或者，如第4C圖所示，該返折線部223係可 為往該第二線段224做單一次往復彎折之後，再壓焊形 成該第二線壓焊點227在該第一線壓焊點226上。之後 適當回復伸直後再往相鄰的第二焊點212或該第三焊點 213延伸。以上實施例，皆是利用該打線工具在第二 D焊點2i2上做出特定形狀線弧的返折線部，以增加 該焊線2 2 0之黏著力與穩定性。201034780 VI. Description of the Invention: [Technical Field] The present invention relates to a manufacturing technique of a semiconductor device, and more particularly to a continuous wire bonding method and structure which are not cut off between multiple solder joints. [Prior Art] In recent years, in order to meet the requirements of light and thin electronic products, the semiconductor back-end process is in the three-dimensional space (Three Dimensi () n; 3D) 〇 package's in order to achieve the highest with the least area. Density or the capacity of the memory. At this stage, the use of chip stacking has been developed to achieve a three-dimensional space package. In a conventional multi-chip package technology, a plurality of wafers can be stacked on each other and disposed on a wafer carrier. The pads on the wafer cannot be covered or blocked, and then a wire bonding process is used to make the plurality of wafers. The pads of the same signal in one wafer are electrically connected to the same fingers of the wafer carrier, that is, the type in which multiple solder joints are connected in series. The electrical connection quality and structural strength of the bonding wires formed by the wires are very important, which determines the reliability and operational efficiency of the electronic packaging products. The current series connection method is to bond on the same pad by a multi-stage solder wire. If the bonding interface between the bonding wire and the bonding wire is peeled, there will be an electrical disconnection problem. If the peeling is increased to increase the number and strength of the wire bonding on the same bonding pad, the easier it is to weld. The surface of the pad causes damage. As shown in Fig. 1, a cross-sectional view of a conventional multi-wafer wire bonding structure is shown. The multi-chip wire bonding structure 1 comprises a first wafer 1 , a plurality of second wafers 20 , a first bonding wire 12 , a plurality of second bonding wires ι 3 〇 3 201034780 , and a wafer carrier 30 . The wafer carrier 3 can be a substrate such as a printed circuit board or a lead frame (or lead frame). The first wafer 1 and the second wafers 20 are made of a semiconductor material and can be stacked on the wafer carrier 30. The first bonding wires 12 and the second bonding wires are formed in a wire-bonding manner for electrically connecting the first wafer 1 to the second wafers 20 and the second wafers 2 Between or to the wafer carrier 30. The active surface of the first wafer 10 has at least one pad as a first pad 111, and each of the second wafers 2 has at least one pad 21 on each of the active faces. The soldering pad 21 is pre-formed as a second solder joint 112 by using a wire bonding tool (or a drying nozzle) to form a second bump 112, that is, the first soldering is performed on the solder ball (electHcal spark). Corresponding to the solder pad 21. Thereafter, the first bonding wire 12 is formed by wire bonding, one end of which is pressure-welded to the first bonding pad m (ie, the bonding pad of the first wafer 1), and the wire is extended from the first bonding wire 120 to The second solder joint 112 is pressed and the other end of the first bonding wire 120 is soldered to the second solder joint 112 on the soldering pad 21, and the bonding wire is cut. At this time, one of the first bonding wires 丨2 球 is balled. The end 121 is bonded to the first solder joint in, and the first wire end 122 of the first bonding wire 12 is bonded to the second solder joint 112, that is, the second soldering is performed on the corresponding solder pad 2 1 . Then, at least the second bonding wire 130 is formed by wire bonding, and a ball joint end 131 and a wire tail end 132 are formed between the two second die pieces 20, and the ball joint end 131 of the second bonding wire 130 is bonded. To the first wire bonding wire 12, the black wire tail 122, and further to the second wafer 2, the second soldering point 201034780 (〇°ping), and the second bonding wire 130, the wire tail end 132 key And the second solder joint 112 of the second crystal μ 20 is merged. Repeating the above-mentioned wire bonding method according to the number of wafer stacks until the last wire terminal 132 of the second wire bonding wire 130 is connected to the finger of the wafer carrier (ie, the third soldering point 113), so that the first wafer 10 is poor In this case, the first wafer 20 and the wafer carrier 3〇 Ο are electrically connected in series. As shown in the enlarged view of FIG. 2, in the above-mentioned conventional wire bonding method, 'the portion of one of the pads 21 is first joined to the second pad 112 of the wire bump, for example, First-time pressure welding. The end of the wire of the first bonding wire 12G is joined to the second soldering point 112, which is the second bonding. One ball joint end m of the second bonding wire 13 is pressure-welded to the wire end 122 and the second pad 112 of the first bonding wire 120, which is a third pressure welding. Therefore, the pad 21 is subjected to three times of wire bonding, and in particular, a sufficient pressure welding force is required in the third pressure welding, otherwise the ball bonding end 131 of the second bonding wire 13 is once above. If the peeling occurs, the entire series of electrical disconnections will be caused, but this will cause the surface of the pad 21 to be easily damaged, resulting in a decrease in product yield and affecting the reliability of the electronic package product. In addition, between the multiple solder joints connected in multiple sections of the bonding wire, the electrical path of the connection is formed by the bonding interface formed by the welding of the tail of the bonding wire, and the more the number of soldering points in series, the key that the current needs to pass. The more interfaces, the more likely it is that the signal is exhausted or delayed. SUMMARY OF THE INVENTION In order to solve the above problems, the main object of the present invention is to provide a continuous wire bonding method and structure that are not cut off between multiple solder joints, and can effectively solve the problem of the conventional multi-segment wire bonding in series at the time of 201034780. The wire impact causes damage on the surface of the pad and causes a peeling at the bonding interface between the conventional segment/knife and only the wire to cause an electrical disconnection. The second objective of the present invention is to provide a continuous wire bonding method and structure that does not interrupt between multiple solder joints, which can increase the adhesion and stability of the bonding wires between the multiple solder joints. The object of the present invention is that the 棱 Ο 曰妁 在于 is used for a continuous wire bonding method and structure that is not cut off between multiple solder joints, and the number of solder joints even if it is connected in series by Fu The bonding interface through which the current needs to pass does not increase the signal attenuation or delay. The re-purpose of this month is to provide a continuous wire bonding method and structure that does not cut off between multiple solder joints, and can check the buffering effect of the solder joints in the middle to prevent disconnection. The object of the present invention is to solve the problem. The technical problems are implemented using the following technical solutions. The present invention describes a continuous method of wire-cutting that does not cut off between multiple solder joints. The main steps include the following steps: First, a first solder joint, a v-first solder joint, and a third solder joint are provided. Then, the wire is formed into a bonding wire, which has a ball joint end, a first line segment, at least a return line portion, a second line segment, and a "tail end", and the ball joint end is joined to the first a solder joint, 兮 Β 1 ping point, the end of the wire is joined to the third solder joint, the first line segment is formed between the first solder joint and the second solder joint to integrally connect the ball joint And the return line portion, the return line portion has a first line bonding point and a -th male-green-type solder joint, the first line bonding point is bonded to the second solder joint, the horse笛-·4& Μ first line pressure welding joint is joined to the first line pressure welding 6 201034780 point, the second line segment is formed at the second welding point and the third welding point body is connected to the return line portion and The end of the line. The present invention also discloses a continuous wire-bonding structure that is not interrupted between multiple solder joints formed by the month 1' method. ❹ ❹ Measures to achieve. And solving the technical problem, the following technical block may be used. In the foregoing continuous wire bonding method, the second defect may be a convex wire bonding method in the foregoing, and may be bonded to the upper stacking die of the intermediate stacked wafer. In the continuous wire bonding method of the pre-weld: on the junction bump, the first solder joint may be - the wafer is in front: the second solder joint may be a finger on the wafer carrier. In the continuous wire bonding method, the finger on the first carrier is a ^ J ^ 曰 block. °" The second solder joint may be a bump on a wafer pad which may have a slow continuous green line method, which is a line arc. The line arcing system can be oriented toward the aforementioned continuous greening method, the solder joint. (Au) In the above-mentioned continuous wire bonding method, the material of the wire may include gold in the above-mentioned continuous wire bonding, and the wire portion may further have a third wire bonding point which is bonded to the solder joint Line segment between. It can be seen from the above technical party that the continuous method and structure of the present invention is not continuous between the first line bonding point and the second line bonding point, and has the following advantages and effects: First, the use of continuous wire bonding technology between multiple solder joints as one of the technical means, can effectively improve the working efficiency of the wire bonding process, and save the use of wire bonding into the ball joint end. In addition, since the twisted wire is continuously connected in series with a plurality of solder joints, the second wire bond pad at the intermediate solder joint return line portion does not affect the electrical quality even if it is broken, so that it can be effectively and simultaneously solved due to the conventional knowledge. The segment welding wire is connected to the wire to cause damage to the surface of the mattress and the peeling at the bonding interface between the conventional segmented wires causes an electrical disconnection. Second, the use of the wire segment bending to form the return line portion on the intermediate solder joint as one of the technical means, can increase the adhesion and stability of the bonding wire on the intermediate solder joint. Third, the use of a wire bond in series with a plurality of solder joints and the formation of a fold line at the intermediate solder joints as a technical means, even if the number of solder joints in series is increased, the current needs to pass the solder The bonding interface between the wire and the wire bond does not increase, so it can reduce the signal failure or delay. Fourth, a plurality of solder joints are connected in series by a wire bond, and a fold line portion is formed on the intermediate solder joint by a wire segment bending method as one of the technical means, and the second wire bond pad of the return line portion can serve as a pre-breaking buffer function. Even if it is disconnected, it will not affect the quality of the electrical connection, and it can achieve the buffering effect of preventing the disconnection of the solder joints in the middle. [Embodiment] 8 201034780 The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The method and therefore only show the components and combinations related to the case. The components shown in the figure are not drawn in proportion to the actual number, shape and size. Some scale ratios are exaggerated or simplified. Processed to provide a clearer description. The actual number, shape and size ratio of the implementation is a choice of Ο Ο, and the detailed component layout may be more complicated. According to a first embodiment of the present invention, a continuous wire bonding method which is not interrupted between multiple solder joints is illustrated as a schematic cross-sectional view of the components in the processes of Figs. 3 to 31. A continuous wire structure in which the multi-solder joint formed by the above method is not cut off can be seen in Fig. 31. The continuous wire bonding method without breaking between the multiple solder joints of the present invention comprises the following steps: First, as shown in Figures 3 to 3F, a first solder joint 2 ιι, at least a second solder joint 2 12 and a second solder are provided. Point 2 } 3. In the present embodiment, the first solder joint 211 can be a solder paste of the uppermost wafer (ie, the first wafer 4) (as shown in FIG. 3A), and the material of the solder bump can include the inscription or copper. metal. The -Head- solder joint 213 can be a finger on a wafer carrier to provide an illustration of a hit wire connection. As shown in FIG. 3E, the first solder joint 212 can be replaced by a, for example, j is a bump, for example, a stu "ump" which is formed by a ball joint end formed by wire bonding and is immediately cut off. The hardness of the bump can be small; the pad can establish a non-planar bonding interface with the non-ball joint end of the wire (such as the wire bond pad or the wire end of the middle segment), so the wire can be added Bonding strength and life; in this embodiment, for example, the second solder joint 212 of the junction 201034780 wire bump can be bonded to the pad 51 of the intermediate stacked wafer (second wafer 5.0). As shown in FIG. 3A, the first wafer 4 and the second wafers 5 are stacked on the wafer carrier 60, wherein the first wafer 4 is located at the uppermost layer of the second wafers 50. Stacked between the first wafer 4 and the wafer carrier 60, the number of the second wafers 5 can be increased and stacked upwards to achieve higher capacity or to achieve more functional applications. The active surface of the first wafer 40 and the second wafers 50 are upwardly arranged and staggered in a stepped manner to make the first The pad 51 of the wafer 5 is exposed, so that the continuous wire bonding operation without cutting off between multiple solder joints can be performed after the stacking operation is completed. The wafer carrier 6 can be a printed circuit board and a lead frame (L). /F), a circuit film or various wafer carriers. In addition, known adhesive materials such as double-sided adhesive tape, B-stage adhesive or Die Attach Material can be used. DAM), to adhere the lower surface of the second wafer 5 to the upper surface of the wafer carrier 4 to the top of the wafer carrier 6 。. In this embodiment, as shown in FIG. 3E, The first solder joint 211 and the first solder joints 2 1 2 are arranged in the same lateral direction to facilitate the electrical connection with the finger of the wafer carrier 60 (ie, the third solder joint 213) in a wire bonding manner. As shown in FIG. 3A, the second solder joint 2丨2 is sintered by a firing ball 70 to form a junction bump of the bonding wire and soldered to the second wafer 5 by a firing ball method. On the pad 51. After forming the second pad 212 of one of the second wafers 50, 10 201034780 3B and 3C show 'adjacent second wafer 5 〇 pads 51 are formed in a wire bonding manner in a wire bump. As shown in Figures 3D and 3E, sequentially in each subsequent second wafer 50 A bonding bump is formed on each of the pads 51. Therefore, a second pad 2 1 2 is formed on the pad 51 of each of the second wafers 50. Next, as shown in Figures 3F to 31, the wires are wired. Forming a continuous series of multiple solder joints 220, which is a bendable metal thin Q line, usually made of gold (Au), or copper (Cu) or aluminum ( A1). The bonding wire 220 can serially connect a plurality of wafers 4, 5 〇 to the signal transmission and ground/power path of the wafer carrier 60 without segmentation. The bonding wire 22 has a ball joint end 22i, a first line segment 222, at least one return line portion 223, a second line segment 224, and a line tail end 225 (as shown in Fig. 3H). In this embodiment, the bonding wire 220 can be formed by positive bonding, which is a wire bonding operation from the wafer to the substrate. That is, when the wire bonding is performed, the ball bonding end 221 is bonded to the pad on the wafer, and the wire tail end 225 (or the tail bonding end or the stitching bonding end, stitchb〇nd) is bonded to the wafer carrier. Refers to. As shown in FIG. 3G, the ball joint end 221 is coupled to the first solder joint 211, and the first line segment 222 is formed between the first solder joint 211 and the second solder joint 212 to be integrally connected. The ball joint end 221 and the return line portion 223. Then, the bonding wire 220 is pulled by the wire bonding tool 70 to join the wire bonding bumps (i.e., a first solder joint 212) adjacent to the second wafers 5 without uninterruptedly. A return line portion 2 2 3 is formed on the second solder joint 212 (ie, the junction bump), which is formed according to the specific back and forth movement mode of the 201034780, and then pulls out a line segment. As shown in Fig. 3h, since there are a plurality of intermediate stacked second wafers 50 in this embodiment, an intermediate = section 229 can be pulled between the second wafer 50 and the second wafer 5''. As shown in Fig. 31, repeating the above operation, a return line portion 223 is formed on each of the second pads 212, and an intermediate line segment 229 is pulled between the second wafers. And the second solder joint 212 is finally pulled out, the second wire segment 224 is pulled out, and the wire tail end 225 is joined to the third solder joint 213 to complete the multi-solder joint of the present invention. The continuous wire structure 200 (as shown in FIG. 31) is electrically connected to the first wafer 4 and the second wafer 50 to the wafer carrier 6 . As shown in FIG. 4A, the return line portion 223 has a first wire bond pad 226 and a second wire bond pad 227, and the first wire bond pad is bonded to the second pad 212. The second wire bond pad 227 is bonded to the first wire bond pad 226. The return line portion 223 may be s-shaped and closed. Preferably, a third wire bonding pad 227a is further provided, which is bonded to a line between the first wire bonding pad 226 and the second wire bonding pad 227 such that the folding wire portion 223 is flat. In addition, an intermediate line segment 229 is integrally connected to the return line portion 223 and extends from the second wire bond point to the other second solder joint 212. The return line portion 223 increases the adhesion and stability of the wire 220 and provides a buffer line as a line break prevention. Specifically, the return line portion 223 can have a buffer line arc 228 that is at the highest point of the return line portion 223. As shown in FIGS. 31 and 4A, the buffer line arc 228 can face the first pad 211 to facilitate subsequent line segments (such as the intermediate line segment 229 or the 12th 201034780 second line segment 224) to be adjacent to the second soldering. Point 212 or the third pad 213 is stretched. The second line segment 224 is formed between the second solder joint 212 and the third solder joint 213 to integrally connect the return line portion 223 and the tail end 225. In other variations, as shown in FIG. 4B, the return line portion 223 may be formed by re-welding the second line bond pad 227 after the first line segment 222 is bent back and forth. The formation of the return line portion 223 toward the first line segment 222 can be used to lower the arc of the first line segment 222. Thereafter, the appropriate return is straightened and then extended to the other adjacent second solder joint 2 i 2 , so that the return line portion 223 may be a meandering shape and a closed shape. Alternatively, as shown in FIG. 4C, the return line portion 223 may be a single reciprocating bend to the second line segment 224, and then re-welded to form the second wire bond pad 227 at the first wire bond pad. Point 226. Thereafter, the appropriate return is straightened and then extended to the adjacent second pad 212 or the third pad 213. In the above embodiments, the line-cutting tool is used to make a return line portion of a specific shape line arc on the second D-weld point 2i2 to increase the adhesion and stability of the wire bond 2200.

以省略'一 省略一次球接合端之壓焊次數。 的返折線部223的第 響電性品質。該烊線 的第二焊點212上可 故能有效且同時地解 13 201034780 決因習知多段焊線串連所受到的打線衝擊而在焊塾之表 面產生㈣以及纟習知/分段焊、線間鍵合界面產生剝離而 引起電性斷路之問題。 依據本發明之第二具體實施例，另一種多焊點之間不 截斷之連續打線結構說明於第5圖之截面示意圖。該多 焊點之間不戴斷之連續打線結構3〇〇包含一第一焊點 211、至少一第二焊點212、_第三焊點213以及打線形 〇成串連該些焊點211、212與213之焊線22()。其中與第 一實施例相同的主要元件將以相同符號標示，並具有上 述之相同作用，在此不再予以贅述。該焊線22〇之形成 方法亦如同第一實施例所述技術相同。 在此實施例中，該焊線22G係可為逆向打線（旧⑽ bonding)形成。該第一焊點211係可為一晶片載體上 之接指，而該第三焊點213係可為設置在第一晶片 之焊墊上的凸塊。而該第二焊點212係為凸塊，其係設 ©置在中間堆疊第二晶片50之焊墊51上。該烊線22〇之 該球接合端22丨係以球接合方式焊接在第一焊點2ιι(該 晶片載體60之接指），該返折線部223係設置於該第二 焊點212上，該焊、線220之線尾端225係以壓印接合方 式焊接在該第三焊點213(該第一晶片4〇之焊墊上之凸 塊）。使用反向打線的模式，可有效降低該焊線22〇之線 弧高度，因此可符合低厚度封装構造之要求。 以上所述，僅疋本發明的較佳實施例而已，並非對本 發月作任何形式上的限制，雖，然本發明已以較佳實施例 14 201034780 揭露如上，然而並非用以限定本發明，任何熟悉本項技 術者，在不脫離本發明之技術範圍内，所作的任何簡單 修改、等效性變化與修飾，均仍屬於本發明的技術範圍 内。 【圖式簡單說明】 第1圖.為、知一種多晶片打線結構之截面示意圖。 第2圖.為第！圖中一上方焊線之球接合端壓焊一下方 ΟIn order to omit 'one, the number of times of welding of the ball joint end is omitted. The electrical quality of the return line portion 223. The second solder joint 212 of the squall line can be effectively and simultaneously solved. 13 201034780 Depending on the wire impact impact of the conventional multi-segment wire bond series, the surface of the solder joint is generated (4) and the conventional/segment welding, The inter-line bonding interface creates a problem of peeling and causing an electrical disconnection. In accordance with a second embodiment of the present invention, another continuous wire structure that is not interrupted between multiple solder joints is illustrated in cross-section of Figure 5. The continuous wire bonding structure 3 不 without the break between the multiple solder joints includes a first solder joint 211, at least one second solder joint 212, a third solder joint 213, and a wire-shaped twisted pair of the solder joints 211 , 212 and 213 welding wire 22 (). The same elements as those in the first embodiment will be denoted by the same reference numerals and have the same functions as described above, and will not be described again. The method of forming the bonding wire 22 is also the same as that described in the first embodiment. In this embodiment, the bonding wire 22G can be formed by reverse bonding (old bonding). The first solder joint 211 can be a finger on a wafer carrier, and the third solder joint 213 can be a bump disposed on a pad of the first wafer. The second solder joint 212 is a bump which is disposed on the pad 51 on which the second wafer 50 is stacked. The ball joint end 22 of the twist line 22 is soldered to the first solder joint 2 ι (the finger of the wafer carrier 60) by ball bonding, and the return line portion 223 is disposed on the second solder joint 212. The wire tail 225 of the soldering wire 220 is soldered to the third pad 213 (the bump on the pad of the first wafer 4) by embossing. By using the reverse wire bonding mode, the wire arc height of the wire 22 can be effectively reduced, thereby meeting the requirements of a low-thickness package structure. The above is only the preferred embodiment of the present invention, and is not intended to limit the present invention in any way. However, the present invention has been disclosed above in the preferred embodiment 14 201034780, but is not intended to limit the present invention. Any simple modifications, equivalent changes and modifications made by those skilled in the art without departing from the scope of the present invention are still within the technical scope of the present invention. [Simple description of the drawing] Fig. 1 is a schematic cross-sectional view showing a multi-wafer wire bonding structure. Figure 2. For the first! In the figure, the ball joint end of the upper wire is welded under one Ο

太干線已接合於焊點之線尾端之局部放大立體 圖。 第3 A至31圖.為依據本發明之第一具體實施例的在多 焊點之間不截斷之連續打線方法中的元件截面 示意圖。 第4A至4C® :為依據本發明之第一具體實施例的多焊 ’.、占之間不截斷之連續打線方法中用以繪示不同 返折線部形狀變化之局部截面示意圖。 第5圖··為依據本發明之第二具體實施例的另一種多焊 點之間不截斷之連續打線方法所形成之結構之 截面示意圖。 【主要元件符號說明 ] 10 第一晶片 20 第二 -曰 tl -曰曰 30晶片栽體 40 第一晶片 50 第二 •曰 ϋ -ΒΒ /l 60晶片載體 21 焊墊 5 1 焊墊 70 打線工具 15 201034780 100 多 晶 片 打線結構 111 第 一 焊 點 112 笛一 ——* 焊 點 113 第J L焊點 120 第 一 焊 線 121 球接 合 端 122 線尾端 130 第 二 焊 線 131 球接合 端 132 線尾端 200 連 續 打 線結構 211 第 一 焊 點 212 第二 焊 點 213 第i L焊點 220 焊 線 221 球接 合 端 222 第_ -線段 223 返 折 線部 224 第二 線 段 225 線尾端 226 第 一 線 壓焊點 227 第 二 線 壓焊點 227Α ： 第- 三線壓焊點 228 緩 衝 線 弧 229 中 間 線 段 300 連 續 打 線結構 16A partially enlarged perspective view of the end of the wire that has been bonded to the wire. 3A to 31 are schematic cross-sectional views showing elements in a continuous wire bonding method which is not cut between multiple solder joints according to the first embodiment of the present invention. 4A to 4C® are schematic partial cross-sectional views showing the change in the shape of the different fold line portions in the continuous wire bonding method according to the first embodiment of the present invention. Fig. 5 is a schematic cross-sectional view showing a structure formed by a continuous wire bonding method which is not interrupted between two kinds of multiple solder joints according to a second embodiment of the present invention. [Main component symbol description] 10 First wafer 20 Second-曰tl-曰曰30 wafer carrier 40 First wafer 50 Second•曰ϋ-ΒΒ/l 60 wafer carrier 21 Solder pad 5 1 Solder pad 70 Wire-punching tool 15 201034780 100 Multi-chip wire structure 111 First solder joint 112 Flute - * Solder joint 113 JL solder joint 120 First bond wire 121 Ball joint end 122 Wire end 130 Second bond wire 131 Ball joint end 132 Wire tail End 200 continuous wire structure 211 first solder joint 212 second solder joint 213 i r solder joint 220 bond wire 221 ball joint end 222 first _ - line segment 223 return line portion 224 second line segment 225 wire tail end 226 first line pressure Solder joint 227 Second line bond pad 227Α : First - third line bond pad 228 Buffer line arc 229 Middle line segment 300 Continuous wire structure 16

Claims (1)

201034780 七、申請專利範圍： 1、-種多焊點之間不截斷之連續打線方法，包 步驟： 提供一第一焊£1；、至少—银 矸點 S. V 第二焊點以及一第三 點；以及 —坪 ❹ 〇 打線形成一焊線，該焊線係依序具有一球接合端、 一第一線段、至少一返折線部、一第二線段以及一 線尾端，該球接合端係接合至該第一焊點，該線尾 端係接合至該第三焊點，該第一線段係形成於該 -焊點與該第二焊點之間’以一體連接該球接合端 與該返折線部’該返折線部係具有一第一線壓：點 與第—線壓焊點，該第一線壓焊點係接合至該 二焊點，該第二線壓焊點係接合至第一線壓焊點， 該第二線段係形成於該第二焊點與該第三焊點之 間，以一體連接該返折線部與該線尾端。 ，之 2 3 .根據申請專利範圍第！項之多焊點之間不截 續打線方法，其中該第二焊點係為一凸塊。 根據申請專利範圍第2項之多焊點之間不 續打線方法’其中該凸塊係為—結線凸 中間堆疊晶片之焊墊上。 接。於 心、根據申請專利範圍第！項之多烊 續打線方法，其中該第一焊點係為一：:：之連 墊，而該第三谭點係為一晶片裁體上之❹之释 5、根據申請專利範圍第i項之多焊點之間不_之連 17 201034780 6 7 9 10 ❹ 續打線方法’其中該第一焊點係為一晶片載體上之 接指，而該第三烊點係為一晶片烊墊上之凸塊。 根據申請專利範圍第1項之多焊點之間不截斷之連 續打線方法，其中該返折線部係、具有—緩衝線弧。 根據申請專利範圍第6項之多焊點之間不截斷之連 續打線方法，其中該缓衝線i係朝向該第—焊點。 根據申請專利範圍第1項之多焊點之間不截斷之連 續打線方法’其中該焊線之材質係包含金(Au)e 根據申請專利範圍第1項之多焊點之間不截斷之連 續打線方法，其中該返折線部係另具有—第 壓 焊點，其係接合至在第一線壓 一 坪點與第二線壓焊點 之間的線段。 、-種多焊點之間不截斷之連續打線結構，包含. -第-焊點、至少一第二焊點以及一第三焊點；以 及 一打線形 端、一第 及一線尾 線尾端係 該第一焊 合端與該 焊點與一 該第二焊 點，該第 成之焊線，該焊線係依序具有一球接合 -線段、至少一返折線部、一第二線段： 端，該球接合端係接合至該第一焊點，該 接合至該第三焊點’該第一線段係形成於 點與該第二焊點之間’以一體連接該球接 返折線部，該返折線部係具有一第一線壓 第二線壓焊點，該第一線壓焊點係接合至 點，該第二線壓焊點係接合至第一線壓焊 —線段係形成於該第二焊點與該第三焊點 18 201034780 之間，以-體連接該返折線部與該線尾端。 11、根據申請專利範圍第10項之多焊點之間不截斷之 連續打線結構，其中該第二焊點係為一凸塊。 n 請㈣範圍第u項之多蟬點之間不截斷之 連續打線結構’其中該凸塊係為'结線凸塊並接合 於中間堆疊晶片之焊墊上。 Ο 〇 13'根據申請專利範圍第1〇項之多焊點之間不截斷之 連續打線結構，其中該第一焊點係為一晶片上之焊 墊，而該第三焊點係為一晶片載體上之接指。 14、 根據申請專利範圍第10項之多焊點之間不截斷之 連續打線結構’其中該第一焊點係為一晶片載體上 之接指，而該第三焊點係為一晶片蟬墊上之凸塊。 15、 根據申請專利範圍第10項之多焊點之間不截斷之 連續打線結構，其中該返折線部係具有一緩衝線弧。 16、 根據申請專利範圍第15項之多焊點之間不截斷之 連續打線結構’其中該緩衝線弧係朝向該第一焊點。 17、 根據申請專利範圍第10項之多焊點之間不截斷之 連續打線結構，其中該焊線之材質係、包含金㈣。 18、 根據申請專利範圍第10項之多焊點之間不截斷之 連續打線結構’其中該返折線部另具有一第三線壓 焊點，其係接合至在第一線壓焊點與該第二線壓焊 點之間的線段。 19201034780 VII. Patent application scope: 1. - Continuous wire bonding method without cutting off between multiple solder joints, package step: provide a first welding £1; at least - silver enamel point S. V second solder joint and one And the ❹ ❹ 〇 形成 形成 形成 形成 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及The end is bonded to the first solder joint, the end of the wire is bonded to the third solder joint, and the first line segment is formed between the solder joint and the second solder joint to integrally connect the ball joint The end line and the return line portion have a first line pressure: a point and a first line bond point, the first line bond point is bonded to the second line, the second line bond point The second line segment is formed between the second solder joint and the third solder joint to integrally connect the return line portion and the tail end of the wire. , 2 3 . According to the scope of the patent application! There is no continuous wire bonding method between the plurality of solder joints, wherein the second solder joint is a bump. According to the second aspect of the patent application, the method of non-continuous wire bonding between the solder joints is performed, wherein the bumps are on the pads of the intermediate stacked wafers. Pick up. Yu Xin, according to the scope of patent application! The method of continuous threading, wherein the first solder joint is a pad of:::, and the third tanpoint is a release on a wafer. 5, according to the i-th item of the patent application scope There is no connection between the solder joints. 17 201034780 6 7 9 10 ❹ Continued line method 'where the first solder joint is a finger on a wafer carrier, and the third bump is a wafer pad Bump. According to the first aspect of the patent application, the continuous wire bonding method is not cut off between the plurality of solder joints, wherein the return line portion has a buffer line arc. A continuous wire bonding method in which a plurality of solder joints are not cut off according to the sixth aspect of the patent application, wherein the buffer line i is oriented toward the first solder joint. According to the scope of the patent application, the number of consecutive solder joints is not cut off. The material of the wire is gold (Au) e. According to the scope of the patent application, the number of solder joints is not truncated. The wire bonding method, wherein the return line portion further has a first pressure bonding point that is joined to a line segment between the first line pressing point and the second line bonding point. a continuous wire-bonding structure that is not interrupted between the plurality of solder joints, comprising: a - solder joint, at least a second solder joint, and a third solder joint; and a dozen linear end, a first and a tail tail end The first soldering end and the solder joint and the second solder joint, the first soldering wire, the bonding wire sequentially has a ball joint-line segment, at least one return line portion, and a second line segment: End, the ball joint end is joined to the first solder joint, the joint to the third solder joint 'the first line segment is formed between the point and the second solder joint' to integrally connect the ball joint return line a portion of the fold line portion having a first line pressure second wire bond pad, the first wire bond pad being bonded to a point, the second wire bond point being bonded to the first wire bond-line segment Formed between the second solder joint and the third solder joint 18 201034780, the return line portion and the tail end of the wire are connected in a body. 11. A continuous wire-bonding structure that is not interrupted between a plurality of solder joints according to item 10 of the patent application scope, wherein the second solder joint is a bump. n (4) The continuous wire structure is not cut off between the multiple points of the u-th item. The bump is a 'junction bump' and is bonded to the pad of the intermediate stacked wafer. Ο ' 13′ according to the patent application scope of the first item, the continuous wire bonding structure is not cut off between the multiple solder joints, wherein the first solder joint is a solder pad on the wafer, and the third solder joint is a wafer The finger on the carrier. 14. According to claim 10, the continuous wire bonding structure is not cut off between the solder joints, wherein the first solder joint is a finger on a wafer carrier, and the third solder joint is a wafer pad. Bumps. 15. A continuous wire-bonding structure which is not interrupted between a plurality of solder joints according to the tenth item of the patent application, wherein the return line portion has a buffer line arc. 16. A continuous wire-bonding structure in which a plurality of solder joints are not cut off according to the fifteenth aspect of the patent application, wherein the buffer line arc is oriented toward the first solder joint. 17. According to the tenth item of the patent application scope, the continuous wire bonding structure is not cut off between the solder joints, wherein the material of the bonding wire is gold (four). 18. According to claim 10, the continuous wire bonding structure is not cut off between the solder joints, wherein the return line portion further has a third wire bonding point, which is bonded to the first wire bonding point and the first The line segment between the two-wire bonding points. 19
TW098108999A 2009-03-19 2009-03-19 Method and device of continuously wire-bonding bet TWI358337B (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012092707A1 (en) * 2011-01-04 2012-07-12 Sandisk Semiconductor (Shanghai) Co., Ltd. Continuous wire bonding
CN103077903A (en) * 2011-10-25 2013-05-01 先进科技新加坡有限公司 Automatic wire tail adjustment system for wire bonders
CN111864530A (en) * 2019-04-30 2020-10-30 深圳市聚飞光电股份有限公司 Wire bonding method and optical device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012092707A1 (en) * 2011-01-04 2012-07-12 Sandisk Semiconductor (Shanghai) Co., Ltd. Continuous wire bonding
CN103077903A (en) * 2011-10-25 2013-05-01 先进科技新加坡有限公司 Automatic wire tail adjustment system for wire bonders
TWI483323B (en) * 2011-10-25 2015-05-01 Asm Tech Singapore Pte Ltd Automatic wire tail adjustment system for wire bonders
CN103077903B (en) * 2011-10-25 2016-04-06 先进科技新加坡有限公司 For the transfer matic tail regulating system of wire bonding machine
CN111864530A (en) * 2019-04-30 2020-10-30 深圳市聚飞光电股份有限公司 Wire bonding method and optical device

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