TW201032484A - Diversity combining iterative decoder - Google Patents

Abstract

An iterative decoder circuit includes an N number of sub-decoders, N-1 of the sub-decoders each being responsive to a baseband signal from one of M number of signal processing circuits. Each of the N-1 number of sub-decoders includes, an inner delay responsive to a baseband signal provided by a corresponding signal processing circuit for generating an inner delayed signal, a modified decoder that receives the inner delayed signal and generates a set partition signal, some of which have less errors than previous set partition signals. An Nth inner delay is responsive to the baseband signal and provides an Nth inner delayed signal. An Nth modified decoder is responsive to the Nth inner delayed signal and to the set partition signal and provides an output signal, wherein the probability of error of the output signal is reduced by correcting errors in some of the set partition signals.

Description

201032484 VI. Description of the Invention: Field of the Invention The present invention relates generally to wireless digital communication systems, and more particularly to receivers for use in such systems and including iterative decoders. [Prior Art] In a wireless digital communication system, the orientation of the receiving antenna can have a significant impact on receiver performance. Some antenna pointing may cause the signal to be unusable by the receiver. A well-known way to overcome this problem is to use "antenna diversity." This involves borrowing more than two receive antennas to receive the same transmitted signal and combining the signals in the receiver. The combined signal in this type of receiver typically has a higher probability of obtaining a correct decoding than one of the constituent signals alone. The best way to combine signals in a diversity receiver is called "maximum ratio combining." This method is well known to the industry and can be traced back to the era of Φ than communication and vacuum tubes. This involves weighting the individual signals by their individual signal-to-noise ratios and then adding the signals together. Other sub-optimal approaches have been studied for wireless digital communications, which have lower performance levels and less implementation complexity than the largest scale combiner. A method called "block selection" involves the selection of only a data block that does not have a bit error if it is indeed available from any of these signal paths. Many digital communication systems contain block numbers that allow the receiver to detect and/or correct bit errors within the data block. Examples include Reed_ Solomon (Rs) Digital and Cyclic Redundancy Check (CRC) numbers. The decoding results of these numbers for 201032484 can be selected from multiple antenna receivers to be selected in multiple operations. Although the block type selection cannot be matched with the "block between the output..θ, ^ ^ method is proportional to the performance of the maximum ratio,": the case of the 'Tenged white Gaussian noise (AWGN) channel, However, this method provides significant gain for many actual situations and channels. Context. It is true that the knife set known in the case of a single antenna is usually the signal of the antenna. However, this method is received from the antenna. Αα> mz sister is limited to the inability to use the output of one decoder to affect the operation of another decoder. In digital communication systems, it is common to use two levels of error correction 2: - internal digital and an external digital, and In the meantime, there is an interleaver. Generally speaking, the internal digital can be used to correct a short error event and the combination of the interleaver and the external digital can be used to correct a long error event. Example t' is based on the "Advanced Television System" The digital television signal transmitted by the standard (ATS) of the Commission (ATSC) utilizes an internal grid number and is coupled to an interleaver and an external Reed_solomon digital. In conventional prior art receivers, the internal decoders and external decoders operate independently with a deinterleaver therebetween. However, these conventional receivers typically operate at multiple dBs over the Shannon limits for their individual data rates and signal bandwidths. For example, the best traditional ATSC receiver can usually handle the carrier noise ratio (C/N) of about 9 according to the "visibility threshold (τ〇ν)", but the Shann〇n limit is about 丨〇$ Part of this difference can be due to the limitations of the grid and Reed_s〇1〇m〇n (rs) digital itself. However, the significant part of this difference is indeed due to the traditional decoding 201032484 m The architecture is not fully applicable to grid and rs forces. An example of this prior system can be shown in Figure 能. Figure 1 shows a prior art solution 1fv _ ” ” code 1〇 containing the internal decoder 12, The 自 交错 交错 amp amp 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收Decoder 16. The internal decoder 12 is typically a raster decoding technique in which the heart algorithm "is partially decoded from the signal processing circuit:: the word number, and the external hacker 16 typically utilizes the RS decoding technique: two ekamp - Massey algorithm to decode the remaining codes appearing within the received 7 . The external decoder 16 provides a signal that should be received and decoded. Note that the M w TSC A/53 system contains a random generator, so the external decoder generator (not shown) is processed, so that the yield is randomized = our coding algorithm can be optimized The internal and external solutions still cannot fully utilize the incorporated coding techniques as the internal and external decoders 12 and 16 are independently programmed to each other. ^=Enhanced image is used in the claw (3) 53 transmission # The full capacity of the collection. In some prior art systems, a one-of-a-kind solution involves interleaving, re-encoding, and re-encoding the output of the external decoder to generate a known input for a subsequent internal decoder, while limiting the ride. Star (DBS) standard. The pre-existing prior art system may have a limited memory bank for the re-encoding process, so the error in the output of the external decipherer may cause the re-encoded output to be an error from the point of 201032484. . In some transmission systems, this problem can be mitigated by the fact that the encoder state is reset by a regular interval. This is not the case in many transmission systems and is included in the ATSC A/53. Other prior art techniques utilize information from an external decoder to improve the performance of a subsequent internal decoder and claim to provide decoding processing of the ATSC A/53 signal at a benefit of 146 dB C/N '- 0.3 dB. Some of the information from this external decoder can be used to improve the internal decoder performance. However, this technology does not fully use all the information. For example, this technique does not utilize reliable corrected data bits available at the output of the Reed-Solomon decoder. In still other prior art techniques, an iterative decoder involves reinterleaving an "annotated decoded output" from an external decoder and utilizing to deduct the state in the subsequent internal decoder while asserting for "digital" The digital used in the Video Broadcasting (DVB) standard has a gain of about 〇 dB in terms of c/N performance. The primary cost associated with this gain is the additional memory necessary to store the delayed input and perform the re-interlacing. In the prior art, 'decoder aliasing requires a large amount of additional memory, and does not provide a mechanism for trade-off between memory size and performance for a given number of iterations. In addition, all of the above prior art iterative decoders are directed to a single-round scenario. In view of the foregoing, the ability to more fully utilize the digitals it collects for the use of iterative decoding and reduce the memory = size while maintaining or improving performance. For this, the components required for the step-by-step integration into the 201032484 can be applied to the signals transmitted according to the ATSC A/53.

Briefly, in one embodiment of the invention, an iterative decoder circuit '纟" includes N sub-decoders, each of which responds to - from one of the signal processing circuits Baseband signal. The Ni sub-decodings include: an "internal delay" in response to a baseband signal provided by a phase-receiving signal processing circuit to generate an internal delay signal; - a modified decoder that receives the The internal delay signal and the generation-set split signal 'the set split signal' are partially less erroneous than the previous set split signal. An Nth internal delay is responsive to the baseband signal and provides an Nth internal delay signal. An Nth modified decoder responds to the _th solid internal delay signal and the set split signal 'and provides an output signal 纟 to reduce the output by correcting errors in some of the set split signals The probability of a signal error. The foregoing and other objects, features and advantages of the present invention will become apparent from the Detailed Description of Description [Embodiment] To overcome the limitations of the prior art, and to overcome other limitations that can be apparent from the reading and understanding of the present application, the present invention discloses a method for utilizing an iterative decoding technique from an antenna or a self. Apparatus and method for decoding signals received by multiple antennas, thereby enabling a reduced bit error rate at low signal to noise ratios while reducing memory requirements. That is, if the user is a user who does not want the information, or should not be part of the signal transmitted and intended to be received, this is meaningless. The features and other features and characteristics of the present invention are set forth in a particular form and form part of the invention. For a better understanding of the invention, the advantages thereof, and the advantages thereof, which are utilized in the <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; A specific example of an embodiment. Figure 2 shows a signal processing circuit 22 that receives digital terrestrial television signals broadcast according to Standard A/53 of the Advanced Television Systems Committee (ATSC). In FIG. 2, a signal processing circuit 22 is shown to include a modulator 201, an analog to digital (A/D) converter 203, a baseband mixer 2〇4, a carrier recovery circuit 206, and a timing sequence. The recovery circuit 2〇5 and an adaptive equalizer 207. The tuner receives a radio frequency (RF) input 2 〇〇 and provides an intermediate frequency (IF) signal 202 to the a/D converter 203 to which the person is coupled. The A/D converter 203 is coupled to the tuner 201 and the baseband mixer 2〇4. The A/D converter 203 compares the analog IF signal at a rate that is not synchronized with the remote transmitter. Sampling is performed to generate a digital IF signal. The digital IF signal is then passed to the baseband mixer 2〇4. The baseband mixer 204 downconverts the digital IF signal to baseband and transmits the downlink converted baseband signal to the timing recovery circuit 205 to which the partner is coupled. . The baseband mixer 204 is coupled to the a/D converter 203, the timing recovery circuit 205, and the carrier recovery circuit 206. The carrier recovery circuit 206 is coupled to the baseband mixer 204 and the timing recovery circuit 2〇5. The carrier recovery circuit can be synchronized to the 1 wave frequency with 201032484 205. The timing recovery circuit ',' is coupled to the baseband mixer 204 and the adaptive equalizer 2〇7, and configured to perform the downlink converted baseband signal at a rate synchronized with the remote transmitter. Resample. The timing recovery circuit 205 automatically updates its resampling rate to maintain synchronism with the remote transmitter. The adaptor equalizer = 7 is connected to the timing recovery circuit 2 () 5 and is the final processing step before the signal leaves the &amp; processing circuit 22 and goes to the iterative decoder circuit. The adaptive equalization of the Muse removes the multipath distortion and other forms of intersymbol interference from the signal (Isis is filed in 2(9) 7 years ^ 5 曰, US Patent Application entitled "dynamic DETECTION DEVICE AND METHOD" Further details of the signal processing circuit 22 are provided in the text of the ll/ 620, 226, the disclosure of which is hereby incorporated by reference in its entirety.

In an alternate embodiment of the signal processing circuit 22, the A/D sampling rate is synchronized to the remote transmitter. This particular embodiment eliminates the need for the timing recovery circuit 205. A further alternative embodiment includes an automatic gain control (AGC), a digital filter, and various synchronization circuits. In alternative embodiments, different communication systems and different 彳s number processing configurations can be considered. Although a specific embodiment of the signal processing circuit 22 has been disclosed herein, it will be appreciated that those skilled in the art will be able to contemplate other embodiments. Referring now to Figure 3, in accordance with an embodiment of the present invention, a receiver 20 is shown as comprising a plurality of signal processing circuits 22, each receiving an input from a different antenna and being coupled to a modified iterative gema Circuit 24. The 201032484 iterative decoder circuit 24 operates as a sub-collector. The plurality of signal processing circuits 22 are _; containing N signal processing circuits 48_52' NL. Each signal processing circuit is shown as a self-corresponding antenna receive-input. For example, the first signal processing circuit 48 is shown as receiving its input from the antenna ANT #1. The second signal processing circuit 50 is shown as receiving its input from the antenna ANT #2, and the Nth signal processing circuit is received. The 52 series is shown to receive its input from an antenna biliary state, and the like. That is, as shown in Fig. 2, any number of antennas can be utilized to receive the (4) therefrom, and a corresponding number of signal processing circuits are received from the corresponding antenna. It is also contemplated that one or more of the n(d) processing circuits may themselves have multiple antenna inputs and utilize a maximum ratio combining or other technique to perform the fractional ordering of the first order. The output of the single-signal processing circuit having multiple antenna inputs for the purpose of the present invention is considered to be the same as that of a soap-signal processing circuit having a single-JC. antenna input. To simplify the description of the present specification, the signal processing circuit has been described and illustrated as having [antenna input. (d), that is, in the alternative embodiment of the present invention, any of the signal processing circuits can be inflicted with multiple antenna inputs. Each of the k processing circuits 22 can be used to convert the signal it receives from a radio frequency (10) signal into a digital baseband signal suitable for decoding by the iterative decoder circuit. The numbers received by each of the signal processing circuits are usually interleaved by the decoding technique used, and the receiver 20 is obscured. Each of the signal processing circuits 22 generates a digital baseband # number for decoding by the iterative decoder circuit 24. 12 201032484 In FIG. 3, the iterative decoder circuit 24 is shown as containing \ sub-decoders, each of which is coupled to receive input from a separate signal processing circuit 22. . For example, the sub-decoder 26 is shown as receiving input from the signal processing circuit 48, the sub-destroyer 34 is shown receiving input from the signal processing circuit 5, and the sub-decoder 46 is shown as The input is received from the signal processing circuit 52. Each of the signal processing circuits 22 generates a baseband signal, and the signal system

❹ Provide a corresponding internal delay to a corresponding sub-decoder. For example, the output of the signal processing circuit 48 is a baseband signal 23 which is provided to the internal delay 28 of the sub-decoder 26. Similarly, the output of the signal processing circuit 2 is a baseband signal 35, which is provided as an input to the internal delay 36 of the sub-decoder, while the output of the signal processing circuit 52 is a baseband signal 41' The internal delay 42 is provided to the sub-decoder as an input. The respective internal delays of the N sub-decodes are generated - the internal delay signal is supplied and provided to - the modified solution of the (four) connection, for example, the internal delay 28 is, - is shown to generate - an internal delay signal. Repair M 3G. The (d) delay % is the 'partial delay signal' and provides this to the modified decoder 3 to produce 8: the (four) delay 42 is shown to produce the internal delay annunciator 43 = provided to the modified decoding 44, ' ^ output signal 45, and the dry out ... / decommissioner is shown to provide the delayed delay of the delayed signal. The internal delayed signal signal has a solid delay delay, respectively, which can be set as required 13 201032484 Zero, by which the internal delay a is removed from the iterative decoder circuit 2G. Each of the modified decoders of the =N sub-decoders produces a knife-cut signal and provides this to a coupled The external delay/in other words, the modified decoders of the N sub-decoders: each of the last or the Nth modified decoder, generates a set split signal. The singular split signals 31 and 33 are Delayed by a variable delay, thereby generating delayed set split signals 54 and 2 which are used to remove some symbols from a subsequent sub-decoder consideration. If due to a failure in the sub-solver Unable to use reliable settings The failure is expressed in the set split signal. Referring now to the specific embodiment of FIG. 3, the modified decoder 30 is shown to generate a set split signal 3 丨 and the person provides the External delay 32. The modified decoder 38 is shown as generating - setting the split signal 33 and providing the one to the external delay 4. The set split signal 33 of the sub-coder 33 is compared to the sub-decoder Setting 26 split k number 3 1 has a lower probability of error because each modified decoder has the ability to remove extra errors from signals that benefit from a previous sub-decoder result. In other words, in this In the various embodiments of the invention, as in Figures 3, 12, 14 and 15, errors in some of the set split signals are corrected relative to the forward set split signal, thereby advantageously reducing overall errors. The probability, or in the embodiment of Figure 3, is the probability of error within the signal 45, which has a lower per-sub-decoder manufacturing cost compared to prior art iterative decoding techniques. Reliability is a description of a set split signal with minimal error 201032484. In one embodiment of the invention the reliability description contains a very low probability of error (le_10 or less) such as a Reed-Solomon (RS) (207 187) a digital block, such as the atsc A," the system user, if not detected by a faulty Rs decoder (that is, an RS decoder without a priori error location information) The error is reliable. In an alternative embodiment of the invention, an error correction and elimination (em > r-and_erasures) RS decoder is used (i.e., using a priori error location information). The RS decoder) does not detect digital blocks that cannot be corrected for errors and is necessarily necessarily reliable because the combination of some errors and elimination counts has a high probability of false decoding. When the error is corrected, the number is determined? The group can be # or not (4), and this false decoding probability must be taken into account. The first modified numerator 'or the modified decoder 3 of FIG. 3 produces a least reliable set split signal (the second modified decoder with the highest probability of error ' or the modified decoding @ 38, Generate - set the split number, which has a lower error probability than the decoder 3G and has a higher error probability than the set split signal of the subsequent sub-decoder, etc. N] of the N sub-decoders The external delay of each responds to one: correspondingly sets the split signal, and operates to generate a delayed-rectified split signal for the decoder of the subsequent sub-decoder. For example, in Figure 3, the hopper 26 has a delay of 32. The modified decanter 38 of the sub-decoder 34 is provided by (4) for receiving the set partition number 3 1 'at the same time - to the sub-extraction ^ 遽 54 and providing the defragmenter 34. The 201032484 section delay 40 is shown as receiving the set split signal", while generating a delayed set split signal 21 and providing the one to the modified decoder 44 of the sub-decoder 46. The delay-set split signal ^ 2] has (d) in these settings The variable delay of signals 31 and 33. This variable delay is determined by the (four) address logic of the material delay circuit (4), as will be described later. Figure 3 shows the internal delays 28, % and 42 of the specific embodiment. Each is a conventional delay line $, as is known in the industry. Each internal delay can contain a single-delay line or a combination of multiple smaller delay lines. Each of these beta delays can be made to | The band signal input is delayed by a predetermined (or fixed) period before being provided to the modified decoder coupled to an internal delay. In one embodiment of the invention, the fixed delay can be designed to compensate for a sub-decode. The worst case delay of the device. For a signal transmitted according to ATSC Α/53, the fixed delay for compensating for the worst case sub-decoder delay is 43884 symbols. In another embodiment, a larger one can be selected. Delay to compensate for longer processing delays. In still further embodiments, a shorter delay that does not compensate for the worst case sub-decoder delay may be selected. ❹ However, 'when using this delay' sometimes cannot Get this setting in time The signal is split for use by subsequent sub-decoders and must therefore be treated as unreliable by subsequent sub-decoders. The Ν-1 external delays 32 and 40 of the Figure 3 embodiment are more complex than the internal delays. 'The reason is that the de-interlacing process within the modified decoder, as discussed in further detail below. Further details of an exemplary external delay can be provided and discussed in Figures 9 and 11. 16 201032484, in a In an exemplary application, the receiver 20 is used in a wireless communication system, and the signal input to the signal processing circuit 22 is a digital terrestrial television signal 'like the one used by the Advanced Television Systems Committee (ATS). Know, the person defined by A/53. In the following article, we will discuss this-application. Operationally, the receiver 2 receives a signal through its N antennas and each of the N antennas provides a received signal to a corresponding one of the signal processing circuits 22, and then processes the The signal is received while the baseband signal is provided to the internal delays 28, 36, 42 of the corresponding sub-decodes $26, 34, 46. The internal delay delays the baseband signal by a magnitude that is determined by the worst processing delay of the sub-decoder and the desired trade-off between the size of the memory and the availability of the reliably set split signal. . Then, after being delayed by the internal delay, the baseband signal is provided to a corresponding modified decoder, which is sufficient to generate a set split signal like the signal 3^ or 33, and the signal is sufficient to decode the subsequent sub-sequence The device provides enough information to eliminate some of the cluster points by considering a given symbol interval. In one embodiment of the invention, the set split signal is comprised of two sub-signals. The first sub-signal contains set split information for each received symbol, wherein the information may or may not be reliable. The second sub-signal then contains a reliability indicator for a received symbol block. In the case of signals transmitted according to ATSC A/53, a reliable block is generated for each block having 828 symbols, ie, a Reed s〇i〇m〇n digital block corresponding to a 207 byte. Sex indicator. In summary, the set split output of each sub-decoder will have higher or equal reliability than the previous sub-decoder. 17 201032484 Figure 4 shows a different timing diagram illustrating how the Reeds〇1〇in〇n decoder wheel is associated with the set split signal. Six signals are shown in Figure 4: RS_fail 301, RS-out[7:0] 302, syml 303, symO 304, set-part 305, set_part_rel 30ό. RS_fail 301 is a 1-bit signal. When the RD numerator detects an uncorrectable error, the signal 3 〇丨 is set to 1. RS-Out[7:0] 302 is an 8-bit round-out tuple of the RS decoder. Syml 303 is the most significant bit of the symbol data (X2 in Figure 6.8 of ATSC A/53 Part 2 of Figure 6). SymO 304 is the least significant bit of the symbol data (XI of Figure 6 in ATSC A/53 Part 2, Figure 6.8). ❾ Set_part 305 is the set split signal, which is equal to Sym〇 3〇4.

Set a part-rel 306 is a set partition reliability signal, that is, equal to Rs_fau 30. In this example, the binary "丨" indicates an unreliable set split signal. The signals set_part 305 and set_part_rel 306 will be stored in external delay memory' which will be discussed in further detail in Figure 14. Figure 4 shows the same situation in which the first byte labeled "〇χΑ6" is the last bit of the first Reed-Solomon digital block that is reliably decoded (ie, no error can be detected). The second byte of the group 'marked as O "OxB 1" is the first byte of the second Reed-Solomon digital block that cannot be reliably decoded (ie, an uncorrectable error is detected). The levels of syml and sym〇 can be derived by dividing the octet of bytes into a plurality of 2-bit symbols starting with the most significant bit. Figure 5 shows further details of each of the N modified decoders in accordance with one embodiment of the present invention. In FIG. 5, a modified decoder 60 is shown as containing a modified internal decoder 62, which is shown as a handle-deinterleaver 64 via 18 201032484, which is modified by an external solution. Displayed as coupled to 1 Liaoqi 1 § 66. The modified decoding decoder 38 is identical. For the 胄## s _ '器 60 and the modified J, for the sake of simplicity, the modified solution is explained by the modified decoder 38, and the solution is 6. It will be like the sub-decoder 34. The second modified external decoder 66 provides a set 仏 对于 for a certain split 兮 兮 &lt; 6 '^ 解 。. The Di Ding split signal eliminates at least one group of 隹 &amp; 4 定 公 丨 ρ 于 于 于 于 于 于 于 于 于 。 。 。 。 。 。 。 。 。 。 。 。 。 消除 消除 消除 消除 消除 消除 消除 消除 消除 消除 消除 消除 消除The set of cuts is based on the error corrected output of the possible cluster point, and is derived from the external output 4 positive output, and if the cluster points are given to the internal encoder of the 2 The input is equal to the error corrected output of the external decoder and can be generated at the transmitter. The modified internal code (4) is displayed (10) in the 'delayed cut signal 7'. Note that in this example the signal 71 and the signal Μ the modified (four) decoder 62 is further displayed in response to the Oh. The delay signal 73, which in this example is the same as the signal 37. The via decoder 62 is operative to generate - the modified internal decoder signal and to provide the 3x to the deinterleaver 64. The deinterleaver is shown responsive to the modified internal decoder signal 63 and is operative to generate a deinterleaved signal 65 while the person is provided to the modified external decoder 66. The modified external damper (4) is shown responsive to the interlaced signal 65' and is operative to generate a set split signal 67, which in this example is the same as the signal 21. In the case where the decoder is located within the first sub-decoder 26, there will be no delayed set split 201032484 signal 71' while a legacy internal decoder is located at the last 6 of the final sub-decoder 46. In the case of the gate, the signal 67 is the seek signal 45 and a conventional external decoder can be utilized. Given that the known symbols have been removed based on the set split signal based on considerations, the modified internal decoder 62 can be utilized to decode the transmitted day code before being received from the antenna. In an exemplary embodiment of the present invention utilizing the ATSC A/53 standard, the internal digital system is smashed through the "丄 糸 糸 数码 ' ” and the modified internal unlock code 1 § Partial symbols are eliminated by 12 parallel grid decoder numbers, each performing v. Since (4) the splitting signal each performs a Vl_ algorithm to determine the optimal symbol sequence. The deinterleaver 64 is a conventional solution. An interleaver that can be used to deinterlace the received signal or to remove interleaving effects that have been introduced into the device prior to its transmission. In the exemplary embodiment of the present invention, the deinterleaver 64 is comprised of the following two The components are: a cyclotron deinterleaver, which operates on an 8-bit data bit, and a raster digital deinterleaver, which operates on a 2-bit data symbol.

The modified external material 66 can decode the external digital signal applied to the signal prior to transmission to further generate a set split signal for use by a subsequent modified internal decoder in the present invention - utilizing the ATSC to die / In a specific embodiment of the 53 standard, the modified external decoder is a Reed-Solomon decoder, and the η to ^^ operate to correct errors in the received data bit group, and output one from the The error corrected data bit: the derived set split signal 67. The set split signal Μ is composed of two sub-numbers. The first sub-segment is used to identify the winter batch. #* The billion-number contains the set points for each received symbol. 20 201032484 Cut information 'This is defined in A/53. Χι and χ 2 bits, where there are 4 X1 bits and 4 乂 2 bits for each error correction data byte. The set split information contained in the first sub-signal may or may not be reliable. The second sub-signal contains reliability information including a 1-bit pass/fail signal for each block of 828 symbols, representing a 2-7-bit Reed-Solomon digital block. If an error cannot be detected in the digital block, the Reed-Solomon decoder fails. If the number of errors in the digital block is less than or equal to its error correction capability, the Reed Solomon decoder passes. Conventional internal decoders that conform to the ATSC A/53 standard typically use the Viterbi algorithm to decode the raster digital. In a conventional internal decoder, a coset slicer receives an input in the form of a baseband signal. This baseband signal is typically the output of a signal processing circuit that contains an equalizer. The ATSC A/53 standard, as published on the http://www.atsc.org/stanards/a_53-Part-2-2007.pdf website, defines eight symbol levels for transmission jobs. Figure 6 shows an internal grid encoder using the ATSC A/53 standard to better understand the application of the embodiment of the present invention. That is, as shown in FIG. 6, at each symbol pitch in the transmitter, three bits π (Ζ2, Z1, and Z0) are used to select one of the eight symbols and the two bits are The output of this internal encoder. Further details of the modified internal decoder 62 can be as shown in FIG. The modified internal decoder 62 is shown as including a coset slice $212 coupled to the $select circuit 214, and a path traceback circuit 216 coupled to the circuit 214. The coset slicer 212 is shown as receiving the 21 201032484 internal delay signal 73 and is operable to generate a coset decision with the associated branch measure 211 that is provided as an input to the circuit 214. The circuit 214 is further shown to receive the delayed set split input signal 213 from a previous external delay. Based on these inputs, the branch selection circuit 214 is operative to select the optimum grid tool for each possible grid state and to generate an output signal 217» which is received by the path traceback circuit 216. In a preferred embodiment, a four state raster decoder is utilized to decode the internal digital code defined in ATSC A/53. The branch selection circuit 214 maintains a state transition history that is used by the path traceback circuit 216, and the circuit 216 is operative to generate the modified internal decoder signal 63. The coset slicer 212, i.e., as known to those skilled in the art, can be used to extract the closest cluster level to the received symbol in one or more of the cohesive clusters. The distance(s) from which the (or) transmitted symbol is to the nearest cluster level can be used to calculate the associated branch measure(s). The absolute or square value of the distance is usually used in the measure generation work. The circuit 214 is operative to utilize the branching metrics to determine an optimum branch that is well suited for decoding the received signal for each state of the ◎ grid number, and to store coset decisions for the best branches, while Accumulating the path measure for each state" The modified internal decoder 62 differs from the conventional internal decoder in that the delayed set split input 213 is placed in the branch selection circuit 214. The delayed set split input 213 includes setting split information and setting split reliability information. In the modified internal decoder 62, the 22 201032484 and other associated branch measure 2&quot; coset decisions and the set split input 2i3 are both used to select the best received symbols and associated raster branches for each state, This advantageously improves the selection of the raster branches for the various states. The modified internal decoder provides prior knowledge of some of the input symbols for more frequent selection of the correct raster branch than conventional internal decoders. In conventional internal decoding (4), the selected circuit uses only these co-set decisions with associated branch measures to select the best thumb branch for each state. ❹ 注意到 Note that there may be more than one deinterleaver between the internal and external decoders 62 and 66. In the case where the decoder application of the various embodiments of the present invention receives an A/53 signal, the decoder has two demultiplexer blush byte deinterleaver and a raster digital deinterleaver. In one embodiment of the invention, the set split output of the modified external decoder is stored in the memory in the order in which they are generated. This is different from the different order required for the subsequent modification of the internal decoder input due to the effect of the (equal) deinterleaver. That is, as shown in the subsequent figures and discussed by the discussr address logic, the index of the sequence can be generated so that the modified internal decoder inputs are in the correct order. Table 1 illustrates the ::logical differences between the legacy internal decoder and the modified internal decoder. In the table, "current state" represents the bit 'stored in the delay component of the raster de-worm" and is a binary-marked crying = equal-knowledge information bit" as a previously modified external decoding , 'out' and contain XI and χ2 bits corresponding to the current symbol, and a carry note is expressed as the upper female \ 衣丁 is X2X1. The "set split reliability bit" 23 201032484 is also the output of the same previously modified external decoder and contains a pass/fail bit 70 'This bit represents the Reed-Solomon digital word associated with the currently received symbol. Whether the group was successfully decoded. The "set split reliability bit" is displayed as being set to "a" indicating that "〇" is reliable. "Possible Symbols (Traditional)" lists the possible symbols available for selection in a conventional internal decoder. The "possible symbol (modified)" is a list of possible symbols available for selection in the modified internal decoder. For both conventional and modified internal stockers, the possible sign of the best measure from the coset slicer is selected by the branch selection circuit. In various embodiments of the present invention, the modified internal decoder may advantageously limit the set of possible symbols to reduce the chance of incorrect symbol decision making, thus allowing the modified internal decoder 62 to be compared to a conventional internal The decoder makes a more correct decision. Current status Set split information Bit ραχι) Set split reliability bit Possible symbol (traditional) Possible symbol (modified)

❹ 24 201032484

table

G ^. Further details of this modified 66 are shown in accordance with an embodiment of the present invention. The modified external decoder 66 is shown not to include the Reed-SG1() mGn decoder 218 and the "byte-to-symbol conversion circuit" 22G. Decoder 218, which receives this signal 65, is shown to be connected to circuit 220 and provides an output 219. The Reed s〇i〇m〇n

The 218 operates on a digital block having a fixed number of bytes, wherein the fixed number is equal to 207 in the ATSC A/53 standard. One of these bytes is a data byte (187 in the ATSC A/53 standard) and the rest are added to the data bytes by the Reed-Solomon decoder according to a generator polynomial Colocated byte (疋20 in the ATSC A/53 standard). Assuming that no external information such as a softness measure or a schematic indicator is used in the receiver, a Reed_s〇]〇m〇n decoder can correct the number of half of the parity bits in the digital subgroup. The error (in the ATSC 25 201032484 A/53 private standard is 1〇). If [,, t is the fault of the rule, then the decoding process will be lost. This failure is usually handled by a J π and will be lost at the output of the pass/fail bit available at the ι Reed-So!om〇n decoder. The byte to symbol 220 extracts the settings for each symbol from the output of the error correction conversion circuit eight (4): and for each byte of the error corrected output, the set split information is composed of four XI〆古分; consists of X1 bit 70 and 4 χ 2 bits (optional). Figure 9 shows a detailed progress of the external delay in accordance with the present invention. It should be understood that all of the external delays of the particular embodiment of Figure 3 are shown to be included within the external delay 69 and operate in a similar manner. The external delay 69 of FIG. 9 is similar to any of the ni external delays of FIG. 3, such as the delay of 69 of the external material, which is shown to be delayed by the inclusion-delay memory 68'. The output of the address logic 7 ° the delay memory 68 is displayed in response to the set-point d signal 78, i.e., as indicated by χη. The delayed memory 68 is shown as generating a delayed set split signal 80, i.e., as indicated by Xam. The letter G 78 is identical to any of the signals 31 or 33, and the signal 8 is the same as any of the numbers S or 54 or 21. The external delay 69 is further shown as including an optional round-out multiplexer (mux) 236 that responds to the delayed set split signal 8 and responds to an optional flag 72, the flag It is generated by the address logic 70. The external delay 69 is shown to include the delayed memory 68, which is coupled to receive the set split signal 78, that is, by χη*, the sister 26 201032484 can operate to generate the delayed set split signal 8 Hey. The set split signal 78 is generated by a modified decoder coupled to the external delay 69' as previously described. The delay memory 68 is further shown as an address logic signal 75 generated by the address logic 7 ,, the address logic being shown coupled to the delay via the address logic signal 75 Memory 68. The address logic 7 is further shown to generate an optional flag 72. The flag 72 advantageously indicates that the set split signal corresponding to the currently received symbol processed by the modified internal decoder 62 尚 is not yet available. use. This flag 72 is necessary if the internal decoder memory size is less than the worst case delay of a sub-decoder. When the flag 72 is set, the optional output multiplexer (mux) 236 generates a default set split signal indicating that the sigh split information is not reliable. When the flag 72 is not set, the output multiplexer outputs a set split signal extracted from the memory according to the address logic. The address logic 70 typically produces a sequence of metrics and compensates for operational effects including deinterlacers between internal and external decoders such as ❹, while causing the correct ordering of the split input for subsequent modified internal decoders. And aligned to the delayed symbol inputs. The operation 'writes a sequence of inputs (i.e., sets the split signal 78 to the one shown) to the delay memory 68. The set split signal 78 is delayed by a variable amount of time and then followed by a different order of input to the delayed delta recall 68 (i.e., as determined by the address logic 7) The delay memory 68 is read out. The address logic 7 is operable to align the delayed set split signal 80 to the delayed input signals to facilitate subsequent internal decoder operation. For example, where the external decoder 69 is externally delayed 32 of the particular embodiment of FIG. 3, the address logic % is operative to align the signal 54 to the signal 37. The external delay 69 is shown in Fig. 9 as having a __single-delay line (or component). This may include a plurality of delay members, and may also include a combination of a plurality of smaller delay lines. The typical external delay size for the ysc a/53 application in this exemplary ATSC application is 4 hands-on symbols, = 53 is the Reed_s 〇 1 〇 m 〇 digital block. The atsc a/53 symbol rate is approximately 10.76 MHZ, such that the total delay time is approximately 4 〇 75 ms &lt;) the delay ◎ time can be changed symbol by symbol' and its range is 〇 _ 4.075 ms depending on the address logic. The delay member 68 can be formed by a scratchpad, memory of any time, or any storage logic thereof. According to the features of the present invention, the magnitude of these internal and external delays can be fine tuned to trade off between cost and effectiveness. For example, the size of the external delay 69 can be made sufficiently small that the address logic 70 can sometimes refer to a memory location that has not been previously written by a previously modified external:coder. In other words, this is a future output with reference to the previous J external decoder. In this case, the address logic is configured to cause the flag 72 to be represented when the desired output (i.e., the signal 80) is not available. The flag 72 is used to notify the subsequent internal decoder to indicate that the split information 0 is not available for its current input. When the flag 72 is a follow-up indicating that there is no set split information available for its current input. In the case of an internal decoder, the subsequent internal decoder operates as a conventional internal decoder. When the setting split information is not reliable due to the failure of the external decoding 28 201032484, the setting of the split information may sometimes be 'obtained $ ^ in the variable delay to achieve performance improvement, and there is no such It must be available at all times. Then no. However, as shown in the figure, according to the present invention ‘―. 70 step-by-step details. The address logic 7Q is a ===address logic 222, an output counter 23', and includes an input meter 230, a displacement calculation circuit 224 and an overflow comparator 22^ / The input juice counter 222 is shown coupled to the circuit and produces an output thereof that is subtracted from the output of the displacement calculation circuit 226 that is also shown to be transferred to the circuit. The circuit receives the output of the § decimator 230 as an input. In operation, the circuit 226 calculates a displacement used in the addressing of the external delay memory. The circuit 224 provides the result of its subtraction to the comparator, while the output of the comparator 228 indicates that the result of the subtraction overflow is either at or greater than zero, ie, for the ATSC A/53 ship embodiment The displacement calculation operation performed by the circuit 226 can be described as follows in the following subroutine. In this case, a hypothesis is assumed, that is, the setting of the divided information bits is the width of the remaining bits. It is 'in the body' and is arranged from the maximum valid to the least significant X2X1 bit with respect to the RS decoder output bit group. The subroutine is represented by a note like C code, as is well known in the industry. However, the displacement calculation operation is not limited to a software implementation, and may be derived using alternative f-generated logic as long as the displacements can be generated in the same sequence as produced by the following sub-programs. 29 201032484 off 1 = (out_cnt% 1 2)*4+(out_cnt/12)+(out_cnt/48)*44; off2 = (out_cnt%3 3 12)/828; if ((off2&gt;0) &amp;&amp;;(((out_cnt%828)/12)&lt;(4-off2))) { if((out_cnt% 12)&lt;8) offl+=16; else offl- = 32; } off=43 264* (off 1/208)-82 8 *(offl/4)+(offl%4); For example, assume that the first RS output byte is represented by a binary annotation as R7R6R5R4R3R2R1R0. The contents of the memory locations at shifts 0, 1, 2, and 3 are R7R6, R5R4, R3R2, and R1R0, respectively. The input to the equation counts the output ("〇ut_cnt"), where 〇ut_cnt is zero for the first symbol within a block. The output of the equation is a displacement ("off") relative to the first symbol in a block. Depending on the configuration of the delayed memory, it may be necessary to add the start address to the offset to obtain the address of the split signal to be set. At the same time, if a circular delay buffer is used, it is necessary to perform an index calculation based on the delay buffer size. The input counter 222 continues to track the amount of input stored in the delayed memory. This person can be periodically reset to a 201032484 fixed value during the receiving process. In an exemplary embodiment of the present invention utilizing the ATSC A/53 standard, the input counter 222 is set to a fixed value when the first symbol of a field is processed by the sub-decoder. The fixed value is calculated based on the internal delay magnitude such that the first symbol of the field is aligned to the appropriate set split signal. The output counter 23 maintains the number of symbols generated by the external delay 69. This person can be periodically reset to zero during reception. In an exemplary embodiment of the present invention utilizing the ATSC A/53 standard, the output counter 230 is reset to zero when the first symbol of a field is processed by the decoder. The displacement calculation circuit 226 calculates the address shift necessary to extract the appropriate set split signal corresponding to the current received symbol from the delayed memory. The subtraction circuit 224 subtracts the input count from the displacement. A positive or negative displacement table does not correspond to the currently set symbol. The split signal is not yet available. If the output of the subtraction circuit 224 is greater than or equal to 〇, the overflow comparator 228 sets a flag 72. In an embodiment of the present invention that utilizes the atsc octave standard, when the flag 72 is set, the output multiplexer sets the set partition reliability sub-signal to "丨". This means that the split information is not reliable. Figure 11 shows the modified decoder 60 coupled to the external delay and wherein 3 has one of the N stages of the iterative decoder of the various embodiments of the present invention. The delayed memory 68 is shown as receiving the signal 78' and the modified internal decoder 62 is shown as receiving the signal %. The delayed memory 68 is shown to provide the signal 8() to the modified internal decoder 62. The modified external decoder 66 is shown as producing 31 201032484 to generate the split signal 67, and the specific embodiment of FIG. 1 is any sub-decoder other than the Nth sub-decoder in the iterative decoder. , this signal is provided to the subsequent internal decoder. The external delay 69 of the figure is not shown to be without the optional flag signal and the output multiplexer. Therefore, this indicates that the internal delay size is large enough to compensate for the worst case sub-decoder delay. situation. Figure 12 shows another embodiment in accordance with the present invention. The receiver 9 of the L-processing circuit 92 is 〇, and the circuit receives a Qin from an antenna.

147, and coupled to a modified iterative decoder circuit 94. The stack decoder circuit 94 operates as a diversity combiner. The iterative decoder circuit 不 is an input that combines input from a plurality of ^s (i.e., as shown in FIG. 3) to merge information from the _--the antenna and has different settings for multiple delays. The s signal processing circuit 92 operates in the same manner as the signal processing circuits 48, $ and 52 of Fig. 3, and the &amp;&amp; circuit 94 produces a (four) μ for the modified iterative solution 94 system &amp; baseband signal 93° the modified iterative decoder

Contains such sub-solutions as Γ6 34: 5 and 401, which operate in the same way as (4). The similar elements of the 46-bit and the sub-solver similar to the embodiment of Figure 12 are in different ways: the sub-decoding ϋ 103 is shown to contain the _internal delay in response to the baseband signal 93 and is operational This number 113 to - is also shown as being included in the delayed signal decoder %. The modified decoder 96 is = generating - setting the split signal 1 〇 7 , and this external delay is also shown as incorporating 32 201032484 is within the sub-decoder 103. The external delay 97 is delayed to set the split signal 1 15. The 'sheng=sub-decoder 1〇5 is shown to contain an internal delay %, modify the decoder 99 and an external Delay 9 </ RTI> The internal delay 98 is shown as responsive to the signal 113 and is operable to "reproduce the signal 109 to respond to the signal u ° as a set split". The decoder _ _ J Ren No. 111 to the external delay 91, this is not a result of the generation of a delay of the middle of the eight "ίΜ 1, , © Department of the Departmental 07 signal 117. Should be noted that the delay. 97卩91 each Have the same structure and are in phase with the external delay The same way t operates. Therefore, the set split signal generated by its individual modified decoder is not only delayed, but also aligned to a sequence or signal of a subsequent internal delay. For example, the external delay 97 (four) address logic can make The signal 115 is aligned with the signal! 〇 9. The sub-decoder 4〇1 is shown to contain an internal delay, which is connected to the modified decoder 〇1. The internal delay is shown as ◎ Responding to the internal delay signal 1G9, and operable to generate an internal delay signal 119 for input to the decoder 1〇1. The decoder ι〇ι further responds to the money 117 and is operable to generate The received signal, or the output signal 121. The internal delay signals 113, 1 〇 9 and 119 have a fixed delay with respect to the baseband signal 93. The solid delay of the signal can be zero, thereby decoding from the iteration The internal delay 95 is effectively removed within the circuit. Due to the iterative decoding process, the output signal 121 of Figure 12 can advantageously have the same or less than the output of a conventional single pass decoder. 3 201032484 A small bit error. Due to the new structure used in this embodiment, it can be used to achieve a performance gain compared to the prior art iterative decoder. The body size typically results in lower receiver manufacturing costs. An example of the gain in signal noise ratio and memory capacity will be briefly explained below. In the present invention - the use of ATSC A/53 should (4) an exemplary implementation In the example, the external delay of the receiver 90 can be configured to store only the magic bits as the set split signal. Since there is only one antenna, tuner and signal processing circuit, each sub-decoder input has the same The level of noise. The X2 bit can be reliably decoded at the level of noise that can be tolerated by the iterative decoder as long as the state within the raster decoder is shifted to the correct

Just fine. Since only these ghost bits affect the raster decoder state transition, only those bits need to be stored for use by subsequent sub-decoders. In contrast, when the noise signals in the input of the sub-decoder are not related to each other, that is, when using multiple antennas, such as &amp;, the external delay must be m彳, the power of WW

Depending on the level of noise in the final sub-decoder input, this can be felt much higher than the previous sub-decoders. When compared to a conventional decoder, the 寺 temple signals 121 and 45 can experience a reduced bit error rate at the low noise ratio. Especially in the case of signal 12, compared to the users of the traditional iterative decoder, the lower bit error rate can be obtained by using less memorization, and you can reduce the receiver. Manufacturing costs. An example of the gain in signal noise t i ^ noise ratio and memory capacity will be briefly explained below. 34 201032484 The receiver 90 is shown as having only one input from one antenna instead of the N antenna inputs received by the receiver 20. Therefore, the receiver 90 is simplified relative to the receiver 2. The receiver 9A typically has a lower cost than the receiver 20 because the receiver 2 requires multiple antennas, tuners, and signal processing circuits, but the receiver 90 only needs one of them. At the same time, the external delay memory requirement can be reduced, i.e., as previously described for the exemplary ATSC A/53 application. However, the receiver 20 achieves better results in terms of bit error rate, especially when the noise at the input of each antenna is unrelated to noise at other antenna inputs. In the embodiment of Figure 12, a single signal processing circuit 92 is used, and its output is differentiated by the magnitude of the input to the plurality of decoders, i.e., by the sub-decoders 103, 1 and 5, and The internal delay decision of 4〇1 is delayed. In Figure 12, there are N sub-decoders and thus there are N one-part delays. Those skilled in the art will also appreciate that, in the present invention, the internal delays 95, 98, and gamma may be by a combination of a solid delay member, or by a single The fly stalk is self-contained with multiple delay components with delayed output. Each delay component is a combination of a number of smaller delay line circuits. And discuss the m π _ note round system to present an example for showing these changes. It can be appreciated that although each of the receivers 20 and 90 can be used, it is possible to use any number of sub-decodings. If you don't encounter a long time, you can add more cost to the receiver. At the same time, for example, if you set a flute, you will have a decrement result. The gain of the second sub-decoder is less than the add-on. - Second sub-decode 35 201032484 gain. Figure 13 shows a 'three-stage receiver 208' having phases N-1, N and N+1 in accordance with an embodiment of the present invention. Noted in Figure 13

The first external delay includes address logic 116 and delay memory 118, and is not shown as part of the sub-decoder 102, while the second external delay includes address logic 152 and delay memory 128' and Shown as part of the sub-decoder 104. This is an alternative embodiment of the receiver 90 wherein the external delays 32 and 40 are depicted as part of the sub-decoders 26 and 34, respectively. Alternative embodiments may be considered in which the address logic 丨丨6 and the delay memory 丨丨8 are part of the sub-decoder 1 并且, and the address logic 152 and the delay memory 128 Is part of the sub-decoder 102. The receiver 208 is similar to the receiver 90&apos; and displays further details of the modified decoder and external delays. The receiver 208 is shown to include a sub-decoder N·100, a sub-decoder N 1〇2, and a sub-decoder N+丨1〇4 in its three stages. The scorpion decoder N-1 is shown to include a modified internal decoder 110, a deinterleaver 112, and a modified external decoder 114, which collectively comprise a modified decoder Ν_1β. The modified internal decoder 1丨〇 operable to generate an internal decoder signal 3G7 by which the deinterleaver

Π2 received. The deinterleaver 112 is operative to generate a deinterleaved 3'9' which is received by the modified external decoder 114. The subcoder N 102 is shown to include an internal delay, address logic 116, delay memory 118, a modified internal descrambler interleaver 122, and a modified external decoder 124. The address logic &quot;b 36 201032484 operates to generate an address logic signal 308 that is received by the delayed memory 118. The delay memory 118 is operative to generate a delayed set split signal 312 that is received by the modified internal decoder 151. The modified internal decoder 15 and the modified external decoder 124 collectively form a modified decoder N, and the address logic 116 and the delay memory 118 collectively comprise the external delay N. The modified inner decoder 15 1 is operative to generate a modified internal decoder signal 314 that is received by the deinterleaver 22 and operates on the deinterleaver 22 to generate a deinterleaver signal 316, this signal is received by the modified external decoder 124. The sub-decoder 1 〇 4 is shown to include an internal delay 108, address logic 152, a delay memory 128, a modified internal decoder 153, a deinterleaver 132, and a modified external decoder 134. The address logic 152 is operative to generate an address logic signal 32, which is received by the delay memory 128, "The Modified Internal Decoder 153, the Deinterleaver 132, and the Modified External Decoder" 34 is collectively configured to modify decoder N+1, and the address logic 152 and the delay memory 128 collectively comprise the external delay N+1. The modified internal decoder 153 is operative to generate a modified internal decoder signal 324 that is received by the deinterleaver 132. The deinterleaver 132 is operative to generate a deinterleaver signal 326 that is received by the modified external decoder 134. The modified decoder is similar to the modified decoder 6 and can operate in the same manner. Similarly, the modified decoders N &amp; n+i are similar to the modified decoder 6 〇 β. The external delays N+i are similar to the internal delay of the external delay 69β. 6 and ι〇8 each 37 201032484 is similar to the internal delay of 28 or 36 or 42 or 95 or 98 or 400

The specific embodiment of FIG. 13 differs in that the signal is from a single signal processing circuit, and the circuit is coupled to the internal delay 106 of the sub-decoder N 102 and the sub-decoder N1. The internal decoder 110 is modified. It is noted that the internal delay % can be removed from FIG. 12 to obtain a similar configuration. The internal delay 1 〇 6 generates an internal delay signal 310 coupled to the interior of the sub-decoder N+1. The delay is 1〇8 and is coupled to the modified internal decoder 151 of the sub-decoder N 102. The modified external decoder 114 of the sub-decoder N-1 is the set split signal 21〇, which is coupled to the delay memory 118 of the sub-decoder N 1〇2.

The modified external decoder 124 generates a set split signal 318 coupled to the delay memory 128 of the sub-decoder N+1 104. The modified external decoder 134 of the sub-decoder N+1 104 generates the output signal 328, which is the signal sought to be decoded. By the various stages of the receiver 2〇8, generated by the various stages Setting the split signal will contain fewer errors than the previous stage. Therefore, the signal noise ratio required to achieve a desired bit error rate will be lower for each additional stage. The sub-decoders N 1 〇 2 and N +1 104 are shown to contain the same structure as the modified decoder 60, although the sub-decoder N1 does not contain internal and external delays. Figure 14 shows a receiver 120 in accordance with another embodiment of the present invention. The receiver 12A includes a signal processing circuit 154 responsive to the signal from an antenna and further comprising an iterative decoder 155 in the same manner as the receiver 9〇, except for the receiver 12 ( The iterative numerator 38 201032484 i 5 5 contains an internal delay i 2 6 which generates internal delay signals 181, 183 and 185 for the modified decoders 157, 158 and 159, respectively. It is noted that the internal delay signal 181 can have a zero delay relative to the baseband signal output of the signal processing. The modified decoders 157, 158, and 159 are similar to the decoders %, 99, and ι, respectively, and the external delays 130 and 156 are similar to the external delays 91 91, respectively. The connectivity between the modified decoder and the external delay in the iterative decoder 155 is similar to the corresponding connectivity of the iterative decoder 94. The decode H 159 is operative to generate the output (four) 138, which is the signal sought for decoding. Figure 15 shows a receiver 140 in accordance with yet another embodiment of the present invention. The receiver 140 includes a signal processing circuit 142 that responds to a signal from the antenna and further includes an iterative decoder 143' in the same manner as the receiver 120 except the receiver 14 The iterative decoder 143 contains an external delay 146. For example, all of the external delays 13 〇 and 156 of the iterative decoder 155 are combined into an external delay 146 for the internal delay! The 44 series is shown coupled to the decoders 1, 1% and 159. If the delay size is designed to be smaller than the worst case scenario: delay: causing sometimes unavailable segmentation information from the immediately adjacent sub-decoder is obtained, ie, as shown in FIG. 15(4) - the single-external delay may be advantageous. Another advantage of the single external delay architecture is that the sub-decoding 11 can utilize any of the previous sub-decoders (rather than only from the immediately preceding sub-decoder) to split the information. The segmentation information generated by the encoder is reliably set, and the subsequent sub-decoder does not need to generate the segmentation information again. The subsequent sub-decoder only needs to generate the set splitting information when the previous sub-decoder sets the split output to be unreliable. This reduces the amount of RS decoder operation necessary, thus reducing overall implementation complexity. It is noted that the same advantages can be achieved in the receiver 90 by fusing each external delay to all subsequent sub-decoders rather than just the immediately subsequent sub-decoder. In general, receivers 90, 120, and 140 have equivalent functionality and achieve the same performance gains. The choice of which memory architecture to use is often based on design considerations beyond the scope of the present invention. Figure 16 shows a specific embodiment of the external delay of the modified decoder of the single antenna embodiment of the present invention for the exemplary ATSc A/53 application. In more detail, the MEM 1 160 system is configured to store N

The Reed-Solomon decodes the X1 bits of the operation, and MEM2 162 is configured to store the pass/fail representation of the N Reed-Solomon decoding operations (performed by the modified external decoder). That is, as shown, the size of the MEM1 160 is 828*N bits, and the size of the MEM2 162 is N bits. The MEM1 160 and MEM2 162 can be implemented at different address displacements within a single memory component. The memory structure of Figure 16 is for illustrative purposes only. Those skilled in the art will recognize that alternative memory configurations do exist and are within the scope of the present invention. In an alternative configuration, the pass/fail bit within the MEM2 can be copied for each X1 bit within the MEM1. This increases the bit width of the MEM 1 while increasing the total memory size to 828*N*2 bits. Figure 17 shows a flow diagram illustrating a specific embodiment of the steps performed by the address logic to read the set split signal for use by the modified internal solution. These steps perform the function of modifying the raster decoder. The program indicated by &## 17 can be used to calculate the displacement described above with reference to the displacement calculation circuit 226. Meanwhile, it is assumed here that the structure is shown in Fig. 16, and the set division signal is stored in ΜΕΜ1, and the set division reliability signal is stored in μεμ2. The program shown in the flow chart of Fig. 17 is executed once for each input to the raster decoder (internal decoder), and generates a corresponding set split signal in the delayed memory (ΜΕΜ_ address. The program description The effect of the traditional byte decoder and the raster digital interleaver in Α/53. In this procedure, the first step 172 is to check whether the current raster decoder input is a field. The first one, as defined in the ATSC Α/53 standard, is then initialized to 〇 at step 174 with the internal counters m〇D52, MOD12 and MOD4, and the raster index offset TRE. At the same time, the index value PTR1 is set to an initial value p, which is selected such that the set split signal at the address p can be aligned to the first raster decoder input of the @bit. After step 174 Or if the decision at step 172 is negative, then step 188 checks if the current raster decoder input is the first of the segments, as defined by the ATSC A/53 standard. If so, then at step 190 m〇D4 is better than 〇. If m If D4 is not equal to 〇, then TRE is set to 4 in step 192. After step 192, or if M0D4 is not equal to 〇 in step 190, or if the target symbol is not the first one of the segments as determined in step 188 Then, in step 丨76, the index value pTR is calculated according to functions such as MOD52, MOD12, TRE, PTR1, and integer memory size (MEM_SIZE). Note that the modulus 201032484 operator "%" is used to indicate The remainder after division of the two operands, as commonly used in the industry, "Secondly, at step 178, the value M 〇 D12 is updated for use in the next raster decoder input spacing. In step 18, If MOD12 is equal to 〇, if M0D12 is equal to 〇, then the value of MOD4 is updated in step ι82. After step 182, if it is indeed taken, MOD4 is compared to 〇 in step 184. If M0D4 is equal to 〇, then The values of MOD 52, PTR 1 and TRE are updated in step 186. After step 186, or if MOD 12 is not 〇 in step 180, or if m 〇 D4 is not 〇 in step 184, the input to a raster decoder is reached. The end step of the program ❿ 194 ° in MEM1 The set split signal at the address PTR is input to the modified raster decoder for cluster setting splitting. In addition, the address of the split reliability signal in MEM2 can be set as follows (flooMPTR/QOTM)) It is calculated that the fl〇〇r() function returns the nearest integer that is less than or equal to its operand. Meanwhile, if the memory size is set to be smaller than the full interleaver depth, the pTR must be verified to ensure that the person does not point to an external decoder that has not been modified by the previous modification (ie, substantially modified) The Reed-Solomon decoder) generates a future set split signal. If the PTR does point to a future set split signal, a default set split signal is output to the raster decoder, and the set split reliability signal is set to indicate that the set split signal is unreliable. Table 2 shows the simulated performance results for various embodiments of the present invention, wherein the delay memory 68 is of sufficient size to handle the worst case sub-decoder delay such that the address logic 70 never refers to the future external decoder 42. 201032484 output. For the purposes of this example, a simple "additive white Gaussian noise (AWGN)" channel model is used. Uncorrelated sources of noise are used for each receive antenna. The data is encoded according to ATSC A/53 and the output is monitored by 2,500 stops (approximately equal to 1 minute in actual time). The SNR reported in Table 2 is represented by the highest level of noise with no bit errors in the 2500 fields, and can be up to 〇·1 dB. The first course is the reference value, which represents a The performance of previous technology receivers. The gain wales of Table 2 refer to this value. 〇Receiving antenna number Sigma path number SNR(dB) Benefit (dB) 1 1 14.7 0.0 1 2 14.2 0.5 1 3 13.9 0.8 1 4 13.7 1.0 2 2 14.0 0.7 3 3 13.7 1.0 4 4 13.5 1.2 5 5 13.4 1.3 2 〇 In the case where the prior art blocks are selected for diversity, using 2 antennas and 2 decoder paths, the result of the Snr is approximately 14 3 dB with a gain of 0.4 dB. This is 14.0 dB and the gain is 〇.7 dB compared to the 2 antennas and 2 decoder paths in Table 2. The diversity and sub-decoding decoder of the present invention is superior to the prior art block-selected diversity set. To illustrate the trade-off between delay size and performance, consider the case of one receive antenna and two decoder paths 'with various delay sizes between the decoders'. The results are shown in Table 3 below. This situation is based on the atsc 43 201032484 A/53 signal and a model of the m ^ f channel. In Table 3, the delay size is normalized, so that this 1.0 represents the maximum available delay, where the t ^ ownership cutoff output from the first external decoder can be used for timely use. The second internal decoder is used. The delay size 〇〇 represents a prior art case with only one decoder path. Delay size SNRidKl gain _ 0.00 -----^ 7 —_14.7 0.0 0.07 _14.7 0.0 0.15 —_14.7 0.0 0.17 _14.7 0.0 0.18 ___14.7 0.0 0.20 14.6 0.1 0.22 _ 14.6 0.1 0.26 14.5 0.2 0.28 14.5 0.2 0.30 14.4 0.3 0.38 14.4 0.3 0.39 14.4 03 0.41 14.4 0.3 0.43 14.3 0.4 0.45 14.3 0.4 0.53 14.3 0.4 0.61 14.3 0.4 0.62 14.3 0.4 0.64 14.3 0.4 0.66 14.2 0.5 0.70 14.2 0.5 0.78 14.2 0.5 0.85 14.2 0.5 0.93 14.2 0.5 1.0 14.2 0.5 table 3

That is, as can be seen from Table 3, only 66% of the maximum available memory Zhaoda 44 201032484 is small (that is, the size necessary to ensure that the split information is always available), that is, it can be obtained by two decoders. Up to .5 dB gain. Thus, the prior art sub-set solver of the present invention can be implemented at a lower cost than prior art techniques that cannot fine-tune the delay between iterations. The present invention has been described in terms of a particular embodiment, and it is to be understood that modifications and modifications will be apparent to those skilled in the art. Therefore, it is intended that the scope of the patent application should be interpreted as covering all such alternatives and modifications within the true spirit and scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows a prior art receiver 1A. FIG. 2 shows a signal processing circuit 22. Figure 3 shows a receiver 2 in accordance with an embodiment of the present invention. Figure 4 shows a timing diagram 'which illustrates how the Reed_s〇i〇m〇n depleted output is associated with the set split signal. Figure 5 shows further details of each of the N modified decoders in accordance with an embodiment of the present invention. Figure 6 shows Figure 6.8 of the ATSC A/53 standard, whereby the application of the specific embodiment of the present invention is better understood. FIG. 7 shows further details of the modified internal decoder 62. Figure 8 shows further details of the modified external decoder 66 in accordance with an embodiment of the present invention. Figure 9 shows further details of an external delay in accordance with an embodiment of the present invention. 45 201032484 FIG. 4 shows further details of the address logic 70 in accordance with an embodiment of the present invention. Figure 11 shows a modified decoder 60 spliced to the external delay 69, which contains one of the N stages of an iterative decoder of various embodiments of the invention. 12 shows a receiver 90 including a signal processing circuit 92 which, in accordance with another embodiment of the present invention, receives an input 147 from an antenna and is coupled to a modified iterative decoder 94. Figure 13 shows a three-phase receiver 208 containing stages ❹ N·1, N and N+1 in accordance with one embodiment of the present invention. Figure 4 shows a receiver 120 in accordance with another embodiment of the present invention. Figure 15 shows a reception 140 in accordance with yet another embodiment of the present invention. . Figure 16 shows a modified embodiment of a modified decoder of a single-signal processing circuit embodiment of the present invention for the exemplary aTSc A/53 application. 〇 - Figure 17 shows a flow chart illustrating the steps performed by the address logic 7() to pass the modified internal decoding to the read φ v entry. &lt; Description of [Main Element Symbol] 10 Decoder 12 Internal Decoder 46 201032484 14 Deinterleaver 16 External Decoder 20 Receiver 21 Delayed Set Split Signal 22 Signal Processing Circuit 23 Baseband Signal 24 Iterative Decoder Circuit 26 Subdecoder 28 Internal Delay 29 Internal Delay Signal 30 Decoder 31 Set Split Signal 32 External Delay 33 Set Split Signal 34 Sub Decoder 35 Baseband Signal 36 Internal Delay 37 Internal Delay Signal 38 Decoder 40 External Delay 41 Baseband Signal 42 Internal Delay 43 Internal Delay Signal 44 Decoder 47 201032484 45 Output Signal 46 Sub Decoder 48 First Signal Processing Circuit 50 Second Signal Processing Circuit 52 Nth Signal Processing Circuit 54 Delayed Set Split Signal 60 Modified Decoder 62 Modified Internal Decoder 63 Modified Internal Decoder Signal ® 64 Deinterleaver 65 Deinterleaved Signal 66 Modified External Decoder 67 Set Split Signal 68 Delay Memory 69 External Delay 70 Address Logic 71 Delayed Set Split Signal ® 72 Flag Standard 73 Internal Delay Signal 75 Address Logic Signal 7 6, 78, 80 Signal 90 Receiver 91 External Delay 92 Signal Processing Circuit 48 201032484 93 Baseband Signal 94 Modified Iterative Decoder Circuit 95 Internal Delay 96 Modified Decoder 97 External Delay 98 Internal Delay 99 Modified Decoder 100 Decoder 101 Decoder 102, 103, 104, 105 Subdecoder 106 Internal Delay 107 Set Split Signal 108 Internal Delay 109 Internal Delay Signal 1 10 Modified Internal Decoder 111 Set Split Signal 112 Deinterleaver 113 Internal Delay Signal 114 Modified External Decoder I 15 Set Split Signal 116 Address Logic 11 7 Delayed Set Split Signal II 8 Delay Memory 119 Internal Delay Signal 49 201032484 120 Receiver 121 Output Signal 122 Deinterleaver 124 Modified External Decoder 126 Internal Delay 128 Delay Memory 130 External Delay 132 Deinterleaver 134 Modified External Decoder 138 Output Signal 140 Receiver 142 Signal Processing Circuit 143 Iteration Decoder 144 Internal Delay 146 External Delay 147 Input 148, 150 Decoder® 1 5 1 modified internal decoder 152 address logic 153 modified internal decoder 154 signal Processing Circuit 155 Iterative Decoder 1 5 6 External Delay 157 ' 158 ' 159 Modified Decoder 50 201032484 κ 160 Memory (MEM 1) 162 Memory (MEM2) 172-194 Each step 181 of the flowchart in FIG. 183, 185 internal delay signal 200 radio frequency (RF) input 201 tuner 202 intermediate frequency (IF) signal 203 analog to digital (A / D) converter © 204 baseband mixer 205 timing recovery circuit 206 carrier recovery circuit 207 adaptability Equalizer 208 Receiver 210 Set Split Signal 2 11 Associate Branch Measure 2 1 2 Coset Slicer 213 Delayed Set Split Input Signal 214 Branch Select Circuit 216 Path Back Circuit 217 Output Signal 218 Reed-Solomon Decoder 219 Output 220-bit to symbol conversion circuit 222 input counter 51 201032484 224 subtraction circuit 226 displacement calculation circuit 228 comparator 230 output counter 236 output multiplexer (mux) 300 signal 301 signal RS_fail 302 signal RS_out[7:0] 303 signal syml

304 signal symO 305 signal set_part 306 signal set_part_rel 307 internal decoder signal 308 address logic signal 309 deinterleaved signal 3 10 internal delay signal 3 12 delayed set split signal 3 14 modified internal decoder signal 3 16 deinterleaver Signal 3 1 8 Set Split Signal 320 Address Logic Signal 3 24 Modified Internal Decoder Signal 326 Deinterleaver Signal 328 Output Signal 201032484 400 Internal Delay 401 Sub Decoder

53

Claims (1)

201032484 VII. Patent application scope: 1. A foster decoder circuit operable to provide a round-out signal in response to a received signal, comprising: N sub-decoders of the sub-decoders, N- Each of the respondents responds to a baseband signal from one of the signal processing circuits, μ is an integer 'where Μ ranges from 1 to Ν-1; and Ν is an integer, the N-1 sub-decodes Each of the devices includes an internal delay 'this is in response to a baseband signal provided by a corresponding signal processing circuit' and is operable to generate an internal delayed signal, upon modification of the decoder, which is responsive to the internal delayed signal And operable to generate a set split signal, the π疋 split signal of the N modified decoders has less than a second internal delay than the set split signal before I, the baseband provided by the circuit a signal, a delayed signal, which is responsive to being processed by the second signal and operable to provide a third internal ...-the third modified decoder, the one responding to the first internal delay signal and The set split signal & is operable to provide an - output signal, wherein the error in the split (4) of the set is corrected to reduce the probability of error in the output signal. As described in claim 1, the Ν-1 (five) sub-decoder $ step includes an external delay, which is set to: split the signal and operate to generate a delayed setting The k number is used by a subsequent sub-decoder. 54 201032484 3' The iterative decoder circuit of claim 1, wherein the N sub-decoders are equal to the M signal processing circuits. 4. The iterative decoder circuit as described in claim 1, wherein the N sub-resolutions are less than "M (four) processing circuits., 5. The stack as described in claim 4 A decoder circuit in which Μ is equal to 1. '^6' is an iterative decoder circuit as described in claim 1, wherein each of the sub-decoders includes a modified internal decoder, which is responsive to The external delay and the delay of the internal delay signal set the split signal and are operable to generate a modified internal decoder signal, each of the sub-decoders further comprising a deinterleaver in response to the modified, portion decoder Signaling and operable to generate a deinterleaved signal, each of the sub-decoders further comprising a modified external decoder that is to be deinterleaved and operable to generate the set split signal The last of the sub-decoders includes a conventional externally solved Q-coder that operates to generate the signal sought to be decoded. 7. As described in claim 6 of the patent scope An iterative decoder circuit, wherein the modified internal decoder comprises: a coset slicer responsive to a received symbol and operable to detect that one or more escorts of the transport cluster are closest to the The symbols of the received symbols are simultaneously operable to generate coset decisions and associated branch measures, and the 'branch selection circuit' responds to the coset decisions and branch measures and is responsive to a set split input signal while operating To select 55 201032484 for the best branch of each state of the - raster number, and store the coset for the best branch, and respond to accumulate the path measure for each state; and the path backtracking circuit 'this responds The stored coset decisions and the path measure 'and operate to generate a branch circuit comparison circuit signal representing the best received symbol at the delay from the received symbol. 8_, wherein the modified external decoder comprises a Reed_SG1Gmcm decoder and a byte-to-symbol conversion circuit consuming the Reed-Solomon decoder, as described in claim 7 The Reed-S〇lomon decoder is responsive to a deinterleaver signal and is operative to generate an error correction round trip, providing a subsequent external delay k-bit tuple to the symbol conversion circuit, the byte to symbol conversion The circuitry is responsive to the error corrected output and is operative to extract set split information for each symbol from the error corrected output. ^9. The iterative decoder circuit of claim 8 of the patent scope, wherein The Reed-Solemn decoder is operative to receive a deinterleaver signal comprising a fixed number of bytes of the digital block, and wherein the portion of the bits is a data byte and the remaining The byte is a parity bit that is placed in the data byte by the Reed-S〇l〇m〇n decoder according to a generator polynomial. 10. The iterative decoder circuit of claim 2, wherein the at least one external delay comprises a delay memory coupled to a sub-decoder, the person responding to a set split signal from the sub-decoder And operable to generate a delayed set split signal 56 for a subsequent sub-decoder, wherein the external delay further comprises at least one address logic operable to generate an address logic signal for providing to the delayed memory And the address logic is operative to align the set split signal to an internal delay signal. 11. The iterative decoder circuit of claim 10, wherein the address logic is operative to generate a flag indicating that the current received symbol is processed corresponding to a sub-decoder that is not yet available. Set the split signal. 12. The iterative decoder circuit of claim 11, further comprising an output multiplexer responsive to the delayed setting of the split signal and the flag, and operable to generate a default Setting a split signal, the signal indicating that the set split information is unreliable, wherein when the flag is set, the output multiplexer generates a default set split signal indicating that the set split information is unreliable, and when the flag is When not set, the output multiplexer outputs the set split signal according to the address logic. 13. An iterative decoder circuit operable to provide an output signal in response to a received signal comprising:卩 delay, which is responsive to a baseband signal provided by a signal processing circuit and operable to generate N internal delayed signals, N modified decoders, each responding to the phase of the N internally delayed signals Corresponding, and operable to generate a set split signal, the portion of the N modified decoders having fewer offsets than the previously set split signal, wherein the previously modified decoded set split The signal is provided as a input to the 57 201032484 pair-subsequent modified decoder, and wherein the overall error probability is reduced by correcting errors in the partial set split signal. 14. The iterative decoder circuit of claim 13, wherein the further step comprises N external delays 'each external delay is responsive to the n corresponding 5 cut signals - the corresponding one' and is operable The delay is set to the cut signal and is applied by a subsequent modified decoder. 15. The iterative decoder circuit of claim 13, further comprising an external delay responsive to the N set split signals and operable to generate a __delayed set sub-number Used by the subsequent modified decoder. 16. The iterative decoder circuit of claim 15, wherein the N sub-decoders each comprise a modified internal decoder responsive to the delayed set split signal from the external delay and The internal delay signal is operative to generate a modified internal decoder signal. Each of the sub-decoders further includes a deinterleaver responsive to the modified internal decoder signal and operable to generate a Each of the deinterleaved/number It sub-decoders further includes a modified external decoding buffer responsive to the deinterleaved signal and operable to generate the set split signal while the last of the N sub-decoders One includes - a traditional external decoding H, which can operate as a signal that the line seeks to decode. 17. An iterative decoder circuit, comprising: means for receiving a baseband signal; N sub-decoders, each comprising means for generating an internal delay signal 58 201032484 in response to the received baseband signal Means for receiving the internal delay signal and generating a set split signal; ^ means for receiving the baseband signal and generating an Nth internal delay signal; ° for receiving the Nth internal delay signal, and Means for generating an output signal, wherein the error probability in the set split signal of each sub-decoder is reduced in at least a portion of the set split signals. 18. The iterative decoder circuit of claim 17, wherein the sub-decoder is operable to reduce an error probability within the decoded signal, the sub-decoder further comprising: for receiving the set split signal And generating a device that is delayed by the split signal and used by a subsequent sub-decoder. 19. A method of decoding a received signal in an iterative manner, comprising: a. receiving at least one baseband signal from at least one signal processing circuit, the baseband signal containing noise; b. generating at least one internal delay from the received baseband signal Signal c. generates a set split signal from an internal delay signal; d. generates a delayed split signal from the set split signal. e_ generates a set split signal from the internal delay signal and a delayed set split signal; f. The set split signal is generated by delay setting the split signal g_ repeating step e. to step f. N-2 times, thereby reducing the delayed set split signal (4) error probability each time step e 59 201032484 to f. is performed. ; h· self-internal delay signal and N] delayed set split signal to generate the signal sought to be decoded. The method of decoding a received signal in an iterative manner as described in the _4 patent scope ,19, wherein the step e• comprises: a. receiving the delayed set split signal from the self-external delay, and from the internal delay Receiving the internal delay signal; b) generating a modified internal decoder signal from the delayed set split signal and the internal delay signal; c. generating from the modified internal decoder signal - deinterleaving and ... d. The de-parent error signal generates a set split signal and passes the set split signal to an external delay. It is determined that it is a 4th generation decoding ^, which can operate in response to the received signal and k to provide an output signal, which includes: the US I decoder is provided by the responder - the signal processing circuit Carrying a signal 'and operable to generate N internal delay signals, N peaks to change the decoder, each (4) corresponding to one of the n internal delay k numbers, and a portion of the N settings Dividing the split signal, there are fewer errors, the 4th is compared to the previous setting of the split signal with a delay. This is in response to the N modified modified solver cut signals, so that the signals are lightly connected to the N modified decoders - subsequent modified decoders. The method of claim 21, wherein the ones of the sub-decoders each comprise a modified internal decoder responsive to the delayed set split signal from the external delay and The internal and operable to generate a modified internal decoder signal, each of which includes a __ deinterleaver, responsive to the modified internal decoder, and operable to generate a deinterleaved The signal 'these sub-solvers each pushes the first right test to include a modified external decoder, Ο this responds to the de-intercept s signal 'and can operate to generate the set split signal' while The last of the AA sub-decoders includes a conventional external decoder that operates to produce the signal sought to be decoded. Eight, the pattern: (such as the next page) ❹ 61