201032233201032233
Fy/Ul^4 29437twf.doc/n 六、發明說明： 【發明所屬之技術領域】 本發明是有’-種記憶體震置的操作方法，且特別 是有關於一種快閃記憶體的操作方洼^ 【先前技術】 快閃記憶體具有可多次進行資料之存入、讀取、抹除 藝 _作’且存人之㈣在_後也不會消失㈣點，故成 為個人電腦、可攜式《、叹數仙機⑽子設備所廣 泛採用的-種非揮發性記憶體元件。然而，快閃記憶體在 使用-段時間後，會有-些位元發生錯誤，進而造成資料 的存取錯誤。針對上述情況，先前技術一般會使用錯誤校 正碼(Error Correction Code)來進行錯誤校正。 圖1A與圖1B分別為先前技術利用錯誤校正碼來程式 化與讀取快閃記憶體的方法流程圖。如圖1A所示的，在 程式化快閃圮憶體的過程中，先前技術在將所接收到的使 用者資料存入暫存器之後(步驟S111與S112)，即依據使 用者資料來產生錯誤校正碼(步驟SU3)，並將使用者資料 與錯誤校正碼同時寫入快閃記憶體(步驟sn4)。藉此，如 圖1B所示’在讀取快閃記憶體的過程中，先前技術在將 所讀取到的錯誤校正碼以及讀取資料存入暫存器之後(步 驟S121與S122) ’即可利用錯誤校正碼來校正讀取資料’ 並進而取得使用者資料(步驟S123)。藉著，先前技術將可 暫存並輸出使用者資料(步驟S124與S125)。 3 201032233 ry /υι/^ z9437tw£doc/n 值得注意的是，對於多階記憶胞(Multi Level Cell，以 下簡稱MLC)快閃記憶體而言’由於其是透過多個不同級 別的臨界電壓來§己錄位元的資訊，因此如圖2所示，jy[Lc 快閃記憶體往往會因為臨界電壓VT的重疊(overiap)分佈 210，而造成讀取準位RD無法辨別位元的資訊。此外，記 憶胞的過度程式化（over-program)以及電荷損失(charge loss)是導致臨限電壓偏移的主因，且過度程式化是發生在 使用者資料寫入至快閃記憶體的過程中，而電荷損失則是 ® 隨著記憶胞的循環操作而不斷地累加。 對於先則技術而言，其只是利用在寫入使用者資料之 如所產生的單一錯誤校正碼來進行錯誤校正。因此，對於 使用者資料在寫入的過程中因過度程式化所產生的錯誤， 或是使用者資料在寫入後因電荷損失所產生的錯誤，先前 技術必須不斷地提高錯誤校正碼的可更正位元數才能完成 錯誤校正。然而，隨著錯誤校正碼之可更正位元數的提高， 先前技術勢必要增加硬體設施來支援複雜且龐大之錯誤校 φ 正碼的演算。 【發明内容】 二本發明提供一種記憶體裝置的操作方法，除了有助於 »己隐體裝置之更正能力的提升，更有助於降低記憶體裝置 之硬體設施的複雜度。 本發明提供-種記憶體裝置的操作方法，可以提升記 憶體裝置之更正能力。 4 201032233 ^70124 29437twf.doc/n 本發明提供一種記憶體裝置，具有較佳的更正能力。 本發明提出一種記憶體裝置的操作方法，包括下列步 驟。在控制記憶體裝置的過程中，根據一使用者資料產生 一第一錯誤校正碼。接著，將使用者資料寫入至記憶體裝 置。之後，將讀取記憶體裝置中的使用者資料，並根據所 讀取到的使用者資料產生一第二錯誤校正碼。最後，將第 一與第二錯誤校正碼寫入至記憶體裝置。 另^度來看，本發明另提出—種記憶體裝置的操 作方法，其中所述記憶體裝置贿有一第一與一第二錯誤 校正碼，且所述記憶體裝置的操作方法包括下列步驟二 ==置中，—錯誤校正碼、第二錯誤校正碼以； 以^得二第二錯誤校正碼校正讀取資料， 以獲付-暫時資料；以及，利 貝付 資料，以獲得一使用者資料。 a、父碼校正暫時 ❹ 在本發明之一實施例中，上述 法更包括：將°己隐體裝置的操作方 儲在/叙六 貧科館存至一暫存器’·以暫時資料㈣ 存器^暫時資料；以及，輸出使用更新儲存在暫 本發明又提出—^ 誤校正電路以及—操包括一記憶體、-錯 憶體。操作電路用以致利:正=電路電性連接至記 憶體的-使用者資二吏== 根據尚未寫入至記 使錯誤校正電路根據來自記憶^錯t正碼，並用以致 —錯誤校正碼。 思、。買取資料而產生一第 5 201032233 ry/υι^ z9437twf.doc/n 基，上述’本發明是在使用者資料存人記憶體裝置之 月j ”之4 ’二別產生第—與第二錯誤校正碼。藉此，本發 利用第—與第—錯誤校正碼對使用者資料進行階段 0的校正，進而致使本翻可以_較低可更正位元數的 ί一與第二錯誤校正竭，即可達到良好的更正能力。換而 «之與先刚技術相較之下’本發縣可降低硬體設施的 複雜度。Fy/Ul^4 29437twf.doc/n VI. Description of the Invention: [Technical Field of the Invention] The present invention has a method for operating a memory device, and particularly relates to an operation method of a flash memory.洼^ [Prior Art] Flash memory has the ability to deposit, read, and erase data multiple times. _ and '4' will not disappear after the _, so it becomes a personal computer. A non-volatile memory component widely used in the portable ", sigh number machine (10) sub-device. However, after the flash memory is used for a period of time, there will be some errors in the bits, which may result in data access errors. In view of the above, the prior art generally uses an Error Correction Code to perform error correction. 1A and 1B are flow diagrams of a prior art method of programming and reading flash memory using error correction codes, respectively. As shown in FIG. 1A, in the process of programming the flash memory, the prior art stores the received user data into the temporary memory (steps S111 and S112), that is, according to the user data. The error correction code (step SU3), and the user data and the error correction code are simultaneously written into the flash memory (step sn4). Thereby, as shown in FIG. 1B, in the process of reading the flash memory, the prior art stores the read error correction code and the read data into the temporary memory (steps S121 and S122). The error correction code can be used to correct the read data' and further the user data is obtained (step S123). By the prior art, the user profile can be temporarily stored and outputted (steps S124 and S125). 3 201032233 ry /υι/^ z9437tw£doc/n It is worth noting that for multi-level cell (MLC) flash memory, 'because it is through multiple different levels of threshold voltage § The information of the recorded bits, so as shown in Figure 2, jy [Lc flash memory tends to be due to the overlap VT overlap (overiap) distribution 210, causing the read level RD can not distinguish the bit information. In addition, over-programming of memory cells and charge loss are the main causes of threshold voltage shift, and over-stylization occurs in the process of writing user data to flash memory. And the charge loss is constantly accumulating as the memory cell cycles. For the prior art, it simply uses the single error correction code generated by writing the user data to perform error correction. Therefore, the prior art must constantly improve the error correction code for errors caused by over-stylization of the user data during writing, or errors caused by charge loss after the user data is written. The number of bits can be corrected for errors. However, as the number of correctable bits of the error correction code increases, it is necessary for the prior art to add hardware facilities to support the computation of complex and large erroneous φ positive codes. SUMMARY OF THE INVENTION The present invention provides a method of operating a memory device that, in addition to contributing to the improvement of the correction capability of the hidden device, helps to reduce the complexity of the hardware device of the memory device. The present invention provides a method of operating a memory device that enhances the corrective capabilities of the memory device. 4 201032233 ^70124 29437twf.doc/n The present invention provides a memory device with better correction capabilities. The present invention provides a method of operating a memory device comprising the following steps. In the process of controlling the memory device, a first error correction code is generated based on a user profile. Next, the user data is written to the memory device. Thereafter, the user data in the memory device is read, and a second error correction code is generated based on the read user data. Finally, the first and second error correction codes are written to the memory device. In another aspect, the present invention further provides a method for operating a memory device, wherein the memory device has a first and a second error correction code, and the operation method of the memory device includes the following step two: == centering, - error correction code, second error correction code; correcting the read data with the second error correction code to obtain the temporary data; and, Libe paying the data to obtain a user data. a. Parent code correction temporary ❹ In an embodiment of the present invention, the above method further comprises: storing the operator of the hidden body device in the /Six Poverty Museum to a temporary storage device. The temporary data of the memory is stored; and the output is stored using the update. The present invention further proposes that the error correction circuit and the operation include a memory and a memory. The operating circuit is used to make a profit: positive = circuit is electrically connected to the memory - user 吏 = = according to not yet written to the error correction circuit based on the memory from the error, and used to - error correction code. think,. Buying the data and generating a 5th 201032233 ry/υι^ z9437twf.doc/n base, the above-mentioned 'this invention is in the user's data storage memory device month j ′′ 4 'two generation second and second error correction Therefore, the present invention uses the first-and-first error correction codes to perform phase 0 correction on the user data, thereby causing the current _ _ lower correctable number of bits and the second error correction, that is, A good correction capability can be achieved. In contrast, the county can reduce the complexity of hardware facilities.
為讓本發明之上述特徵和優點能更明顯易懂 ，下文特 舉貝施例，並配合所附圖式作詳細說明如下。 【實施方式】 、圖3繪不為依據本發明—實施例之記憶體裝置的操作 方法流程圖’圖4繪示為依據本發明另一實施例之記憶體 裝置的操作方法流程圖，以下將以圖3為主來說明程式化 β己憶體裝置的餘’並以圖4為主來說明讀取記憶體裝置 麟程。此外’圖3與圖4實施例所述的操作方法可應用 β 纟乡階記舰㈣域财，但其並仙錄定本發明。 請參照圖3，在程式化記憶體裝置的過程中，本實施 例會先如步驟S310所示的，接收一使用者資料，並於步 驟S320，將所接收到的使用者資料儲存在一暫存器中。接 著，如步驟S330所示，根據使用者資料產生一第一錯誤 校正碼。 另一方面，於步驟S340中，將使用者資料寫入至記 憶體裝置中。此外，針對資料寫入的細部流程來看，首先， 6 201032233 z.9437twf.doc/n 於步驟S34卜依據使用者資料來程式化記憶體裝置。之 後’將於步驟S342，對記憶體裝置進行一寫入驗證，以判 別記憶體裝置中被程式化的記憶胞，其臨界電壓的準位是 否符合使用者資料的位元資訊。接著，於步驟S343，判別 -己體裝置是否通過寫入驗證。藉此，當寫入驗證尚未通 過時，則將重複上述步驟S341〜S343。反之，去官入給與 通過時，則將執行步驟S350。 _ .巧在步驟S350中’將讀取記憶體裝置中的使用者資料。 值得注意的是，在寫入使用者資料的過程中，使用者資料 可能會因過度程式化(over_program)而產生錯誤位元。此 外，在寫入使用者資料之後，使用者資料也可能會因電荷 損失(charge loss)而產生錯誤位元。因此，於步驟S35〇中 所讀取到的使用者資料可能帶有錯誤位元，而被視為一筆 讀取資料。 請繼續參照圖3 ’當讀取到記憶體裝置中的使用者資 料之後，將於步驟S360，根據所讀取到的使用者資料產生 ©—第二錯誤校正碼。接著，將於步驟S37〇，將第一與第二 錯誤校正碼寫入至記憶體裝置。藉此，使用者資料^可利 用第一與第二錯誤校正碼進行階段式的校正，進而致使本 實施例可以利用較低可更正位元數的第一與第二錯誤校正 碼，即可達到良好的更正能力。 舉例來說，如圖4所示的，在讀取記憶體裝置的過程 中，首先，於步驟S410,依照原先使用者資料所存入的位 址，讀取記憶體裝置中的第一錯誤校正碼、第二錯誤校正 201032233 /Ui^4 z9437twf.doc/n 碼以及-讀取資料。值得注意的是，步驟S35〇與步驟s· 所界定的讀取資料’其實是在；^_雜錢體農置中 所讀取到的使用者資料。由於讀取時間點的不同，因 步驟S35〇中所讀取到的使用者資料(讀取資料），與在步驟 S·中所讀取到的使用者資料(讀取資料），會因受 程度的電荷損失而可能有所不同。 s 於步驟S420,將讀取資料 ❹ ^暫存器，並透過步驟_，利用第二錯誤校正碼校正 Ί育料’以獲得-暫時資料。在校正讀取資料的過程中， =,步驟S43卜利用第二錯誤校正碼與讀取資料 3讀取資料的錯誤餘。之後，更於步驟趣，對讀取 =的錯誤位讀行校正，以獲得暫時㈣。換而言之， ==是_第二錯誤校正碼來對電荷損失所形成的部 刀位兀錯誤先進行第一階段的校正。 於㈣剛’時時資败新儲存在暫存器中 如Ϊ 致使暫時資料儲存在暫存器中。另一方面， 以獲、所不’利用第一錯誤校正碼校正暫時資料， 步者資料。在校正暫時資料的過財，首先，於 資料的錯誤校正碼與暫時資料，偵測出暫時 位元進^ ’於步驟S452 ’對暫時資料的錯誤 進仃扠正，以獲得使用者資料。 輕式本實施例是利用第—錯誤校正碼來對過度 正。Jr了損失所形成的位元錯誤進行第二階段的校 g ’本貫施娜可透過步驟變，利用使用者資料 8In order to make the above features and advantages of the present invention more comprehensible, the following detailed description is given in the accompanying drawings. [Embodiment] FIG. 3 is a flow chart showing an operation method of a memory device according to another embodiment of the present invention. FIG. 4 is a flow chart showing a method for operating a memory device according to another embodiment of the present invention. The remainder of the stylized β-remembrance device will be described with reference to FIG. 3 and the read memory device will be described mainly with reference to FIG. 4 . Further, the operation method described in the embodiments of Figs. 3 and 4 can be applied to the β 纟 阶 阶 ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( Referring to FIG. 3, in the process of programming the memory device, the embodiment first receives a user data as shown in step S310, and stores the received user data in a temporary storage in step S320. In the device. Then, as shown in step S330, a first error correction code is generated based on the user data. On the other hand, in step S340, the user profile is written to the memory device. In addition, for the detailed flow of data writing, first, 6 201032233 z.9437twf.doc/n in step S34, the memory device is programmed according to the user data. Thereafter, in step S342, a write verification is performed on the memory device to determine whether the programmed memory cell in the memory device has a threshold voltage level that matches the bit information of the user data. Next, in step S343, it is determined whether or not the own device passes the write verification. Thereby, when the write verification has not passed, the above steps S341 to S343 are repeated. On the other hand, when the official entry is passed, the process proceeds to step S350. In step S350, the user profile in the memory device will be read. It is worth noting that in the process of writing user data, user data may generate error bits due to over-programming. In addition, after the user data is written, the user data may also generate an error bit due to charge loss. Therefore, the user data read in step S35〇 may have an error bit and is regarded as a piece of read data. Referring to FIG. 3', after reading the user information in the memory device, in step S360, a ©-second error correction code is generated based on the read user data. Next, the first and second error correction codes are written to the memory device in step S37. Thereby, the user data can be phase-corrected by using the first and second error correction codes, thereby enabling the embodiment to use the first and second error correction codes of the lower correctable bit number. Good correction ability. For example, as shown in FIG. 4, in the process of reading the memory device, first, in step S410, the first error correction in the memory device is read according to the address stored in the original user data. Code, second error correction 201032233 /Ui^4 z9437twf.doc/n code and - read data. It is worth noting that the reading data defined in step S35〇 and step s· is actually the user data read in the ^_ miscellaneous money farm. Due to the difference in reading time, the user data (read data) read in step S35 and the user data (read data) read in step S· are subject to The degree of charge loss may vary. s In step S420, the data ❹ ^ register is read, and through step _, the second error correction code is used to correct the ’ ’ ' to obtain the temporary data. In the process of correcting the read data, =, step S43 uses the second error correction code and the read data 3 to read the error margin of the data. After that, it is more interesting to read the line of the error bit of the read = to obtain the temporary (four). In other words, == is the second error correction code to correct the first stage of the tool position error caused by the charge loss. In (4) just when the time is lost, the new one is stored in the register. For example, the temporary data is stored in the register. On the other hand, the temporary data, the step data are corrected by the first error correction code. In the correction of the temporary information, firstly, the error correction code and the temporary data of the data are detected, and the temporary bit is detected in step S452' to correct the temporary data to obtain the user data. The light embodiment of this embodiment utilizes the first error correction code to over-positive. Jr's loss caused by the bit error is carried out in the second stage of the school's _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
201032233 F970124 29437twf.doc/n 在1ΐ、Γ的暫時資料，使用者資料館存在 二k步驟S470 ’來輸出使用者資料。 糊。記憶繼的電路 一錯誤校正電路52(>Ui:包括—操作電路510、 c 暫存态53〇以及一記憶體540。錯 你ί"! 與暫存器53G電性連接至記憶體540。操 “ 5匕則電性連接至錯誤校正電路似與暫存器跡 w己憶體裝置500接收到使用者 =時地儲存在暫存請中，且操作電二 電路520根據尚未寫入至記憶體54()的使用者資料 錯誤校正碼。之後，使用者資料將寫入至記 請中的使用者資料將被讀取。值得注意的 =使用者資料可能會因過度程式化或/與電荷損失而帶 铁位凡，故被視為一筆讀取資料。此時，操作電路510 二使錯§吳校正電路520根據讀取資料而產生—第二錯誤 校正碼。 曰、 在一讀取操作模式下，錯誤校正電路520將再次讀取 儲存在記憶體540中的使用者資料。值得注意的是，從士己 憶體裝置巾所讀取_使用者資料，其錯誤位元可能合因 不同程度的電荷損失而隨著時間增加，故此時從記^體 540中再次讀取到的使用者資料將被視為另—筆讀取資 料二之，，操作電路510將利用第二錯誤校正碼來二正二 一頃取資料，以獲得一暫時資料，並利用第一錯誤校正碼 201032233 ^z9437twf.doc/n 來校正暫時資料，以獲得原始的使用者賴。 資料與讀取資料可暫存在暫存器53〇中 = =細部操作，已包含在上述各實施例中 ΐίΐ賴，本發日歧在使用者資料存人記憶體袭置之 :ί Ζ別進行編碼以產生第—與第二錯誤校正碼。 = :-31 月將可利用第一與第二錯誤校正碼對使用者資 枓進㈣段式的校正，㈣致使本發明可料㈣較 ，位兀數的第-與第二錯誤校正碼，即可達到良好正 能力。 舉例來說，倘若第一與第二錯誤校正碼的可更正 2別為Ν位讀⑽元，且為正整數時，倘若 —t Μ，則本發明只需帶有Ν位元更正能力的錯誤校正 =法(error-correct_alg〇rithm)，相對地偶若 Μ 大於 ν， ^發明只f帶有Μ位元更正能力的錯誤校正演算法。也 =疋說本發明可以制地針财的特性預先奴合適的 λ二”二中在矽的特性上，錯誤位元主要是受控在通過寫 後期⑽段中。然而’先前技雜是需要帶有 #立7^更正能力的錯誤校正演算法，來提供校正資 :此’與先前技術相較之下’本發明無需提高第-與 的可更正位元魏可以達到良好的更正能 、而5之，本發明將可降低硬體設施的複雜度，並且 #於心_之操作速度的提升。 d本發明已以實施例揭露如上，然其並非用以限定 201032233 P970I24 29437twf.d〇c/n 本發明，201032233 F970124 29437twf.doc/n In the temporary data of 1ΐ, 使用者, the user's library has two steps S470 ’ to output user data. paste. The memory-based circuit-error correction circuit 52 (>Ui: includes-operation circuit 510, c temporary state 53A, and a memory 540. The wrong register is electrically connected to the memory 540. "5" is electrically connected to the error correction circuit and appears to be stored in the temporary memory when the temporary memory device 500 receives the user = time, and the operation second circuit 520 is not yet written to the memory. The user data error correction code of the body 54(). After that, the user data written to the user data will be read. It is worth noting that the user data may be over-stylized or/and charged. The loss is accompanied by the iron position, so it is regarded as a reading data. At this time, the operation circuit 510 causes the error correction circuit 520 to generate a second error correction code according to the read data. 曰, in a read operation In the mode, the error correction circuit 520 will read the user data stored in the memory 540 again. It is worth noting that the error bits may be different from the user data read from the memory device. Degree of charge loss and increase with time Therefore, the user data read again from the memory 540 at this time will be regarded as another data read by the pen, and the operation circuit 510 will use the second error correction code to take the data. Obtain a temporary data, and use the first error correction code 201032233 ^z9437twf.doc/n to correct the temporary data to obtain the original user. The data and the read data can be temporarily stored in the temporary register 53 = = = details The operation, which is included in the above embodiments, is caused by the user data stored in the memory: Ζ 进行 进行 进行 产生 产生 产生 产生 产生 = = = = = = = = = = = = = = = The first and second error correction codes can be used to correct the user's (4) segment type correction, and (4) the invention can be made (4), and the first and second error correction codes of the number of bits can be achieved. For example, if the correctable 2 of the first and second error correction codes is a clamp read (10) element and is a positive integer, the present invention only needs to have the bit correction capability if -t Μ Error correction = method (error-correct_alg〇rithm), relatively even if Μ Greater than ν, ^Invented only f error correction algorithm with Μ bit correction ability. Also = 疋 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 λ λ λ λ λ λ λ λ λ λ λ The bits are mainly controlled in the late stage of writing (10). However, the 'previous skill' is an error correction algorithm that requires the ability to correct the error: this is compared with the prior art. The present invention can improve the complexity of the hardware facility without increasing the correctability of the first and the correctable bits, and the operation speed of the invention can be reduced. The above has been disclosed by way of example, but it is not intended to limit the invention of 201032233 P970I24 29437twf.d〇c/n,
識者，在不脫離 【圖式簡單說明】 虽可作些許之更動與潤飾，故本 之申晴專利範圍所界定者為準。 圖1A為先前 的方法流程圖。 前技術利用錯誤校正碼程式化快閃記憶體 圖1B為先前技術利用錯誤校正 方法流程圖。 碼讀取快閃記憶體的 圖2為MLC快閃記憶體之臨界電堡的分佈示意圖。 圖增示為依據本發明-實施例之記憶體裝置的操 方法流程圖。 圖4繪不為依據本發明另一實施例之記憶體裝置的操 作方法流程圖。 圖5繪示為依據本發明一實施例之記憶體裝置的電路 方塊圖。 【主要元件符號說明】 S111〜S114:用以說明圖1A的各步驟流程 S121〜S125 :用以說明圖1B的各步驟流程 210 :重疊分佈 S310〜S370、S341〜S343 :用以說明圖3實施例的各步 驟流程 S410〜S470、S431、S432、S451、S452 :用以說明圖 11 201032233 F97U124 29437twf.doc/n 4實施例的各步驟流程 500 :記憶體裝置 510 :操作電路 520 :錯誤校正電路 530 :暫存器 540 :記憶體If you know the person, don't leave it. [Simple description of the drawing] Although some changes and refinements can be made, the scope defined by Shenqing's patent scope shall prevail. Figure 1A is a flow chart of a prior method. The prior art uses the error correction code to program the flash memory. Figure 1B is a flow chart of the prior art utilizing the error correction method. Code reading flash memory Figure 2 is a schematic diagram of the distribution of the critical electric castle of the MLC flash memory. The figure is shown as a flow chart of the operation of the memory device in accordance with the present invention. 4 is a flow chart showing an operation method of a memory device in accordance with another embodiment of the present invention. FIG. 5 is a circuit block diagram of a memory device in accordance with an embodiment of the present invention. [Main component symbol description] S111 to S114: for explaining each step flow S121 to S125 of FIG. 1A: for explaining each step flow 210 of FIG. 1B: overlapping distributions S310 to S370, S341 to S343: for explaining FIG. 3 Steps S410 to S470, S431, S432, S451, S452 of the example: for explaining the steps 500 of the embodiment of FIG. 11 201032233 F97U124 29437twf.doc/n 4 : Memory device 510 : Operation circuit 520 : Error correction circuit 530: register 540: memory
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