TW201032202A

TW201032202A - Shift register, scan driving circuit and display apparatus

Info

Publication number: TW201032202A
Application number: TW98104865A
Authority: TW
Inventors: Yi-Cheng Tsai
Original assignee: Chi Mei Optoelectronics Corp
Priority date: 2009-02-16
Filing date: 2009-02-16
Publication date: 2010-09-01
Also published as: TWI433118B

Abstract

A shift register (SR) includes plural stages of shift register units. A first stage of shift register unit includes a first driving element and a first shifting element. The first driving element outputs a first driving signal according to a first clock signal and a start signal. The first shifting element is electrically connected with the first driving element and outputs a first shifting signal as a start signal of the next stage of shift register unit according to the start signal and a second clock signal. Both level differences of the start signal and the second clock signal are greater than that of the first clock signal. A scan driving circuit and a display apparatus including the shift register are also disclosed.

Description

201032202 六、發明說明【發明所屬之枝術領域】明所屬之枝術領域】置、. 於一種顯示裝置，特別關於-種顯示裝知描驅動t路及移位暫存器。【先前技術】 CRT;頁：装5由早期的陰極射線管（Cath°de ray displ y 〇i^id ^Stal ^ — 並廣泛應用於通⑽卿）顯示裝置，以液晶顯示裝置::=:子:產品上。驅動電路及-資料驅動電路二=板、-掃描移位暫存器，其係用以傳 ^動電路係具有一移位暫存單元電性連接_數‘=喊’以依序驅動與請參照圖1所示，— ^ 級移位暫存單元u〜l4。直為知移位暫存器1係包含複數暫存單元Μ移位暫存單幻3’m暫存單元12與移位 13與移位暫存單元14電佳連接，移位暫存單元 =為彼此相位相差180度之時脈=時脈訊號⑶及分別與奇數級移位暫存單、§ ^，時脈訊號CK1 為起始訊號，Vss 及w電性連接。位暫存單元η至移位暫存單元]4輪=::，^^ 201032202 於習知技術中，每一級移位暫存單元輸出至顯示區的驅動訊號，不但用以驅動一整列的像素，亦成為其下一級淨夕位暫存單元的起始訊號，且成為上一級移位暫存單元的重置訊號（Reset)，以此類推。以圖}為例，第—級移位暫存單元11係接收起始訊號STVl及時脈訊號CKi並輸出 -驅動訊號〇Utl ’驅動訊號0utl 一方面用以驅動對應的掃二線’另-方面係作為移位暫存單元12之起始訊號仍2。而移位暫存單元12雜收移位暫存單元u的驅動 ^虎〇Utl作為純暫存單元12之料喊，再配合時脈 _ CK2而輸出-驅動訊號⑽2並作為移位暫存單元13 之起始訊號ST%及移位暫存單元u的重置訊號。 —種習知移位暫存單元之電路如圖2所示f其中，移位暫存單7^包含四個電晶體T1〜T4及m、cb。f :，T1為緩衝（Buffer )電晶體，丁2及η為下拉（puu D賴）電曰曰體，TU驅動（Drive)電晶體。輪入訊號有第（n 動？：輸出的驅動訊號0utN—1及第（Ν+ι)級輸出的驅二〇utN+1、爹考電位Vss以及時脈訊號ck。輸出訊 $第N級輸出的驅動訊號％。舉例來說，若第魏級’則第(N-丨)級為第四級，而第(N+1)級為圖3係頒不一種習知移位暫在置-夂昭_ 杪瞀存早兀的訊號時序圖。請暫;：”及圖3所示’細中N等於！，即第-級移位飞仔早元為例來加以說明盆作動大彳移位暫存單元的起料Utv 而恤即為第一級 5 201032202 於第一時間ti時，第一級移位暫存單元的時脈訊號 CK1為低準位電壓Vgl，起始訊號STV!為高準位電壓 Vgh。此時，電晶體T4為導通狀態，使得節點P的電壓訊號Vp = Vgh—Vth，其中，Vth為電晶體T4之臨限電壓 (Threshold Voltage)。此時電晶體T1將導通，使得第一級的驅動訊號Outu為時脈訊號CK1的低準位電壓Vgl。此時因第二級的驅動訊號Out2為低準位電壓Vgl，故電晶體 T2與T3為截止狀態。於第二時間t2時，第一級移位暫存單元的時脈訊號 CK1為高準位電壓Vgh，起始訊號STV!為低準位電壓 Vgl。此時，電晶體T4為截止狀態，電晶體T1為導通狀態，使得推昇電容器Cb的一端藉由時脈訊號CK1之高準位而昇壓，所以推昇電容器Cb的另一端亦昇壓，以致節點P的電壓Vp訊號改變如下：201032202 VI. Description of the invention [The field of branching technology of the invention] The field of branching of the invention is set. In a display device, in particular, the display device is described as a driving t-channel and a shift register. [Prior Art] CRT; Page: Mounted by an early cathode ray tube (Cath°de ray displ y 〇i^id ^Stal ^ - and widely used in Tong (10) Qing) display device, with liquid crystal display device::=: Sub: On the product. Drive circuit and data drive circuit 2 = board, - scan shift register, which is used to transfer the circuit has a shift temporary storage unit electrical connection _ number '= shout' to drive and please Referring to Fig. 1, the - level shifts the temporary storage units u to l4. The straight-forward shift register 1 includes a plurality of temporary storage units, the shift temporary storage single magic 3'm temporary storage unit 12 and the shift 13 and the shift temporary storage unit 14 are electrically connected, and the shift temporary storage unit is The clocks that are 180 degrees out of phase with each other = the clock signal (3) and the odd-level shift temporary storage list, § ^, the clock signal CK1 is the start signal, and Vss and w are electrically connected. Bit temporary storage unit η to shift temporary storage unit] 4 rounds =::, ^^ 201032202 In the prior art, each stage shifting temporary storage unit outputs a driving signal to the display area, which is not only used to drive an entire column of pixels It also becomes the starting signal of the next-level net-temporary temporary storage unit, and becomes the reset signal of the previous-stage shift register unit, and so on. Taking the diagram as an example, the first stage shift register unit 11 receives the start signal STV1 and the time pulse signal CKi and outputs a drive signal 〇Utl 'drive signal 0utl on the one hand to drive the corresponding sweep line 'other side' The starting signal as the shift register unit 12 is still 2. The shift register unit 12 misplaces the drive of the temporary storage unit u, as the pure temporary storage unit 12, and outputs the drive signal (10) 2 as the shift temporary storage unit with the clock _CK2. The start signal ST% of 13 and the reset signal of the shift register unit u. The circuit of the conventional shift temporary storage unit is as shown in Fig. 2. Among them, the shift temporary storage unit 7^ includes four transistors T1 to T4 and m and cb. f :, T1 is a buffer (Buffer) transistor, and D2 and η are pull-down (puu D) electric ,, TU drive (Drive) transistor. The round-in signal has the (n action?: output drive signal 0utN-1 and the (Ν+ι) level output drive 〇 +1N+1, reference potential Vss and clock signal ck. Output signal $ N level The output drive signal %. For example, if the first level is 'the (N-丨) level is the fourth level, and the (N+1) level is the figure 3, the conventional shift is temporarily placed. -夂昭_ 讯兀兀兀兀。。。。。请请请请请请请请请请请请 ; ; ; ; ; ; ; ; ; : : : : : : : : : : : : : : : : : The shifting Utv of the temporary storage unit is the first level 5 201032202. At the first time ti, the clock signal CK1 of the first stage shift register unit is the low level voltage Vgl, the start signal STV! It is a high-level voltage Vgh. At this time, the transistor T4 is in an on state, so that the voltage signal Vp of the node P is Vgh_Vth, where Vth is the threshold voltage of the transistor T4. At this time, the transistor T1 It will be turned on, so that the driving signal Outu of the first stage is the low level voltage Vgl of the clock signal CK1. At this time, since the driving signal Out2 of the second stage is the low level voltage Vgl, the transistor T2 T3 is an off state. At the second time t2, the clock signal CK1 of the first stage shift register unit is the high level voltage Vgh, and the start signal STV! is the low level voltage Vgl. At this time, the transistor T4 In the off state, the transistor T1 is in an on state, so that one end of the push-up capacitor Cb is boosted by the high level of the clock signal CK1, so the other end of the push-up capacitor Cb is also boosted, so that the voltage of the node P is Vp. The signal changes as follows:

Vp = Vgh-Vth+AVb00St，而 △Vb_=【Cb/ (Cb+Cp)】X ( Vgh-Vgl)(式 1) 其中，Vth為電晶體T4之臨限電壓，而Cp為連接至 P點的寄生電容，例如Cgs或Cgd。因為第二級的驅動訊號Out2仍是低準位電壓Vgl，故電晶體T2與電晶體T3仍為截止狀態。第一級的驅動訊號〇叫由低準位電壓Vgl轉變為高準位電壓Vgh，並成為第二級移位暫存單元的起始訊號。於第三時間t3時，對第二級移位暫存單元而言，因其起始訊號為第一級的驅動訊號Out!且時脈訊號CK2為高 6 201032202 準位電麗Vgh，第二級移位暫存單元如第二時間q之第― 級移位暫存單元的作動順序一樣，因此第二級的驅動訊號〇ut2是高準位電壓Vgh。於第三時間t3時，第一級移位暫存單元的時脈訊號 CK1及起始訊號STV均為低準位電壓Vgl。因為第二級的驅動訊號0加2為高準位電壓Vgh，因此，第—級移位暫存單元的電晶體T2與電晶體T3為導通狀態，節點p的電壓鲁訊號Vp變為低準位電壓VgL·電晶體T1為截止狀態，電晶體T4為截止狀態’以致第一級的驅動訊號由高準位電壓Vgh轉變為低準位電壓Vgl。如圖3所示’當第一級移位暫存單元u於第一時間 tl接收起始訊號STV】後，其驅動訊號〇utl於第二時間時輸出為高準位電壓Vgh，而第二級移位暫存單元的驅動訊號〇说2於第三時間t3輸出為高準位電壓Vgh，第二級移位暫存單元的驅動訊號〇饥3於第四時間t4輪出為高準 • 位電壓Vgh ’即後級輸出的驅動訊號將依不同時間順序，依序地輸出高準位電壓Vgh以驅動其對應之掃描線。然而，若以習知的電路來驅動較大尺寸或高解析度顯示面板時，由於驅動訊號的上升時間（Rise Time)及下降時間（Fall Time)太長而造成充電不足及放電不良之情況，此將造成顯示面板發生混色現象。傳統改良的做法不外乎將時脈訊號CK1及CK2的高低電壓準位差提高，即將（Vgh〜Vgl)提高’但此會增: 功率損耗p : θ曰σ 7 201032202 P = VddxIave=Vdd (Cb><VswiNGxl/2xFCL〇cK)(式 2) 其中，VSWING= (Vgh—Vgl)。如式2所示，提高VSWINC3將同時提高移位暫存單元的驅動功率損耗。另一做法是將緩衝電晶體T1的尺寸加大以增加驅動能力，但此做法將增加寄生電容Cp值（式〇。由式1得知，若寄生電容Cp之電容值增加，將使得變小，使得節點P的電位降低，導致緩衝電晶體T1推動負載（例如顯示區的元件）的能力降低。觀察式1可知，另一提高 P點電位之做法為加大推昇電容器Cb之電容值以使 △Vboost變大，由式2發現，此法又將提高功率損耗，若驅動電路與顯示區同時形成時，將會使面板之額緣寬度 (Border Width)變大而佔用較大基板面積；若驅動電路為一獨立1C封裝，則會加大1C的尺寸而使驅動電路成本增加。因此，如何提供一種能縮短移位暫存單元之驅動訊號的上升時間及下降時間以避免顯示面板發生混色現象，且功率損耗可較傳統設計大幅減少又可縮小額緣寬度或降低驅動電路成本的移位暫存器、掃描驅動電路及顯示裝置，實為當前的重要課題之一。【發明内容】有鑑於上述課題，本發明之目的為提供一種能夠縮短移位暫存單元之驅動訊號的上升時間及下降時間以避免 8 201032202 顯示面板發生混色現象，而且功率損耗可較傳统減少又可縮小額緣寬度的移位暫存器、掃描驅動；路“ 示裝置。 ‘ 為達上述目的，本發明提供—種移位暫複數級移位暫存單元，其中_第„級移位暫存單二一第-驅動元件以及-第-移位元件。第—驅動ς = 第一時脈訊號及—起始訊號輸出—第—驅動_。第: 位7G件與第一驅動元件電性連接，並依多二時脈訊號輸出-第—移位訊號以作為下—71號及一第存單元的起始喊。起始訊號差、，及之移位暫之一準位差大於第一時脈m號之—=及卓二時脈訊號 .〜〜卞Ί儿左〇為達上述目的’本發明提供—_描_ 有複數級移轉存單元，各級移”存單 —具配合。其中一第一級移位暫存單元掃描線及-第-移位元件。第—驅動元件依:一：-:動元件以 -起始訊號輪出—第—驅動訊號，以使—第=訊號及 -第-掃描訊號。第一移位元件與第一驅動二：輸出 t亚依據心訊號及—第二時脈訊號輸出—第—移生連號以作為下〜級之鋒暫存單元的起始立5fl 之-準位差及第二時脈訊號之一準位差：而起：訊號號之一準位差。人於第一時脈訊為達^逑目的’本發明提供一種顯示裝置， H、-資料驅動電路以及-掃描驅動電路J含驅動電路μ複數資料線與顯㈣板電資料疋接。婦插驅動 9 201032202 電路藉由複數掃描線與顯示面板電性連接，且具有複數級移位暫存單元，各級移位暫存單元係與各掃描線配合。其中一第一級移位暫存單元具有一第一驅動元件以及一第一移位元件。第一驅動元件依據一第一時脈訊號及一起始訊號輸出一第一驅動訊號，以使一第一掃描線輸出一第一掃描訊號。第一移位元件與第一驅動元件電性連接，並依據起始訊號及一第二時脈訊號輸出一第一移位訊號以作為下一級之移位暫存單元的起始訊號。而起始訊號之一準位差及第二時脈訊號之一準位差大於第一時脈訊號之一準位差。承上所述，依據本發明之移位暫存器、掃描驅動電路及顯示裝置，其係藉由提高起始訊號之電壓準位差及第二時脈訊號之電壓準位差，使缓衝電晶體的推力升高以縮短驅動訊號的上升時間，與習知技術相比，可以避免顯示面板發生色差現象。另外，更可快速地將驅動訊號降至低準 φ 位以縮短放電時間，避免顯示面板發生混色現象，而且，功率損耗可較傳統設計大幅減少又可縮小額緣寬度或降低驅動電路成本。【實施方式】以下將參照相關圖式，說明依本發明之移位暫存器、掃描驅動電路及顯示裝置。請參照圖4所示，本發明較佳實施例之一種顯示裝置 2係包含一顯示面板3、一掃描驅動電路4以及一資料驅 10 201032202 動電路5。其中，掃描驅動電路4係藉由複數掃描線S21 〜S2m與顯示面板3電性連接，資料驅動電路5係藉由複數資料線D2I〜D2n與顯示面板3電性連接。本實施例之顯示面板3可例如為液晶顯示面板、有機電激發光顯示面板、發光二極體顯示面板或其他平面顯示面板。請參照圖5所示，本發明較佳實施例之掃描驅動電路 4係包含一移位暫存器41，移位暫存器41具有複數級移位暫存單元，分別與掃描線S21〜S2m配合應用。其中，第一級移位暫存單元包含一第一驅動元件411 以及一第一移位元件412。第一驅動元件411依據一第一時脈訊號CK1'及一起始訊號STV'輸出一第一驅動訊號 Out、用以驅動掃描線S21。第一移位元件412與第一驅動元件411電性連接，並依據起始訊號STV1及一第二時脈訊號CK-Γ輸出一第一移位訊號SS、以作為下一級之移位暫存單元的起始訊號STV'。其中，起始訊號STV'之一準位差及第二時脈訊號CK-Γ之一準位差大於第一時脈訊號 CK1'之一準位差。舉例來說，在一第一時間，第一驅動元件411依據起始訊號STV’產生具有一第一準位的電壓訊號Vp'(即節點之電壓）。在一第二時間，第一驅動元件411依據第一時脈訊號CK1'使電壓訊號Vp1提升至一第二準位，俾使第一驅動元件411依據第一時脈訊號CK1'輸出第一驅動訊號 Out、以驅動掃描線S21 〇此外，在第二時間，第一驅動元件411使電壓訊號Vp!提升至第二準位，俾使第一移位元 11 201032202 件412依據第二時脈訊號a]，輪出第—移位訊號μ 作為下一級之起始訊號STV，。當第二級移位暫存單元在第二時間接收到第訊號SSW為其起始訊號STV，之後即開位暫存單元包含1二媒動元件414及一第二移 415。在一第三時間，第二驅動元件414依據一第三訊號㈤，及起始訊號STV，輸出—第二驅動訊號㈣= I第三時脈減CK2H時脈減CK1，反相。由於= 動70件414與第—驅動元件411之電路相同，故動方式請參照上述說明而不再贅述。 /、作此外，第二移位元件415在第三時間依據起始 ^及-第四時脈訊號似，輸出4二移位訊號s = 作為下一級之移位暫存單元的起始訊號STV,。其中第脈戒唬CK-21與第二時脈訊號，係反相，且起始寿Vp = Vgh-Vth+AVb00St, and ΔVb_=[Cb/(Cb+Cp)]X (Vgh-Vgl) (Formula 1) where Vth is the threshold voltage of the transistor T4, and Cp is connected to the P point Parasitic capacitance, such as Cgs or Cgd. Since the driving signal Out2 of the second stage is still the low level voltage Vgl, the transistor T2 and the transistor T3 are still in an off state. The driving signal of the first stage is changed from the low level voltage Vgl to the high level voltage Vgh, and becomes the starting signal of the second stage shift register unit. At the third time t3, for the second-stage shift temporary storage unit, the start signal is the first-level driving signal Out! and the clock signal CK2 is high 6 201032202 level electric Vgh, second The stage shift register unit has the same operation sequence as the first stage shift register unit of the second time q, so the drive signal 〇ut2 of the second stage is the high level voltage Vgh. At the third time t3, the clock signal CK1 and the start signal STV of the first stage shift register unit are both low level voltages Vgl. Since the driving signal 0 of the second stage is increased by 2 to the high level voltage Vgh, the transistor T2 and the transistor T3 of the first stage shift register unit are turned on, and the voltage signal Vp of the node p becomes low level. The bit voltage VgL·the transistor T1 is in an off state, and the transistor T4 is in an off state ′ so that the driving signal of the first stage is converted from the high level voltage Vgh to the low level voltage Vgl. As shown in FIG. 3, when the first stage shift register unit u receives the start signal STV at the first time t1, the drive signal 〇utl is output as the high level voltage Vgh at the second time, and the second The drive signal of the stage shift register unit 〇 2 is output as the high level voltage Vgh at the third time t3, and the drive signal of the second stage shift register unit is high in the fourth time t4. The bit voltage Vgh′, that is, the driving signal outputted by the subsequent stage, sequentially outputs the high level voltage Vgh to drive its corresponding scanning line in different time sequences. However, when a large-size or high-resolution display panel is driven by a conventional circuit, the rise time and the fall time of the drive signal are too long, resulting in insufficient charging and poor discharge. This will cause color mixing on the display panel. The traditional improvement method is nothing more than increasing the high and low voltage level difference of the clock signals CK1 and CK2, that is, increasing (Vgh~Vgl) 'but this will increase: power loss p : θ曰σ 7 201032202 P = VddxIave=Vdd ( Cb><VswiNGxl/2xFCL〇cK) (Formula 2) where VSWING = (Vgh - Vgl). As shown in Equation 2, increasing VSWINC3 will simultaneously increase the drive power loss of the shift register unit. Another method is to increase the size of the buffer transistor T1 to increase the driving capability, but this method will increase the parasitic capacitance Cp value (Expression 〇. It is known from Equation 1 that if the capacitance value of the parasitic capacitance Cp increases, it will become smaller. The potential of the node P is lowered, resulting in a decrease in the ability of the buffer transistor T1 to push the load (for example, an element of the display area). As can be seen from Equation 1, another method of increasing the potential of the P point is to increase the capacitance of the boost capacitor Cb. The ΔVboost is made larger, and it is found by Equation 2 that this method will increase the power loss. If the driving circuit and the display area are formed at the same time, the border Width of the panel will be increased to occupy a larger substrate area; If the driving circuit is an independent 1C package, the size of 1C is increased and the cost of the driving circuit is increased. Therefore, how to shorten the rising time and falling time of the driving signal of the shift register unit can be shortened to avoid color mixing of the display panel. A shift register, a scan drive circuit, and a display device, which have a large power loss and can reduce the margin width or reduce the cost of the drive circuit. SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide a method for reducing the rise time and fall time of a drive signal of a shift register unit to avoid color mixing of the display panel of the 201032202. Moreover, the power loss can be reduced compared with the conventional one, and the shift register and the scan drive can be reduced in the width of the margin; the road "display device." To achieve the above purpose, the present invention provides a shift temporary multi-level shift temporary storage unit, Wherein _ „stage shift temporary storage single two-first drive element and − _ shifting element. The first drive ς = first clock signal and – start signal output – first drive _. Electrically connected to the first driving component, and outputting the first-shift signal according to the second clock signal as the starting address of the lower-71 and the first storage unit. The initial signal difference, and the shifting temporary One of the level differences is greater than the first clock m number -= and Zhuo Er clock signal. ~ ~ 卞Ί儿左〇 for the above purpose 'The present invention provides _ _ _ there are multiple levels of shift storage units, all levels Move "storage order" with a match. a first stage shift register unit scan line and a -th shift element. The first drive element is: -:: the dynamic element is - the start signal is rotated - the first drive signal, so that - the = signal And - the first scan signal. The first shifting element and the first driving two: the output t sub-based heart signal and - the second clock signal output - the first shifting serial number as the lower ~ level of the front register unit The starting position 5fl - the standard deviation and the second clock signal one of the level difference: from: one of the signal number level difference. The person in the first time pulse is for the purpose of the present invention provides a display The device, the H, the data driving circuit and the scanning driving circuit J comprise the driving circuit μ complex data line and the display (four) board electrical data connection. The female insertion driver 9 201032202 circuit is electrically connected to the display panel by the plurality of scanning lines, and has The multi-level shift temporary storage unit is matched with each scanning line. A first stage shift register unit has a first drive element and a first shift element. The first driving component outputs a first driving signal according to a first clock signal and a start signal, so that a first scanning line outputs a first scanning signal. The first shifting component is electrically connected to the first driving component, and outputs a first shifting signal according to the start signal and the second clock signal as the starting signal of the shifting temporary storage unit of the next stage. The one of the start signal and one of the second clock signals are greater than one of the first clock signals. According to the present invention, the shift register, the scan driving circuit and the display device are buffered by increasing the voltage level difference of the start signal and the voltage level difference of the second clock signal. The thrust of the transistor is increased to shorten the rise time of the driving signal, and the chromatic aberration of the display panel can be avoided as compared with the prior art. In addition, the drive signal can be quickly reduced to a low level φ position to shorten the discharge time and avoid color mixing of the display panel. Moreover, the power loss can be significantly reduced compared with the conventional design, and the margin width can be reduced or the cost of the driving circuit can be reduced. [Embodiment] Hereinafter, a shift register, a scan driving circuit, and a display device according to the present invention will be described with reference to the related drawings. Referring to FIG. 4, a display device 2 according to a preferred embodiment of the present invention includes a display panel 3, a scan driving circuit 4, and a data drive 10 201032202. The scan driving circuit 4 is electrically connected to the display panel 3 via the plurality of scanning lines S21 to S2m, and the data driving circuit 5 is electrically connected to the display panel 3 via the plurality of data lines D2I to D2n. The display panel 3 of this embodiment may be, for example, a liquid crystal display panel, an organic electroluminescent display panel, a light emitting diode display panel, or other flat display panel. Referring to FIG. 5, the scan driving circuit 4 of the preferred embodiment of the present invention includes a shift register 41 having a plurality of shift register units, respectively, and scan lines S21 to S2m. With the application. The first stage shift register unit includes a first driving element 411 and a first shifting element 412. The first driving component 411 outputs a first driving signal Out according to a first clock signal CK1' and a start signal STV' for driving the scan line S21. The first shifting component 412 is electrically connected to the first driving component 411, and outputs a first shifting signal SS according to the start signal STV1 and a second clock signal CK-Γ, as a shifting temporary storage of the next stage. The starting signal STV' of the unit. The one-position difference of the start signal STV' and the one-position difference of the second clock signal CK-Γ are greater than one of the first clock signals CK1'. For example, at a first time, the first driving component 411 generates a voltage signal Vp' (ie, the voltage of the node) having a first level according to the start signal STV'. At a second time, the first driving component 411 boosts the voltage signal Vp1 to a second level according to the first clock signal CK1', so that the first driving component 411 outputs the first driving according to the first clock signal CK1'. The signal Out is to drive the scan line S21. In addition, in the second time, the first driving component 411 raises the voltage signal Vp! to the second level, so that the first shifting element 11 201032202 is 412 according to the second clock signal. a], the first shift signal μ is taken as the start signal STV of the next stage. When the second stage shift register unit receives the first signal SSW as its start signal STV at the second time, the open temporary storage unit includes a second medium element 414 and a second shift 415. At a third time, the second driving component 414 outputs a second driving signal (4) according to a third signal (5) and a start signal STV = I third clock minus CK2H clock minus CK1, inverting. Since the operation of the 70th 414 is the same as the circuit of the first driving element 411, please refer to the above description and will not be described again. In addition, the second shifting component 415 outputs the 4 second shift signal s = as the start signal STV of the shift register unit of the next stage according to the initial and fourth clock signals at the third time. ,. The first pulse, the CK-21 and the second clock signal, are in reverse, and the initial life

S_TV之一準位差及第四時脈訊號CK_2'之-準位差:於楚三時脈訊號CK2,之-準位差。由於第二移位元件415 = 移位兀件412之電路相同，故其作動方式請參昭^ 明而不再贅述。 …、上述說另外，第一移位暫存單元更包含一第一下技 d〇wn)凡件413，其係與第一驅動元件411及第— 件化電性連接，並由下一級的移位暫存單元所輪出之: 第一移位訊號SS'2所控制。當第二級移位暫存單元在第三時間輸出第二移位訊號叫時，第一下拉元件413依據[ —移位汛號SS’2使第—驅動訊號〇ut,i迅速下拉至低準位。 12 201032202 第二級移位暫存單元亦可包含一第二下拉元件416, 由於其電路與第一下拉元件相同，故其作動方式不再贅述。如圖5所示係以四級移位暫存單元為例說明，由於各級移位暫存單元之作動可參照第一級及第二級移位暫存單元，故於此不再贅述，且熟知此一技藝者，當可依據其需求而增加移位暫存單元之個數。另外，本實施例所提之第一級移位暫存單元並非一定是實際上的第一級移位暫存單元，其係可為非最後一級之任一級移位暫存單元。另外，本實施例之移位暫存單元亦可應用於資料驅動電路或其他需要依序傳遞訊號之電路。以下將以第一級移位暫存單元為例說明其内部電路架構。第一實施例請參照圖6所示，其係為本發明第一實施例之移位暫存單元之電路示意圖。第一驅動元件411包含一第一電晶體（可稱為緩衝電晶體）T101、一第二電晶體T102以及一電容器Cb'。其中，電晶體T101與電晶體T102以及電容器Cb'電性連接。電晶體T101的控制端用以接收一電壓訊號Vp'(節點P'之電壓），第一端用以耦接第一時脈訊號 CK1'，第二端用以輸出第一驅動訊號Out'!以驅動掃描線 S21。電晶體T102的第一端與其控制端電性連接並接收一起始訊號STV'，第二端係用以耦接電壓訊號Vp’。電容器 cb'的第一端與電晶體Tioi之第二端電性連接，電容器ciy 的第二端係用以耦接電壓訊號Vp'。 13 201032202 第一移位元件412包含一第三電晶體T103,其控制端係用以接收電壓訊號Vp'，其第一端係用以耦接第二時脈訊號CK-Γ，其第二端係用以輸出第一移位訊號SS、。第一下拉元件413包含一第四電晶體T104、一第五電晶體T105以及一第六電晶體T106。電晶體T104的控制端係用以接收第二移位元件所輸出的一第二移位訊號 SS'2，其第一端係用以接收第一驅動訊號Out、，其第二端係用以耦接一參考電位Vss。電晶體T105的控制端係用以接收第二移位訊號SS、，其第一端係用以耦接電壓訊號 Vp'，其第二端係用以耦接參考電位Vss。電晶體T106的控制端係用以接收第二移位訊號SS'2，其第一端係用以耦接第一移位訊號SSS，其第二端係用以耦接一參考電位 Vss。請參照圖7所示，其係為本發明第一實施例之移位暫存單元的時序圖。其中，起始訊號STV1、第二時脈訊號 CK-Γ及第四時脈訊號CK-2'的準位差係大於第一時脈訊號 CK1’及第三時脈訊號CK21的準位差。在本實施例中，上述訊號的低準位皆相同，而起始訊號STV1、第二時脈訊號 CK-Γ及第四時脈訊號CK-2'的最高準位電壓為Vgh1，第一時脈訊號CK1'及第三時脈訊號CK21的最高準位電壓為 Vgh，且 Vgh’大於 Vgh。以下之說明請同時參照圖6及圖7。於第一時間tl時，第一時脈訊號CK1'為低準位電壓 Vgl，第二時脈訊號CK-Γ為低準位電壓Vgl，而第一級移 14 201032202 位暫存單元所接收之起始訊號STV'為高準位電壓Vgh’。此時，電晶體T102為導通狀態，因此，節點F的電壓訊號Vp' = Vgh'—Vth，其中，Vth為電晶體T102之臨限電壓。因為第二移位訊號SS'2是低準位電壓Vgl，電晶體T104、電晶體T105及電晶體T106為截止狀態。因節點P'的電壓訊號Vp'=Vgh’一 Vth，故電晶體T101及電晶體T103為導通狀態，但第一時脈訊號CK1'及第二時脈訊號CK-Γ為低準位電壓，故第一驅動訊號Out、及第一移位訊號SSS亦是低準位電壓Vgl。於第二時間t2時，第一級移位暫存單元所接收之第一時脈訊號CK1'為高準位電壓Vgh，第二時脈訊號CK-Γ為高準位電壓VgW，而起始訊號STV'為低準位電壓Vg卜此時，電晶體T102為截止狀態，而電晶體T101及電晶體 T103為導通狀態，且由於電容器Cb'的一端依據第一時脈訊號的高準位而昇壓，使得電容器Cb’的另一端亦昇壓， φ 故節點P'的電壓訊號Vp'如下：The quasi-position difference of one of S_TV and the quasi-position difference of the fourth clock signal CK_2': in the Chu three-clock signal CK2, the quasi-position difference. Since the circuit of the second shifting element 415 = the shifting element 412 is the same, the manner of operation thereof is described in detail and will not be described again. In addition, the first shift register unit further includes a first lower part 411, which is electrically connected to the first driving element 411 and the first component, and is connected to the next stage. The wheeled temporary storage unit rotates: The first shift signal SS'2 controls. When the second stage shift register unit outputs the second shift signal at the third time, the first pull-down element 413 quickly pulls down the first drive signal 〇ut, i according to the [-shift apostrophe SS'2 Low level. 12 201032202 The second-stage shift register unit may also include a second pull-down element 416. Since the circuit is the same as the first pull-down element, the manner of operation thereof is not described. As shown in FIG. 5, the four-stage shifting temporary storage unit is taken as an example. Since the operation of the shifting temporary storage unit of each stage can refer to the first-stage and second-stage shifting temporary storage units, the details are not described herein. And the skilled person knows how to increase the number of shifting temporary storage units according to their needs. In addition, the first stage shift register unit mentioned in this embodiment is not necessarily the actual first stage shift register unit, and may be any stage shift register unit other than the last stage. In addition, the shift register unit of this embodiment can also be applied to a data driving circuit or other circuit that needs to sequentially transmit signals. The internal circuit architecture will be described below by taking the first-stage shift register unit as an example. First Embodiment Referring to Figure 6, there is shown a circuit diagram of a shift register unit in accordance with a first embodiment of the present invention. The first driving element 411 includes a first transistor (which may be referred to as a buffer transistor) T101, a second transistor T102, and a capacitor Cb'. The transistor T101 is electrically connected to the transistor T102 and the capacitor Cb'. The control terminal of the transistor T101 is configured to receive a voltage signal Vp' (the voltage of the node P'), the first end is used to couple the first clock signal CK1', and the second end is used to output the first driving signal Out'! To drive the scanning line S21. The first end of the transistor T102 is electrically connected to its control terminal and receives a start signal STV', and the second end is coupled to the voltage signal Vp'. The first end of the capacitor cb' is electrically connected to the second end of the transistor Tioi, and the second end of the capacitor ciy is coupled to the voltage signal Vp'. 13 201032202 The first shifting component 412 includes a third transistor T103, and the control terminal is configured to receive the voltage signal Vp', the first end of which is coupled to the second clock signal CK-Γ, and the second end thereof It is used to output the first shift signal SS. The first pull-down element 413 includes a fourth transistor T104, a fifth transistor T105, and a sixth transistor T106. The control terminal of the transistor T104 is configured to receive a second shift signal SS'2 outputted by the second shifting component, the first end is for receiving the first driving signal Out, and the second end is for receiving the second driving end A reference potential Vss is coupled. The control terminal of the transistor T105 is configured to receive the second shift signal SS, the first end of which is coupled to the voltage signal Vp', and the second end of the transistor is coupled to the reference potential Vss. The control terminal of the transistor T106 is configured to receive the second shift signal SS'2, the first end of which is coupled to the first shift signal SSS, and the second end of the transistor is coupled to a reference potential Vss. Referring to Fig. 7, it is a timing chart of the shift register unit of the first embodiment of the present invention. The level difference between the start signal STV1, the second clock signal CK-Γ, and the fourth clock signal CK-2' is greater than the level difference between the first clock signal CK1' and the third clock signal CK21. In this embodiment, the low level of the signal is the same, and the highest level voltage of the start signal STV1, the second clock signal CK-Γ, and the fourth clock signal CK-2' is Vgh1, the first time The highest level voltage of the pulse signal CK1' and the third clock signal CK21 is Vgh, and Vgh' is greater than Vgh. Please refer to Figure 6 and Figure 7 for the following description. When the first time is t1, the first clock signal CK1' is the low level voltage Vgl, and the second clock signal CK-Γ is the low level voltage Vgl, and the first stage shift is received by the 201032202 bit temporary storage unit. The start signal STV' is a high level voltage Vgh'. At this time, the transistor T102 is in an on state, and therefore, the voltage signal Vp' = Vgh' - Vth of the node F, where Vth is the threshold voltage of the transistor T102. Since the second shift signal SS'2 is the low level voltage Vgl, the transistor T104, the transistor T105, and the transistor T106 are in an off state. Because the voltage signal Vp'=Vgh'-Vth of the node P', the transistor T101 and the transistor T103 are in an on state, but the first clock signal CK1' and the second clock signal CK-Γ are low level voltages. Therefore, the first driving signal Out and the first shift signal SSS are also the low level voltage Vgl. At the second time t2, the first clock signal CK1' received by the first stage shift register unit is the high level voltage Vgh, and the second clock signal CK-Γ is the high level voltage VgW, and the start The signal STV' is the low level voltage Vg. At this time, the transistor T102 is in an off state, and the transistor T101 and the transistor T103 are in an on state, and since one end of the capacitor Cb' is in accordance with the high level of the first clock signal. Boost, so that the other end of the capacitor Cb' is also boosted, φ, so the voltage signal Vp' of the node P' is as follows:

Vp’^Vgh' —VA+AVp'，而 AVp'=【Cb，/(Cb’ + Cp)】X (Vgh—Vgl) 其中，Vth為電晶體T102之臨限電壓，而Cp為連接至P點的寄生電容，例如Cgs及Cgd。因為第二移位訊號SS'2仍是低準位電壓Vgl，故電晶體T104、電晶體T105及電晶體T106仍為截止狀態。由於電晶體T101為導通狀態，使得第一驅動訊號Out'!由低準位電壓Vgl轉變為高準位電壓Vgh。而電晶體T103為 15 201032202 導通狀態，因此，電晶體T103輸出一第一移位訊號SS、，且第一移位訊號具有第二時脈訊號CK-Γ的高準位電壓 Vgh'，並作為第二級移位暫存單元之起始訊號。此外，請參考圖5至圖7以說明在第二時間t2時，第二級移位暫存單元之作動。在第二時間時，第二級移位暫存單元之第二驅動元件414接收到第一移位訊號SS、作為其起始訊號STV'，但第三時脈訊號CK2'及第四時脈訊號 • CK-21皆為低準位電壓Vgl，故其節點P’之電壓訊號=Vp'^Vgh' - VA + AVp', and AVp' = [Cb, / (Cb' + Cp)] X (Vgh - Vgl) where Vth is the threshold voltage of the transistor T102, and Cp is connected to the P The parasitic capacitance of the point, such as Cgs and Cgd. Since the second shift signal SS'2 is still the low level voltage Vgl, the transistor T104, the transistor T105, and the transistor T106 are still turned off. Since the transistor T101 is in an on state, the first driving signal Out'! is converted from the low level voltage Vgl to the high level voltage Vgh. The transistor T103 is in the on state of 15 201032202. Therefore, the transistor T103 outputs a first shift signal SS, and the first shift signal has a high level voltage Vgh' of the second clock signal CK-Γ, and The second stage shifts the start signal of the temporary storage unit. Further, please refer to Figs. 5 to 7 to illustrate the operation of the second stage shift register unit at the second time t2. At the second time, the second driving component 414 of the second stage shift register unit receives the first shift signal SS as its start signal STV', but the third clock signal CK2' and the fourth clock. Signal • CK-21 is the low level voltage Vgl, so the voltage signal of its node P' =

Vgh' —Vth，其中，Vth為第二級移位暫存單元的電晶體 T102之臨限電壓。而第二驅動訊號Out'2及第二移位訊號 SS'2W是低準位電壓Vgl。然後，於第三時間t3時，第三時脈訊號CK2'為高準位電壓Vgh，第四時脈訊號CK1為高準位電壓Vgh'，因此，第二級移位暫存單元的節點P'的電壓訊號Vp'如下：乂卩’二乂呂!!1 —Vth+AVp1，而 ❿ AVp'=【Cb' (Cb，+Cp)】X ( Vgh —Vgl) 其中，Vth為第二級移位暫存單元的電晶體T102之臨限電壓，而Cp包含第二級移位暫存單元電晶體T101的寄生電容，例如Cgs及Cgd。因為第三移位訊號SS'3是低準位電壓Vgl，故第二級移位暫存單元之電晶體T104、電晶體T105及電晶體T106為截止狀態。而第二驅動訊號Out’2 將由低準位電壓Vgl轉變為高準位電壓Vgh。第二級移位暫存單元之電晶體T103為導通狀態，因此，第二級移位暫存單元電晶體T103輸出一第二移位訊號SS'2為高準位 16 201032202 電壓Vgh'，並成為第三級移位暫存單元之第三驅動元件 417的起始訊號，同時亦成為第一級移位暫存單元之下拉元件413所耦接之訊號。在第三時間t3，對第一級移位暫存單元而言，第二移位訊號SS'2為高準位電壓Vgh'導致其下拉元件413的電晶體T104、電晶體T105及電晶體T106為導通狀態而放電。因此，於第三時間t3時，第一級移位暫存單元輸出的第一驅動訊號Out、、第一移位訊號SS'!及節點P'的電壓訊號 Vp'將因放電而成為低準位電壓Vg卜而電晶體Τ1(Π、Τ102 及Τ103為截止狀態。因此，如圖6及圖7所示，當移位暫存單元於第一時間tl接收一起始訊號STV'後，第一級移位暫存單元之驅動訊號Out’！於第二時間t2時輸出為高準位電壓Vgh，而第二級移位暫存單元之驅動訊號〇ut'2於第三時間t3時輸出為高準位電壓Vgh'，第三級移位暫存單元的驅動訊號 ❿ Out'3於第四時間t4輸出為高準位電壓Vgh'，以分別依序地驅動其對應之掃描線。此外，移位訊號亦於不同時間，依序地輸出高準位電壓Vgh'以成為下一級的起始訊號並導通前一級之下拉元件而使前一級的驅動訊號變為低準位。承上所述，在一移位暫存單元之電路中，當電晶體 T101處於導通狀態時是操作於線性區，而電晶體T101的汲極電流iD公式如下： iD=pnC0XW/2Lx【2χ (VGS-Vth) xVDS —VDS2】（式 3) 17 201032202 當汲極電流iD越大時，其推動負載的能力越強，如式 3所示，電晶體T101的推力與閘極與源極電位差VGS成正比。在本實施例中，因高準位電壓Vgh'大於習知的Vgh，與習知技術相較，節點F的電壓訊號Vp'將提高更多，又電壓訊號Vp'為電晶體T101的控制端電壓，進而提高電晶體T101的Vgs與》及極電流’因此本貫施例將使電晶體 T101的推力大幅提尚，因而縮短掃描線的的驅動訊號之上升時間，進而改善畫素電極充電不足所引起的色差現象。另外，因下一級的移位訊號係用以導通電晶體T104、電晶體T105及電晶體T106的閘極，而使驅動訊號由高準位變成低準位，而下一級的移位訊號的電壓是較高準位電壓Vgh'。因此，與習知技術相較，本實施例將使掃描線之驅動訊號放電更快而縮短其下降時間，進而改善晝素電極因放電時間太長所引起的混色現象。除此之外，在功率損耗方面，若如習知技術直接將第 ⑩ 一時脈訊號CK1的南低電壓準位差提南50%’即將Vg wing =(Vgh— Vgl)提高50%，則由式2可知功率損耗P也將提高50%。但本實施例於圖6中，加入一電晶體T103，則功率損耗P'之公式將成為： P' = VDDxIAVE = V〇D ( CbufferxVswiNG + CsxV’SWIN.G ) x1/2xFcl〇ck (式 4) 其中，匸心伽與Cs分別為電晶體T101及電晶體T103 的寄生電容Cgd_T101與Cgd_T103 ’而V'SWING為第二時脈訊號CK-Γ的高低電壓準位差，即V' SWING = (Vgh’一Vgl)。 18 201032202 若將V'swmG提高50%，且使電晶體T103的尺寸遠小於電晶體T101的尺寸，例如1 : 10，則Cs等於Cbuffer的10%，因此，式4的功率損耗P1將只提高1/10x150%= 15%。與習知技術直接將第一時脈訊號CK1的高低電壓準位差提高50%相較，本實施例的功率損耗可節省35%。承上所述，依據本發明第一實施例之移位暫存單元，其係藉由提高起始訊號之電壓準位差以及提供移位訊號之第二時脈訊號的電壓準位差，使電晶體的推力升高以縮短驅動訊號的上升時間，與習知技術比較，可以避免顯示面板發生色差現象。另外，本實施例更可快速地將驅動訊號拉至低準位，以避免顯示面板發生混色現象，而且功率損耗可較傳統設計大幅減少。此外，本實施例不藉由增加電容值來提升驅動能力，故可縮小額緣寬度或降低驅動電路的成本。第二實施例請參照圖8所示，其係為本發明第二實施例之移位暫存單元之電路示意圖。移位暫存單元61包含一第一驅動元件611、一第一移位元件612以及一第一下拉元件613。其中，第一驅動元件611與第一實施例主要不同在於：第一驅動元件611更包含一電晶體T206,其控制端耦接第四時脈訊號CK-2"，其第一端耦接起始訊號STV"，第二端耦接電壓訊號Vp"(節點Ρπ的電壓）。電晶體T206係與電晶體Τ201及Τ203電性連接，藉由電晶體Τ206可提升第一驅動元件611及第一移位元件612之效能。 19 201032202 另：’本實施例之第一下拉元件613較第一實施例之包含更多的電子元件，並除了由下一級、*子單兀所輸出之一第二移位訊號來控制之外，更脈訊號似所控制。第—下拉元件613包含電 ::、，T2〇5、電晶體—電晶體T·、電曰曰體Τ·、電晶體·、電晶體㈤、電晶體丁212、電晶體Τ213、電晶體Τ214以及電晶體Τ215。第一下拉元件 613之作動可參考第一實施例，故於此不再贅述。本實施例之第-下拉元件⑴藉由更多的電晶體以使掃描線之驅動訊號放電更快而縮短其下降時間，進而改善晝素電極因放電時間太長所引起的混色現象。Vgh' - Vth, where Vth is the threshold voltage of the transistor T102 of the second stage shift register unit. The second driving signal Out'2 and the second shift signal SS'2W are low level voltages Vgl. Then, at the third time t3, the third clock signal CK2' is the high level voltage Vgh, and the fourth clock signal CK1 is the high level voltage Vgh'. Therefore, the node P of the second stage shift register unit 'The voltage signal Vp' is as follows: 乂卩 '二乂吕!! 1 —Vth+AVp1, and ❿ AVp'=[Cb' (Cb,+Cp)]X ( Vgh —Vgl) where Vth is the second level The threshold voltage of the transistor T102 of the temporary storage unit is shifted, and Cp includes the parasitic capacitance of the second stage shift register unit transistor T101, such as Cgs and Cgd. Since the third shift signal SS'3 is the low level voltage Vgl, the transistor T104, the transistor T105 and the transistor T106 of the second stage shift register unit are in an off state. The second driving signal Out'2 will be converted from the low level voltage Vgl to the high level voltage Vgh. The transistor T103 of the second stage shift register unit is in an on state. Therefore, the second stage shift register unit transistor T103 outputs a second shift signal SS'2 to a high level 16 201032202 voltage Vgh', and The start signal of the third driving component 417 of the third-stage shift register unit is also the signal coupled to the pull-down component 413 of the first-stage shift register unit. At the third time t3, for the first stage shift register unit, the second shift signal SS'2 is the high level voltage Vgh', resulting in the transistor T104, the transistor T105 and the transistor T106 of the pull-down element 413. Discharges for the on state. Therefore, at the third time t3, the first driving signal Out outputted by the first-stage shift register unit, the first shift signal SS'!, and the voltage signal Vp' of the node P' will become low-level due to discharge. The bit voltage Vg and the transistor Τ1 (Π, Τ102, and Τ103 are off states. Therefore, as shown in FIG. 6 and FIG. 7, after the shift register unit receives a start signal STV' at the first time t1, the first The driving signal Out'! of the stage shift register unit is output as the high level voltage Vgh at the second time t2, and the driving signal 〇ut'2 of the second stage shift register unit is output as the third time t3. The high level voltage Vgh', the driving signal ❿ Out'3 of the third stage shift register unit is outputted to the high level voltage Vgh' at the fourth time t4 to sequentially drive the corresponding scan lines thereof. The shift signal also outputs the high level voltage Vgh' sequentially at different times to become the start signal of the next stage and turn on the lower stage pull element to turn the drive signal of the previous stage into a low level. In a circuit of a shift register unit, when the transistor T101 is in an on state, it operates The region, and the threshold current iD of the transistor T101 is as follows: iD=pnC0XW/2Lx[2χ (VGS-Vth) xVDS —VDS2] (Equation 3) 17 201032202 When the drain current iD is larger, it pushes the load. The stronger the capability, as shown in Equation 3, the thrust of the transistor T101 is proportional to the gate-source potential difference VGS. In the present embodiment, since the high-level voltage Vgh' is larger than the conventional Vgh, it is compared with the conventional technology. In comparison, the voltage signal Vp' of the node F will be increased more, and the voltage signal Vp' is the control terminal voltage of the transistor T101, thereby increasing the Vgs and the "pole current" of the transistor T101. Therefore, the present embodiment will make the transistor The thrust of the T101 is greatly increased, thus shortening the rise time of the driving signal of the scanning line, thereby improving the chromatic aberration caused by insufficient charging of the pixel electrode. In addition, since the shift signal of the next stage is used to conduct the transistor T104, electricity The gates of the crystal T105 and the transistor T106 change the driving signal from the high level to the low level, and the voltage of the shift signal of the next stage is the higher level voltage Vgh'. Therefore, compared with the prior art, This embodiment will put the driving signal of the scan line The electric power is faster and shortens the falling time, thereby improving the color mixing phenomenon caused by the discharge time of the halogen electrode. In addition, in terms of power loss, if the conventional technology directly directly turns the south of the 10th clock signal CK1 If the voltage level difference is 50%, that is, Vg wing = (Vgh - Vgl) is increased by 50%, then the power loss P will be increased by 50% from Equation 2. However, in this embodiment, a transistor T103 is added. , the formula of the power loss P' will be: P' = VDDxIAVE = V〇D (CbufferxVswiNG + CsxV'SWIN.G) x1/2xFcl〇ck (Formula 4) where 匸心伽 and Cs are respectively transistor T101 and The parasitic capacitances Cgd_T101 and Cgd_T103' of the transistor T103 and V'SWING are the high and low voltage level differences of the second clock signal CK-Γ, that is, V' SWING = (Vgh' - Vgl). 18 201032202 If V'swmG is increased by 50% and the size of transistor T103 is much smaller than the size of transistor T101, for example 1:10, then Cs is equal to 10% of Cbuffer. Therefore, the power loss P1 of Equation 4 will only increase. 1/10x150% = 15%. Compared with the prior art, the power loss of the first clock signal CK1 is directly increased by 50%, and the power loss of the embodiment can be saved by 35%. According to the first embodiment of the present invention, the shift register unit is configured to improve the voltage level difference of the start signal and the voltage level difference of the second clock signal for providing the shift signal. The thrust of the transistor is increased to shorten the rise time of the driving signal, and the chromatic aberration of the display panel can be avoided as compared with the prior art. In addition, the embodiment can quickly pull the driving signal to a low level to avoid color mixing of the display panel, and the power loss can be greatly reduced compared with the conventional design. In addition, the present embodiment does not increase the driving capability by increasing the capacitance value, so that the margin width can be reduced or the cost of the driving circuit can be reduced. SECOND EMBODIMENT Referring to Figure 8, there is shown a circuit diagram of a shift register unit in accordance with a second embodiment of the present invention. The shift register unit 61 includes a first driving element 611, a first shifting element 612, and a first pull-down element 613. The first driving component 611 is mainly different from the first embodiment in that the first driving component 611 further includes a transistor T206, and the control terminal is coupled to the fourth clock signal CK-2" The initial signal STV", the second end is coupled to the voltage signal Vp" (the voltage of the node Ρπ). The transistor T206 is electrically connected to the transistors 201 and 203, and the performance of the first driving element 611 and the first shifting element 612 can be improved by the transistor 206. 19 201032202 Further: 'The first pull-down element 613 of this embodiment contains more electronic components than the first embodiment, and is controlled by a second shift signal outputted by the next stage and * sub-units. In addition, the more pulse signal seems to be controlled. The first-pull-down element 613 includes electric::, T2〇5, transistor-transistor T·, electro-optical body, transistor, transistor (5), transistor D, transistor 213, transistor 214 And a transistor 215. The operation of the first pull-down component 613 can be referred to the first embodiment, and thus will not be described herein. The first-pull-down element (1) of the present embodiment shortens the fall time by discharging more of the driving signal of the scanning line by more transistors, thereby improving the color mixing phenomenon caused by the discharge time of the halogen electrode being too long.

本發明並不限定以四個時脈訊號驅動，任何驅動方式’、要起始汛旒與提供移位訊號之時脈訊號之準位差大於提供驅動訊號之時脈訊號的準位差皆包含在本發明申請專利範圍内。以下將以實際模擬結果來印證本發明之效能。請參照圖8之移位暫存單元61與圖9之移位暫存單元]。在圖 8與圖9 ^，兩者電路架構相同，差別在於圖8的起始訊说stv、第—日寸脈訊號Cic、in及第四時脈訊號u之高準位為35V巾低準位為_7乂，而第一時脈訊號ckim及第二時脈— 虎CK2”之高準位為册，低準位為_7¥ ;而圖9 的起始5fmTv'第-時脈訊號CK1及第三時脈訊號CK2 之最回準位為2GV ’低準位為_7V，且沒有第二時脈訊號 CK-i及第四時脈讯號CK>_2，而分別以第一時脈訊號㈤ 20 201032202 及第二時脈訊號CK2代替。另外，電晶體t2〇4、電晶體 T205以及電晶體T210之控制端的控制方式也不同，圖8 之移位暫存單7G 61是利用下一級的移位訊號來控制，而圖9之移位暫存71 {以下一級的輸出之驅動訊號來控制。請參照圖10所示，圖1〇為圖8與圖9之節點p"及節點P之電壓訊號Vpn與Vp之訊號比較圖。其中，橫軸代 • 表時間（微秒縱軸代表電壓（伏特）之強度。此圖中可明顯看出圖8之節點P"的電壓訊號比圖9之節點p高出很多，其中，節點p"的最高準位電壓約為54v，而節點p 的最高準位電壓約只有40V左右。請參照® 11，圖n為目8與圖9之移位訊號的比較圖。其中，橫軸代表時間（微秒），縱軸代表電壓（伏特）之強度。圖8電路圖的移位訊號為ss"，而圖9電路圖的移位訊號是ss。此圖中可明顯看出圖8之移位訊號ss，· • 比圖9之移位訊號SS高出很多，其中圖8之移位訊號ss，，的最高準位電壓約為36V，而圖9之移位訊號ss的最高準位電壓只有20V左右。 ,參照圖12,圖12為圖8與圖9輸出之驅動訊號的比較圖。其中，橫軸代表時間（微秒），縱軸代表電壓（伏特）之強度。圖8電路圖的驅動訊號為0ut"，而圖9電路圖的驅動訊號是〇ut。此圖中可明顯看出圖8之驅動訊號比圖9之驅動訊號更快地將電壓提升至高準位，且更快地將電壓拉下至低準位。 ' 21 201032202 综上所述，依據本發明之移位暫存器、掃描驅動電路及顯示裝置，其係藉由提高起始訊號之電壓準位差及第二時脈訊號之電壓準位差，使緩衝電晶體的推力升高以縮短驅動訊號的上升時間，與習知技術相比，可以避免顯示面板發生色差現象。另外，本發明更可快速地將驅動訊號降至低準位以縮短放電時間，避免顯示面板發生混色現象，而且，功率損耗可較傳統設計大幅減少，又可縮小額緣寬 0 度或降低驅動電路成本。以上所述僅為舉例性，而非為限制性者。任何未脫離本發明之精神與範疇，而對其進行之等效修改或變更，均應包含於後附之申請專利範圍中。【圖式簡單說明】圖1係為一種習知移位暫存器的示意圖；圖2係為一種習知移位暫存單元的電路示意圖； ❿ 圖3係為一種習知移位暫存單元的訊號示意圖；圖4係為本發明較佳實施例之顯示裝置的示意圖；圖5係為本發明較佳實施例之移位暫存器的示意圖；圖6係為本發明第一實施例之移位暫存單元的電路示意圖；圖7係為本發明第一實施例之移位暫存單元的訊號示意圖；圖8係為本發明第二實施例之移位暫存單元的電路示意圖； 22 201032202 圖9係為與本發明第二實施例移位暫存單元比較之移位暫存單元的電路示意圖；圖10係為圖8與圖9之節點P"及節點P之電壓訊號的比較示意圖；圖11係為圖8與圖9之移位訊號的比較示意圖；以及圖12係為圖8與圖9之驅動訊號的比較示意圖。【主要元件符號說明】 I、 41 :移位暫存器 II、 12、13、14、61、71 :移位暫存單元 2 :顯示裝置 3 :顯示面板 4:掃描驅動電路 410、411、414、417、611、711 :驅動元件 412、 415、418、41A、612、712 :移位元件 413、 416、419、41B、613、713 :下拉元件 5:資料驅動電路The invention is not limited to being driven by four clock signals. In any driving mode, the level difference between the clock signal to be started and the clock signal for providing the shift signal is greater than the level difference of the clock signal for providing the driving signal. Within the scope of the patent application of the present invention. The performance of the present invention will be confirmed by actual simulation results below. Please refer to the shift register unit 61 of FIG. 8 and the shift register unit of FIG. 9. In Figure 8 and Figure 9, the circuit structure is the same. The difference is that the high-level of the starting message stv, the first-day pulse signal Cic, in and the fourth clock signal u in Figure 8 is 35V. The bit is _7乂, and the high level of the first clock signal ckim and the second clock—the tiger CK2” is the book, the low level is _7¥; and the starting 5fmTv' first-clock signal of Figure 9 The most backward level of CK1 and the third clock signal CK2 is 2GV 'the low level is _7V, and there is no second clock signal CK-i and fourth clock signal CK>_2, respectively, and the first time The pulse signal (5) 20 201032202 and the second clock signal CK2 are replaced. In addition, the control methods of the transistor t2〇4, the transistor T205 and the transistor T210 are also different, and the shift temporary storage 7G 61 of Fig. 8 utilizes the next stage. The shift signal is controlled, and the shift register of FIG. 9 is controlled by the drive signal of the output of the following level. Referring to FIG. 10, FIG. 1 is the node p" and node P of FIG. 8 and FIG. The voltage signal Vpn and Vp signal comparison diagram, wherein the horizontal axis represents the table time (the microsecond vertical axis represents the intensity of the voltage (volts). It is obvious in this figure. The voltage signal of the node P" of 8 is much higher than the node p of Fig. 9, wherein the highest level voltage of the node p" is about 54v, and the highest level voltage of the node p is only about 40V. Please refer to the ®11. Figure n is a comparison of the shift signals of items 8 and 9. In which the horizontal axis represents time (microseconds) and the vertical axis represents the intensity of voltage (volts). The shift signal of the circuit diagram of Fig. 8 is ss" 9 The shift signal of the circuit diagram is ss. It can be clearly seen in this figure that the shift signal ss of Fig. 8 is much higher than the shift signal SS of Fig. 9, wherein the shift signal ss of Fig. 8 is the highest. The level voltage is about 36V, and the highest level voltage of the shift signal ss of Fig. 9 is only about 20V. Referring to Fig. 12, Fig. 12 is a comparison diagram of the driving signals outputted in Fig. 8 and Fig. 9. Time (microseconds), the vertical axis represents the strength of the voltage (volts). The driving signal of the circuit diagram of Figure 8 is 0ut", and the driving signal of the circuit diagram of Figure 9 is 〇ut. The driving signal ratio of Figure 8 is apparent in this figure. The drive signal in Figure 9 raises the voltage to a high level faster and pushes the voltage faster. Pulling down to a low level. ' 21 201032202 In summary, the shift register, the scan driving circuit and the display device according to the present invention improve the voltage level difference and the second clock of the start signal. The voltage level difference of the signal increases the thrust of the buffer transistor to shorten the rise time of the driving signal, and the chromatic aberration of the display panel can be avoided compared with the prior art. In addition, the invention can quickly reduce the driving signal. The low level is used to shorten the discharge time and avoid the color mixture of the display panel. Moreover, the power loss can be greatly reduced compared with the conventional design, and the edge width can be reduced by 0 degrees or the driving circuit cost can be reduced. The above is intended to be illustrative only and not limiting. Any equivalent modifications or alterations to the spirit and scope of the present invention are intended to be included in the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of a conventional shift register; FIG. 2 is a schematic diagram of a conventional shift register unit; ❿ FIG. 3 is a conventional shift register unit FIG. 4 is a schematic diagram of a display device according to a preferred embodiment of the present invention; FIG. 5 is a schematic diagram of a shift register according to a preferred embodiment of the present invention; FIG. 6 is a first embodiment of the present invention; FIG. 7 is a schematic diagram of a signal of a shift temporary storage unit according to a first embodiment of the present invention; FIG. 8 is a circuit diagram of a shift temporary storage unit according to a second embodiment of the present invention; 201032202 FIG. 9 is a schematic circuit diagram of a shift temporary storage unit compared with the shift temporary storage unit of the second embodiment of the present invention; FIG. 10 is a schematic diagram of voltage comparison between the node P" and the node P of FIG. 8 and FIG. FIG. 11 is a schematic diagram of comparison of the shift signals of FIG. 8 and FIG. 9; and FIG. 12 is a schematic diagram of comparison of the driving signals of FIG. 8 and FIG. [Description of Main Component Symbols] I, 41: Shift Registers II, 12, 13, 14, 61, 71: Shift Temporary Unit 2: Display Device 3: Display Panel 4: Scan Drive Circuits 410, 411, 414 , 417, 611, 711: drive elements 412, 415, 418, 41A, 612, 712: shift elements 413, 416, 419, 41B, 613, 713: pull-down element 5: data drive circuit

Cb、Cb'、Cbn :電容器 CK、CIU、CK1'、CKln、CK2、CK2'、CK2"、CK-Γ、CK-r'、 CK-2'、CK-2n :時脈訊號 D21〜D2n :資料線Cb, Cb', Cbn: capacitors CK, CIU, CK1', CKln, CK2, CK2', CK2", CK-Γ, CK-r', CK-2', CK-2n: clock signals D21 to D2n: Data line

Out] ' Out2 ' Out3 ' Out4 ' OutN_! ' OutN ' OutN+i ' Out'i ' Out'2、Out'3、Out'4、Out''〗、Out、Out":驅動訊號 23 201032202 P、P,、Ρπ :節點 Reset :重置訊號 ' S21、S22、S23、S24、§21 〜S2m :掃描線 SSi、SSS、SS'2、SS'3、SS'4、SS、、SSM2、SS、SS":移位訊號 STV、STV1、STV":起始訊號 tl、t2、t3、t4 :時間 ΊΠ、T2、T3、T4、Τ1(Π、T102、T103、T104、T105、T106、 φ Τ201、Τ202、Τ203、Τ204、Τ205、Τ206、Τ207、Τ208、 Τ209、Τ210、Τ211、Τ212、Τ213、Τ214、Τ215 :電晶體Out] ' Out2 ' Out3 ' Out4 ' OutN_! ' OutN ' OutN+i ' Out'i ' Out'2, Out'3, Out'4, Out'', Out, Out": Drive Signal 23 201032202 P, P,, Ρπ: Node Reset: reset signal 'S21, S22, S23, S24, §21~S2m: scan lines SSi, SSS, SS'2, SS'3, SS'4, SS, SSM2, SS, SS": Shift signal STV, STV1, STV": start signal tl, t2, t3, t4: time ΊΠ, T2, T3, T4, Τ1 (Π, T102, T103, T104, T105, T106, φ Τ201, Τ202, Τ203, Τ204, Τ205, Τ206, Τ207, Τ208, Τ209, Τ210, Τ211, Τ212, Τ213, Τ214, Τ215: transistor

Vgh、Vgh'、Vghn :高準位電壓Vgh, Vgh', Vghn: high level voltage

Vgl :低準位電壓Vgl: low level voltage

Vp、Vp'、Vpn :電壓訊號 V s s :參考電位Vp, Vp', Vpn: voltage signal V s s : reference potential

24twenty four

Claims

201032202 VII. Patent application scope: A shift register, having a plurality of shift register units, wherein a first stage shift register unit has a first drive element, according to a first clock signal And a start signal outputting a first driving signal;

a first shifting component is electrically connected to the first driving component, and outputs a first shifting signal according to the start signal and a second clock signal as a starting point of the shift register unit of the next stage The signal, one of the initial signal difference and one of the second clock signals has a level difference that is greater than one of the first clock signals. [2] The shift register according to claim 1, wherein the first driving component generates a voltage signal having a first level according to the start signal, at a second time. The first driving unit sends the voltage signal to the second signal according to the first clock signal, so that the first driving component inputs the driving signal according to the first clock signal. 3. The shift register according to item 2 of the patent application scope, wherein a driving component comprises: /, a T-different electric b-body, the control end is configured to receive the voltage signal, and ^ is used to receive the first a clock signal, the second end of which is used for outputting the first driving signal; and a control terminal thereof is electrically connected and receives the shifting device (4) as described in claim 3, wherein the 25th 201032202 driving component The method further includes: -m: the first end of the first transistor is electrically connected to the first end of the first transistor for coupling the voltage signal. 5. The application of the shift register according to item 2 of the patent scope, wherein the driving element is caused to rise to the second level according to the first clock signal, and the first shift is caused. The first shift signal is output according to a clock signal. For example, please turn _ the movement mentioned in item 5 (4). The first shifting component contains: /, Τ 弟其其其其其其其其其其其其其其其其其其其其其其其其其其其其其其其其'The second end of the second line is used to send the first - shift signal. The device 'and the first driving element and the second electrical property' are controlled by the shift register unit of the next stage. The shift register according to the seventh item, wherein the lower-four body has a control end for receiving the second shift signal-end system for transferring the reference potential; - H: the control terminal is configured to receive the second shift signal system for coupling the voltage signal, and the second end system 26 201032202 is coupled to the reference potential; and the ΤΓΓ: / control terminal is used for Receiving the second shift signal 9

: 俜 lightly connect the first shift signal, and the second is to couple a reference potential. ^申清专(4)(4)] shifting temporary storage ^, wherein the level shifting temporary storage unit further comprises: Μ - I pull component 'connected to the first driving component and the first shifting element 'And controlled by the system-shift signal output by the lower-level shift register unit and the received - third clock signal, as claimed in the patent scope! The shift register described in the item further comprises: a second stage shift register unit, which is a level below the first stage shift register unit, and has: - a second drive element, according to one The third clock signal and the start signal output-second driving signal, wherein the third clock signal is inverted from the first clock signal; and the first shifting component is electrically connected to the second driving component Connecting, and outputting a second shift signal according to the start signal and a fourth clock signal as a start signal of a lower-level shift register unit, the fourth clock signal and the second clock The signal is inverted, and one of the initial signal difference and one of the fourth clock signals has a level difference greater than one of the third clock signals. A scan driving circuit has a plurality of shifting temporary storage units, and each shifting temporary storage unit is matched with a scan line, wherein - the first stage shift 27 201032202 the temporary storage unit has: a first driving element, according to a The first clock signal and a start signal output a first driving signal to enable a first scanning line to output a first scanning signal;

a first shifting component is electrically connected to the first driving component, and outputs a first shifting signal according to the start signal and a second clock signal as a starting point of the shift register unit of the next stage The signal, one of the initial signal difference and one of the second clock signals has a level difference greater than one of the first clock signals. 12. The scanning drive circuit of claim 4, wherein, in a first time, the first driving component generates a voltage signal having a first level according to the start signal, in a second time. The first driving component raises the voltage signal to a second level according to the first clock signal, so that the first driving component outputs the first driving signal according to the number. ^ 。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。 One end is configured to receive the first clock signal, and the second end of the second transistor (4) is used for outputting, and the first end is electrically connected to the control end thereof and receives two: two Bucket: The second end is used to couple the electric dust signal. The scan drive circuit of the 13th item, wherein the X drive element further comprises: 28 14 201032202 15 container: the first end thereof is electrically connected to the second end of the first transistor, and the second The end is used to couple the voltage signal. And: applying the scanning according to item 12 of the patent scope: the moving circuit, and the time of the middle driving, the first driving component is raised to the second according to the first clock signal 16, so that the first shifting component is The second clock signal outputs the first bit = the scan driving circuit of the fifteenth patent scope, wherein the shifting component comprises: 17 a transistor whose control terminal is configured to receive the voltage signal, The first-shifting pulse (four) is rotated, and the second end is the scan_circuit according to the nth item of the 卞=s patent (4), wherein the first-stage shift register unit further includes: m: tt The second driving element and the first shifting element are connected to each other and controlled by a shift signal output by the lower-level shift register unit. The invention relates to a scan driving circuit according to item 17 of the luxury patent scope, wherein the 忒 pull-down component comprises: a fourth transistor, and a ^ Yue 丨嫂号 , , , , , , , , , , , , , , , , , , , , , , , , Connected to the first driving signal, the second body of the second body, the control end is configured to receive the second shifting signal r::, the terminal is used to connect the voltage signal, and the second end is used To couple a reference potential; and ', 29 201032202 a sixth transistor 'the control terminal is configured to receive the second shift signal', the first end of which is coupled to the first shift signal, the first The two ends are used to couple a reference potential. 19. The scan driving circuit of claim 2, wherein the first stage shift register unit further comprises: a pull-down element electrically coupled to the first driving element and the first shifting element The connection is controlled by the second shift signal outputted by the shift register unit of the next stage and the received one of the third clock signals. 20. The scan driving circuit of claim 11, further comprising: a second stage shift register unit, which is a level below the first stage shift register unit, and has: The second driving component outputs a second driving signal according to a third clock signal and the starting signal, so that a second scanning line outputs a second scanning signal, wherein the third clock signal and the first clock signal are The signal is inverted; and the first shifting component is electrically connected to the second driving component, and outputs a second shifting control signal according to the start signal and a fourth clock signal as the next shift The start signal of the temporary storage unit, the fourth clock signal is inverted with the second clock signal, and one of the start signal and one of the fourth clock signals is greater than the first One of the three-clock signal is a level difference. 21. A display device comprising: 30 201032202 a display panel; a data driving circuit connected to the display surface by a plurality of data lines; and a scan driving circuit, wherein the plurality of scans and the panel are electrically The connection has a plurality of shifting temporary storage units, and the shifting temporary storage units of each level are matched with the scanning lines, wherein a first stage shifting temporary storage unit-the first driving element is based on the -first clock signal and The start signal outputs a first-drive signal such that the first scan line outputs a first scan signal; and the first shift element is electrically connected to the first drive element, and is based on the start signal and a The second clock signal outputs a first shift signal as the start signal of the shift register unit of the next stage, and the level difference between the start signal and the second clock signal is greater than One of the first clock signals has a level difference. The display device of claim 21, wherein, at a first time, the first driving component generates a voltage signal having a _th-level according to the start signal, and at a second time, the first The driving device sends the voltage signal to a first level: a level of the first clock signal, so that the first crane component outputs the first driving signal according to the first clock signal. The display device of claim 22, wherein the first driving component comprises: a first transistor, wherein the control terminal is configured to receive the voltage signal, and the third end of the 31 23 201032202 is configured to receive the first time a first signal of the first driving signal; and a second transistor, wherein the first end and the control end thereof are electrically coupled to the start signal, and the second end is coupled to the second end, as described in claim 23 The display device - the drive component further includes:

The first end of the capacitor is electrically connected to the second end of the first transistor, and the first end is used to face the voltage signal. The display device of claim 22, wherein, at the second time, the first driving component raises the voltage signal to the second level according to the first clock signal, so that the The first shifting component outputs the first shift signal according to the second clock signal of δ. The display device of claim 25, wherein the first shifting element comprises: a first transistor, wherein the control end is configured to receive the voltage signal,

The second end is used to output the connection and receive the power signal. The first end is configured to receive the second clock signal, and the second end is configured to output the first shift signal. The display device of claim 21, wherein the first stage shift register unit further comprises: a pull-down element electrically connected to the first drive element and the first shift element And controlled by one of the second shift signals output by the shift register unit of the next stage. The display device of claim 27, wherein the pull-down component comprises: 32 201032202 a control terminal is configured to receive the second shift signal: the user: the end system is used to receive the a first driving signal, wherein the second knowledge is used to face a reference potential; a fifth transistor, the control end is for receiving the second displaced gas: the light signal is lightly connected to the voltage signal, The second end is used to connect a reference potential;

The first terminal is configured to receive the second shift signal, and the second end is coupled to a reference potential. The display-level shift register unit according to claim 21 of the patent application scope further comprises: - a medium-lower pull 7G piece, which is electrically connected to the first drive element and the first shift element 2, And controlled by the Z second shift signal output by the lower-level shift register unit and the received third clock signal

3〇, L—The display device described in claim 21, further comprising: a “second stage shift temporary storage unit” which is a lower level of the first stage shift temporary storage unit and has: The second driving unit outputs a second scanning signal according to the third clock signal and the initial signal output-second driving minus m line, wherein the third clock signal is opposite to the first clock signal And the first shifting component is electrically connected to the second driving component of the shai, and is output according to the start signal and a fourth clock signal—the second shift 33 201032202 bit control signal is used as the shift of the next stage The start signal of the temporary storage unit, the fourth clock signal is inverted with the second clock signal, and one of the start signal and one of the fourth clock signals is greater than the third One of the timing signals is a level difference.

34