201031195 開關 五、 本案若有化學式時，請揭示最能顯示發明特徵的化學式： 六、 發明說明： 【發明所屬之技術領域】 本發明係有關影像感測器’特別是關於一種複合垂直 像素共享（mUltiple_vertical_pixels_shariftg)影像感測 Φ 器的組合（binning)電路及方法。 【先前技術】 半導體影像感測器（例如電荷耦合元件（CCD)戈互 補金屬氧化半導體（CMOS)感測器）普遍使用於照相機 或攝影機中，用以將可見光之影像轉換為電子信號，便於 φ 後續之儲存、傳輸或顯示。 影像感測器的部分像素（或光二級體）可以共享一電 路，以減少整體電路的大小。共享架構可以採用垂直方式 (亦即，位於同一行的像素共享一電路），也可以採用水 平方式（亦即，位於同一列的像素共享一電路）。第一圖 顯示一傳統複合垂直像素共享 (nrnltiPle-vertical-pixels_sharing)影像感測器 4 201031195 其具有多組別（亦即 方式之像素共享電組料）_垂直共享 時，每ϋ測器内製作愈來愈多的像素(或光二級體) =_更佳的信號雜訊比： ❹ ::::)素)的信…相加(或稱為像二: 然而’對於前述傳統垂直共享之影像感測ϋ，若要跨 越不同組別以進行像素組合（binning)時將會遭遇困難， 除非增加-些額外的電路來解決。例如，於第—圖中，若 要於A組別内進行像素組合，只要將該組的相關傳輸閑 (transfergate) (tx—A一n，n=1,2 .)同時打開即可。 ❹然而，如果同打開A組別和B組別的傳輸閘（tx a n=l，2…），則在行（c〇iumn)節點（c〇1)處 將會造成信號之間的衝突。因此，對於傳統複合垂直像素 共享（multiple-vertical-pixels-sharing )影像感測器 1〇，其像素組合數目會受到很大的限制。 鎩於傳統影像感測器’例如第一圖所示的複合垂直像 素共享（multiple_vertical-pixels-sharing)影像感測器 5 201031195 10，無法有效地進行信號的組合’因此亟需提出一種可適 用於影像感測器（特別是複合垂直像素共享 (multiple-vertical-pixels-sharing)影像感測器）的新 穎組合（binning)電路及方法，用於跨越不同組別以進 行信號的組合。 【發明内容】 •鑑於上述’本發明的目的之一在於提出一種可適用於 影像感測器（特別是複合垂直像素共享 (multiple-vertica卜pixels-sharing)影像感測器）的 組合（binning)電路及方法，用於跨越不同組別以有效進 行信號的組合。 根據本發明特徵之一，首先，重置行放大器（CA)， ❹因而產生-CA 4置信號^耦接―電容及切換裝置於影像 感測器之輸出和行放大器之輸入間。控制關聯雙重= (CDS)電路，以接收行放大器之輸出。其中， 裝置使得影像感測器之第一組別影像信號被傳送:儲刀換 CDS電路’且第二組別的影像信號則被加到所錯^ :存於 組別影像信號。 子之第〜 201031195 根據本發明另一特徵，首先，重置一行放大器（CA), 用以產生一 CA重置信號。接收第一組別的重置信號，接 著使用行放大器以放大第一組別的影像信號，並儲存第一 組別的影像信號。接下來，接收第二組別的重置信號，接 著使用行放大器以放大第二組別的影像信號，並將其加到 所儲存之第一組別影像信號。 【實施方式】 第二圖顯示本發明實施例之組合（binning )電路20 .， 其適用於複合垂直像素共享 (multiple-vertical-pixels-sharing)影像感測器 22。 該複合垂直像素共享影像感測器22包含多個組別，例如a 組別（22A)、B組別（22B)，而各個組別則依垂直共 享方式個別共享一相關電路。影像感測器22可以是（但 不限定為）電荷耦合元件（CCD)或互補金屬氧化半導體 .今 (CMOS)感測器，用以將可見光之影像轉換為電子信號。 組合電路20的輸出可饋至一放大器（未顯示於圖式中）， 例如可程式增益放大器（programmable gain amplifier， PGA)。上述之影像感測器22及組合電路20可應用於數 位影像處理裝置中，例如（但不限定為）照相機或攝影機。 201031195 以A組別為例，影像感測器22的每一組別包含一重 置電晶體r st—A、—源極_ ϋ sf〜A、—選擇電晶體<A 及多個傳輸電晶體（或傳輸閘）。 為簡化起見，圖式中的電晶體（或開關）及其控制信號則 使用相同的符號，圖式中，當重置電晶體ma被開啟 時，可用以將光二級體(D一A」、D—A—2等）重置到一個 重置參考電壓。當源極_器被時，可用以_ 光 一級體（D—A 1、D A Q 璧、ϋ ~ )的影像信號。當選擇電晶 體seLA被字元線（word i 田迷擇電日日 )開啟時，則允許像素影像 訊號的讀出。當傳輸電晶體（tx ’、 時，可用以分別傳送光二級體⑺λ, _— 被開啟 ( H1、D-A-2等）的像 素衫像信號。重置電晶體rst A、 雷曰科! Λ 4+ ^ , 一 源極隨耦器sf-A和選擇 電曰曰體d、享於光二級體(d—a」、d 各 ❹ 組別“、B等)的輸出則共，性一一各 組合電路2〇係用於跨越不同組別( 且 ^以有效進行信號的組合1合電路2〇由各個組別㈣ 組合電路20主要包含一行放大器ca。迴授電容^則 搞，於行放大器CA的輪出和輪入之間。CA重置開關CArst t是相接於行放大器CA的輪出和輸入之間。行節點（c〇1) +由電今c及-切換裝置叫接至行放大的輸入。該 切換裝置包含第-開關phil及第二開關㈣。電容c的 8 201031195 第一極板耦接至行節點（col)，第一開關phn耦接於行 放大器CA輸入和電容c第二極板之間，而第二開關phi2 則搞接於電容C第二極板和地之間。 組合電路20更包含一關聯雙重取樣（correlated double sampling, CDS)電路，其包含一取樣-保持-重置 k 號（sample-and-hold-reset_signal，SHR)開關及一 Φ 取樣-保持-影像信號（sample-and-hold-image_signal， SHS)開關。SHR開關及SHS開關分別耦接至SHR電容 Cshr及SHS電容Cshs。其中，當SHR開關閉合（cl〇se) 時，重置信號即可被取樣並儲存保持於SHR電容Cshr。 當SHS開關閉合（close)時，影像信號即可被取樣並儲 存保持於SHS電容Cshs。再者，CDS電路還包含一開關 SW;當完成組合（binning)操作後，欲將SHR電容cSHR _ 和SHS電容Cshs内的信號饋至下一放大器（例如pGA) 時，此時將會開關SW予以閉合（cl〇se)。 ) 第三A圖至第三D圖顯示本發明實施例於進行組合操 作時各步驟的等效電路。第四圖顯示第二圖、第三A D圖的相關信號時序圖。第五圖則顯示本發明實施例組人 操作的流程圖。雖然本實施例以A組別和B組別進行组人 9 201031195 (binning)操作為例，然而，本發明也可適用於其他組 別的組合操作。 於進行組合操作時，首先，閉合CA重置開關CA_rst (1〇〇) ’用以將行放大器CA予以重置（步驟50)，如第 三A圖所示。SHR開關為閉合（1〇1)，使得CA重置信號 被儲存於SHR電容Cshr。於此階段，SHS開關也是閉合 ❹ 的（102)。實務上’主動SHR信號和主動SHS信號會 有一 #又重曼’其係為了防止麵合效應（c〇Upling effect)。 在另一實施例中，此階段的SHS開關係為開斷的。於此同 時，（A組別）重置電晶體rst_A被開啟（1〇3)，且選 擇電晶體sel_A也被開啟（104 )。接著，藉由閉合第二 開關phi2(l〇5)(但開斷第一開關phil)，使得A組 別的輸出重置信號被接收並儲存於電容C (步驟50)。 ❹ 接下來，如第三B圖所示，A組別的傳輸電晶體tx_A_n (n-1，2.··)被開啟（106) ’且第一開關phii被閉合 (107)，但是第二開關phi2則為開斷的（1〇8)。藉此， 行放大器CA的輸入電壓相當於（A組別）影像信號減去 所儲存的（A組別）重置信號’此輸入電壓接著受到行放 大器CA的放大（步驟51) ’此時的SHS開關持續閉合 201031195 著，但開斷SHR開關（1〇9 )。藉此，A組別的影像信號 因而儲存於SHS電容CSHS内。 接著，如第二c圖所示，（B組別）重置電晶體rst_B 被開啟（110)，且選擇電晶體sel_B&被開啟（111)。 接著’藉由閉合第二開關phi2 (i⑵（但開斷第一開關201031195 Switch 5. If there is a chemical formula in this case, please disclose the chemical formula that best shows the characteristics of the invention: 6. Description of the invention: [Technical field of the invention] The present invention relates to an image sensor 'in particular to a composite vertical pixel sharing ( mUltiple_vertical_pixels_shariftg) A binning circuit and method for image sensing Φ. [Prior Art] Semiconductor image sensors (such as charge coupled device (CCD) Ge complementary metal oxide semiconductor (CMOS) sensors) are commonly used in cameras or cameras to convert visible light into electronic signals for φ Subsequent storage, transmission or display. Some pixels (or optical diodes) of the image sensor can share a circuit to reduce the size of the overall circuit. The shared architecture can be in a vertical manner (i.e., pixels in the same row share a circuit) or horizontally (i.e., pixels in the same column share a circuit). The first figure shows a conventional composite vertical pixel sharing (nrnltiPle-vertical-pixels_sharing) image sensor 4 201031195 which has multiple groups (that is, a pixel sharing electric group material) _ vertical sharing, each in the detector More and more pixels (or light-level bodies) = _ better signal-to-noise ratio: ❹ ::::)) The letters ... add up (or called like two: However 'for the aforementioned traditional vertical sharing Image sensing, if you want to cross different groups for binning, you will encounter difficulties unless you add some extra circuits to solve. For example, in the first picture, if you want to do it in group A, Pixel combination, as long as the relevant transfer transfer (tx - A - n, n = 1, 2 .) of the group is simultaneously turned on. However, if the transfer gates of Group A and Group B are turned on ( Tx an=l,2...), at the line (c〇iumn) node (c〇1) will cause a collision between the signals. Therefore, for the traditional composite vertical pixel sharing (multiple-vertical-pixels-sharing) Image sensor 1〇, the number of pixel combinations will be greatly limited. Like a sensor, such as the composite vertical pixel sharing (multiple_vertical-pixels-sharing) image sensor 5 201031195 10 shown in the first figure, the combination of signals cannot be effectively performed. Therefore, it is necessary to propose a method suitable for image sensing. A novel binning circuit and method for multi-vertical-pixels-sharing image sensors for combining signals across different groups. [Summary] One of the above objects of the present invention is to provide a binning circuit and method applicable to an image sensor (particularly a multiple-vertica pixel-sharing image sensor) for Combining different groups to effectively combine signals. According to one of the features of the present invention, first, the row amplifier (CA) is reset, thereby generating a -CA 4 signal, coupling, capacitance, and switching device to the image sensor. Between the output and the input of the line amplifier. Controls the associated dual = (CDS) circuit to receive the output of the line amplifier. Among them, the device makes the image sensor A set of different image signals are transmitted: the knife is replaced by the CDS circuit' and the second group of image signals are added to the error ^: stored in the group image signal. Sub-No. 201031195 According to another feature of the present invention, first Resetting a row of amplifiers (CA) to generate a CA reset signal, receiving a first set of reset signals, then using a line amplifier to amplify the first set of image signals and storing the first set of images signal. Next, a second set of reset signals is received, followed by a line amplifier to amplify the second set of image signals and applied to the stored first set of image signals. [Embodiment] The second figure shows a binning circuit 20 of an embodiment of the present invention, which is suitable for a multiple-vertical-pixels-sharing image sensor 22. The composite vertical pixel shared image sensor 22 includes a plurality of groups, such as a group (22A) and a group B (22B), and each group individually shares a related circuit in a vertical sharing manner. The image sensor 22 can be, but is not limited to, a charge coupled device (CCD) or a complementary metal oxide semiconductor. A current (CMOS) sensor for converting an image of visible light into an electrical signal. The output of combinational circuit 20 can be fed to an amplifier (not shown), such as a programmable gain amplifier (PGA). The image sensor 22 and combination circuit 20 described above can be applied to a digital image processing device such as, but not limited to, a camera or a video camera. 201031195 Taking Group A as an example, each group of image sensors 22 includes a reset transistor r st-A, - source _ ϋ sf ~ A, - select transistor < A and multiple transmissions Crystal (or transfer gate). For the sake of simplicity, the transistor (or switch) and its control signals in the figure use the same symbol. In the figure, when the reset transistor ma is turned on, it can be used to light the diode (D-A). , D-A-2, etc.) reset to a reset reference voltage. When the source _ is received, the image signal of the _ light first stage (D-A 1, D A Q 璧, ϋ ~ ) can be used. When the electro-optic seLA is selected to be turned on by the word line (word i field selection day), the pixel image signal is allowed to be read. When transmitting the transistor (tx ', it can be used to respectively transmit the photodiode (7) λ, _- is turned on (H1, DA-2, etc.) the pixel image signal. Reset the transistor rst A, Thunder Branch! Λ 4 + ^ , a source follower sf-A and an electrified body d, enjoy the output of the light secondary body (d-a", d each group ", B, etc.) The combination circuit 2 is used to span different groups (and ^ to effectively combine the signals 1 circuit 2) by each group (four) combination circuit 20 mainly contains a row of amplifiers ca. Between the round-out and the round-in. The CA reset switch CArst t is connected between the turn-out and the input of the line amplifier CA. The row node (c〇1) + is connected to the line by the current c and - switching device The input device of the amplification includes a first switch phil and a second switch (four). The capacitor 10 has a first plate coupled to a row node (col), and the first switch phn is coupled to the line amplifier CA input and capacitor c. The second switch phi2 is connected between the second plate of the capacitor C and the ground. The combination circuit 20 further includes an associated double sampling. (correlated double sampling, CDS) circuit comprising a sample-and-hold-reset_signal (SHR) switch and a Φ-sample-and-hold-image signal (sample-and-hold-image_signal, SHS) switch. The SHR switch and the SHS switch are respectively coupled to the SHR capacitor Cshr and the SHS capacitor Cshs. When the SHR switch is closed (cl〇se), the reset signal can be sampled and stored and held in the SHR capacitor Cshr. When the SHS switch is closed, the image signal can be sampled and stored in the SHS capacitor Cshs. Furthermore, the CDS circuit also includes a switch SW; when the binning operation is completed, the SHR capacitors cSHR _ and SHS are to be used. When the signal in the capacitor Cshs is fed to the next amplifier (for example, pGA), the switch SW is closed (cl〇se) at this time.) The third to third figures D show the embodiment of the present invention when performing the combined operation. The equivalent circuit of each step. The fourth figure shows the related signal timing chart of the second figure and the third AD picture. The fifth figure shows the flow chart of the operation of the group of the embodiment of the present invention. Group B group 9 201031195 (binning) The operation is taken as an example, however, the present invention is also applicable to the combined operation of other groups. When performing the combined operation, first, the CA reset switch CA_rst (1〇〇) ' is closed to reset the line amplifier CA (step 50), as shown in Figure A. The SHR switch is closed (1〇1) so that the CA reset signal is stored in the SHR capacitor Cshr. At this stage, the SHS switch is also closed (102). In practice, the 'active SHR signal and the active SHS signal will have a #重重曼' in order to prevent the c〇Upling effect. In another embodiment, the SHS open relationship at this stage is open. At the same time, the (group A) reset transistor rst_A is turned on (1〇3), and the selected transistor sel_A is also turned on (104). Next, by closing the second switch phi2 (l〇5) (but breaking the first switch phil), the A group output reset signals are received and stored in the capacitor C (step 50). ❹ Next, as shown in the third B diagram, the transmission transistor tx_A_n (n-1, 2..·) of group A is turned on (106)' and the first switch phii is closed (107), but the second The switch phi2 is open (1〇8). Thereby, the input voltage of the line amplifier CA corresponds to the (group A) image signal minus the stored (group A) reset signal 'this input voltage is then amplified by the line amplifier CA (step 51)' The SHS switch continues to close 201031195, but the SHR switch (1〇9) is turned off. Thereby, the image signals of group A are thus stored in the SHS capacitor CSHS. Next, as shown in the second c-picture, the (group B) reset transistor rst_B is turned on (110), and the selected transistor sel_B& is turned on (111). Then 'by closing the second switch phi2 (i(2) (but breaking the first switch)
Phil)，使得b組別的輸出重置信號被接收並儲存於 〇 c (步驟 52)。 、 接下來’如第三D圖所示’ B組別的傳輪電晶體 tx—B_n(n=1，2.·.)被開啟（113)，且第一開關 被閉合（114)，但是第二開關_2則為開斷的（ι叫。 藉此’行放大器CA的輸入電壓相當於（B組別）影抑 號減去所儲存的（B組別）重置信號，此輪入電壓_ ❹到行放大器CA的放大，此時的開關持續閉= 開斷SHR開關。由於SHS開關持續閉合著，因而使得^ 組別的影像信號得以加（或組Mbinning))__ SHS電容Cshs的先前⑷且合）電壓（步驟叫而 完成信號組合之操作。 根據本發明實施例，於複合垂直像素共古 (niultiple-vertical-pixels-sharing)^,^,；^^ 201031195 可以跨越不同組別（例如圖式中的A組別及β組別）而有 效地進行信號的組合，不會產生信號之間的衝突。 以上所述僅為本發明之較佳實施例而已，並非用以限定 本發明之申請專利範圍；凡其它未脫離發明所揭示之精神 下所完成之等效改變或修飾，均應包含在下述之申請專利 範圍内。 【圖式簡單說明】 第一圖顯示一傳統複合垂直像素共享 (multiple-vertical-pixels_sharing)影像感測器。 第二圖顯示本發明實施例之組合（binning)電路，其適用 於複合 垂直像 素共享 鲁（multiPle-vertica卜pixeis-sharing)影像感測器。 第二A圖至第三d圖顯示本發明實施例於進行.組合操作 各步驟的等效電路。 第四圖顯示第二圖、第三A至三D圖的相關信號時序圖 第五圖顯示本發明實施例組合操作的流程®。 【主要元件符號說明】 10 複合垂直像素共享影像感測器 201031195 20 組合（binning)電路 22 影像感測器 22A、22B影像感測器的各組別 50-53 實施例流程步驟 100-115 相關信號的時間點 col 行節點 rst_A(B) 重置電晶體 ❹ sf_A(B) 源極隨耦器 sel_A (B) 選擇電晶體 tx_A(B)_n 傳輸電晶體（傳輸閘） D_A(B)_n 光二級體 CA 行放大器 Cf 迴授電容 C 電容 ❿ CA_rst CA重置開關 phil 第一開關 phi2 第二開關 SHR 取樣-保持-重置信號開關 SHS 取樣-保持-影像信號開關 CsHR SHR電容 CsHS SHS電容 sw 開關 13Phil), so that the output reset signal of group b is received and stored in 〇 c (step 52). Then, as shown in the third D diagram, the transmission transistor tx-B_n (n=1, 2...) of group B is turned on (113), and the first switch is closed (114), but The second switch _2 is turned off (1). The input voltage of the line amplifier CA is equivalent to the (group B) shadow minus the stored (group B) reset signal. The voltage _ 放大 is amplified by the line amplifier CA, and the switch at this time continues to be closed = the SHR switch is turned off. Since the SHS switch is continuously closed, the image signals of the group are added (or grouped by Mbinning) __ SHS capacitor Cshs The previous (4) concatenated voltage (steps to complete the operation of the signal combination. According to an embodiment of the invention, the niultiple-vertical-pixels-sharing ^, ^,; ^^ 201031195 can span different groups (For example, group A and group β in the figure), the combination of signals is effectively performed, and no conflict between signals occurs. The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention. The scope of the patent application of the invention; other things that have been completed without departing from the spirit of the invention Modifications or modifications are intended to be included in the scope of the following claims. [Simplified Schematic] The first figure shows a conventional composite vertical pixel sharing (multiple-vertical-pixels_sharing) image sensor. The second figure shows the implementation of the present invention. The binning circuit is applicable to a composite vertical pixel sharing multiplex (multiPle-vertica pixeis-sharing) image sensor. The second to third d-d diagrams show the embodiments of the present invention. The fourth circuit shows the flow chart of the correlation signal of the second diagram, the third A to the third D diagram. The fifth diagram shows the flow of the combination operation of the embodiment of the present invention. [Main component symbol description] 10 composite vertical pixel Shared image sensor 201031195 20 binning circuit 22 image sensor 22A, 22B image sensor group 50-53 embodiment process step 100-115 time point of related signal col row node rst_A (B) Reset transistor ❹ sf_A(B) Source follower sel_A (B) Select transistor tx_A(B)_n Transistor (transmission gate) D_A(B)_n Optical diode CA line amplifier Cf Feedback capacitance capacitor C ❿ CA_rst CA phil first reset switch switches the second switch SHR sample phi2 - Hold - reset signal sampling switches SHS - Hold - SHR CSHR video signal switch capacitance capacitor CsHS SHS switch sw 13