TW201029520A - Controller circuit of inverter using pulse width modulation (PWM) dimming - Google Patents

Abstract

A controller circuit of an inverter using pulse-width modulation (PWM) dimming includes a low-frequency (LF) timing capacitor, an LF oscillator, an LF PWM comparator, a feedback controller and an alternating-current (AC) generator. An output of the LF oscillator is coupled to the LF timing capacitor and an input of the LF PWM comparator, and an output of the LF PWM comparator is coupled to the feedback controller. The AC generator generates an AC current having appropriate magnitude and frequency to charge the LF timing capacitor. The charging current of the LF timing capacitor includes a direct-current (DC) current and the AC current. An LF ramp voltage generated at the output of the LF oscillator is fluctuated according to the magnitude of the AC current; and further, an LF PWM signal generated at the output of the LFPWM comparator is fluctuated according to the fluctuated LF ramp voltage. The fluctuated LF PWM signal is input to the feedback controller, and the spectrum of signal energy of the inverter is expanded to a wider frequency range; therefore, it improves electromagnetic interference (EMI) generated at the transition of an enable period and a disable period of the LF PWM signal.

Description

201029520 VI. Description of the Invention: [Technical Field] The present invention relates to an inverter control circuit, and more particularly to a Pulse Width Modulation (PWM) dimming The control circuit of the flow device. [Prior Art] FIG. 1A is a block diagram of a conventional power supply system of a cold cathode fluorescent lamp (CCFL). Referring to FIG. 1A, after the AC mains input is input to the conventional power supply system 1, the electromagnetic interference (ElectroMagnetic Interference, EMI) filter 11 filters out the noise, and then rectifies by the bridge rectifier 12 to become a DC ripple signal. In order to comply with the harmonic specification, the DC system pulse signal of the power system input power greater than 75W must be corrected by the Power Factor Corrector (PFC) 13 to correct the current harmonic distortion' to become a stable typical value of 4〇〇Vdc. The DC voltage Vbus is supplied to the standby power converter 14 and the main power converter 15. The standby power converter 14 changes the DC waste Vbus to a typical 5Vdc power supply, and supplies power to the main board in the standby mode (main Micro Controller Unit (MCU) to maintain the operation of the remote control receiver, and PFC 13 and the main power converter 15 is turned off to reduce standby power consumption. The main power converter 15 converts the DC voltage Vbus to a typical 12Vdc, 14Vdc or other voltage source for powering audio, video, control modules or other modules. And it becomes a power supply with a typical value of 24Vdc to supply power to the inverter 16. The inverter 16 changes the power supply of the typical value of 24Vdc provided by the main power converter 15 to the AC voltage Vlamp of a typical value of 1V to activate the CCFL, and The reduction from i8〇〇Vac to 800VV after startup is enough to stabilize the CCFL. In order to reduce manufacturing costs and improve conversion efficiency, a CIFL power supply system with Lips architecture was developed, where LIPS is the abbreviation of Led Integrated Power Supply. Block diagram of the CCFL power system for the existing LIPS architecture. Please refer to Figure 4 201029520 1A and Figure IB at the same time, no longer like the traditional power system! The inverter 16 is powered by the main power. The source converter i5 is powered, and the inverter 26 of the LIPS f source system 2 is directly powered by the typical 4 〇 的 电压 V V ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' The loss of conversion efficiency 'can reduce the design power of the main power converter 25 and the structure of the joint seam, the wind and heat problem and reduce the manufacturing cost. Since the ups power system 2 has less voltage regulation effect of the main power converter 25, The stability is relatively insufficient, especially when the inverter 26 uses pulse width modulation (p-long) dimming, excessive transient AC changes occur in the DC voltage Vbus provided by the pFCi3. ❹ Figure 2 is shown in Figure 1B. The waveform diagram of the input/output signal of the inverter 26 of the LIPS power supply system 2 is shown. Referring to FIG. 1B and FIG. 2 simultaneously, the inverter 26 uses PWM dimming, so the received dimming signal is the low frequency PWM signal Vlpwm. PWM dimming It is the most common dimming mode due to wide dimming range, good dimming linearity and easy circuit implementation. Each period T of the low-frequency pwM signal Vlpwm includes a uniform energy period Τ_0Ν and an inactive period T_0FF. T-0N, change The device 26 operates normally 'it generates an AC voltage viamp of frequency fh〇sc to drive the CCFL to illuminate (ie, brightens); and during the disable period t_〇FF, the inverter 26 does not operate, and the AC voltage Viamp is zero. CCFL illumination cannot be driven (ie darkening). The frequency f 10SC of the low-frequency PWM signal Vlpwm is usually designed to be higher than ι00Ηζ. Under the shadow of the human visual temporary memory, CCFL cannot be seen. You can see the change of light and dark, so you can achieve the purpose of dimming by adjusting the ratio of light and dark (that is, adjusting the ratio of Τ_0Ν during the enable period to the ratio of T_0FF during the disable period). Since the UPS power supply system 2 has less voltage regulation effect of the main power converter 25, when the inverter 26 uses PWM dimming, during the enable period of the low-frequency P-signal Vlpwm, the transition period Τ_0Ν and the disable period T_0FF are instantaneously changed. The streamer 26 instantaneously loads or unloads 'so that the DC voltage Vbus provided by the PFC 13 will exhibit excessive transient AC changes. The transient AC change of the DC voltage Vbus is easy to map the frequency of the AC change through the inductor in the PFC 13, and the EMI effect on the low frequency spectrum of the fundamental frequency of the band. SUMMARY OF THE INVENTION 5 201029520 The object of the present invention is to propose a control circuit for a converter using pulse width modulation dimming, which improves the conversion of the converter during both the enabling period and the inactive period of the low frequency pulse width modulation signal. Instant electromagnetic interference. In order to achieve the above and other objects, the present invention provides a control circuit for a converter using pulse width modulation dimming, which includes a low frequency timing circuit, a low frequency oscillator, a low frequency pulse width modulation comparator, a feedback control circuit, and an alternating current. Signal generator. The low frequency timing circuit includes a low frequency timing resistor and a low frequency timing capacitor. The low frequency timing resistor determines the magnitude of the direct current and the direct current is used to charge the low frequency timing capacitor. The low frequency timing capacitor has a first end and a second end and the second end is coupled to Ground potential. The low frequency oscillator has an output coupled to the low frequency timing resistor and the first end of the low frequency timing capacitor. The low frequency oscillator control low frequency timing capacitor is repeatedly charged and discharged to generate a low frequency ramp voltage at the first end of the low frequency timing capacitor. The low frequency pulse width modulation comparator has a first input end, a second input end and an output end. The first input end of the low frequency pulse width modulation comparator receives the DC dimming signal, and the low frequency pulse width modulation comparator is coupled to the second input end. Connected to the first end of the low frequency timing capacitor, a low frequency pulse width modulation signal is generated at the output of the low frequency pulse width modulation comparator, wherein the low frequency pulse width modulation signal includes a uniform energy period and an inactive period. The feedback control circuit has an enable end and an output end, and the feedback control circuit enable end is coupled to the output end of the low frequency pulse width modulation comparator, and generates a drive signal at the output of the feedback control circuit during the enable period. During the energy period, no drive signal is generated at the output of the feedback control circuit, wherein the drive signal is used to drive the switching of the switch circuit in the inverter. The AC signal generator has an output coupled to the first end of the low frequency timing capacitor and an alternating current is provided at the output of the AC signal to charge the low frequency timing capacitor. The invention uses the AC current of appropriate size and frequency to charge the low frequency timing capacitor, so that the charging current of the low frequency timing capacitor is the original DC current plus the alternating current, so that the low frequency ramp voltage generated at the output end of the low frequency oscillator is based on the alternating current. The magnitude of the current creates a disturbance, which in turn causes the low-frequency pulse width modulation signal to perturb, and expands the signal energy of the inverter to a relatively wide frequency range, thereby improving the low-frequency pulse width modulation signal of the converter. Electromagnetic interference generated during the transition between the enabling period and the inactive period. The above and other objects, features and advantages of the present invention will become more <RTIgt; Embodiments FIG. 3 is a block diagram of an inverter using PWM dimming according to an embodiment of the present invention. Referring to FIG. 3, the inverter 30 adopts the architecture of the LIPS power supply system 2 as shown in FIG. 1B. The variable inverter 30 is directly powered by the DC voltage Vbus of a typical value of 400 Vdc provided by the PFC and outputs an AC voltage Vlamp. Drive the CCFL. In the present embodiment, the inverter 30 includes a switching circuit 31, a transformer 32, a vibration circuit 33, a voltage sensor 34, a current sensor 35, and a control circuit 36. The switching circuit 31 is, for example, a full bridge type, a half bridge type switching circuit or other switching circuit for converting the direct current voltage Vbus into an alternating current voltage in the form of a square wave. The transformer 32 is used to boost the alternating voltage in the form of a square wave. The resonant circuit 33 is configured to filter the AC voltage in the form of a boosted square wave into an AC voltage Vlamp that approximates a sine wave, and to provide a spectral voltage and current to cause the switching circuit 31 to have a zero voltage/zero current switching characteristic. The voltage sensor 34 and the current sensor 35 respectively sense the voltage Vlamp and the current Ilamp® of the CCFL and output the voltage sensing signal Vvsen and the current sensing signal Visen. The control circuit 36 uses the PWM dimming mode to adjust the brightness according to the dimming signal Vdim, and stabilizes the CCFL brightness according to the current sensing k-number Visen output driving signal Vdrv to feedback the switching of the control switch circuit 31, and according to the voltage sensing signal. Yvsen to protect the circuit ^ due to p-side dimming can be divided into external PWM dimming and internal rain dimming, if the commutation ^ 3 〇 using external just dimming, the dimming signal Vdim is the low frequency pwm signal; and if the converter 3 〇 Using internal pWM dimming, the dimming signal Vdim is a DC signal, and the control circuit 36 generates a low-frequency PWM signal based on the DC signal. Internal PWM dimming is often used because it is relatively simple in design.

4 is a circuit diagram of a specific embodiment of the control circuit 36 of FIG. 3, wherein CMP 201029520 is an abbreviation of a comparator (CoMParator), and EA is an error amplifier (abbreviation of Err〇r. Please refer to FIG. 4 'control circuit 46 includes The low frequency oscillator 461, the low frequency timing circuit 462, the low frequency PWM comparator 463, the feedback control circuit 464, and the alternating current signal generator 465. The low frequency timing circuit 462 includes a low frequency timing resistor R1 and a low frequency timing capacitor C1, in this embodiment, The first end of the low frequency timing resistor ri is coupled to the DC power supply Vdd, and the first end of the low frequency 疋 resistor R1 is connected to the output of the low frequency oscillator 461 and the first end of the low frequency timing capacitor C1, and the second end of the low frequency timing capacitor C1. It is coupled to the ground potential Vgnd. The DC power supply Vdd generates a DC current ic through the low frequency timing resistor R1 for charging the low frequency φ timing capacitor C1, and the low frequency timing resistor R1 determines the magnitude of the DC current Ic. The low frequency oscillator 461 controls Stopping charging and starting discharge at the output or the voltage on the first end of the low frequency timing capacitor C1 is charged to the first set voltage Vpl, and is discharged to When the second set voltage Vp2 is set, the discharge is stopped and charging is started. Therefore, the voltage at the output end of the low frequency oscillator 461 or the low frequency timing capacitor C1 rises and falls repeatedly, forming a low frequency ramp voltage Vlst whose waveform is a triangular wave or a sawtooth wave. The peak voltage is the first setting - the voltage Vp is the second set voltage Vp2, and the frequency is fl 〇 sc and is proportional to 1 / (R1 x Cl). ❹ In the present embodiment, the 'inverter 30 is used. The internal PWM is dimmed, so the dimming signal Vdim is a DC signal. The first input of the low frequency PWM comparator 463 receives the DC dimming signal Vdim, and the second input is coupled to the first end of the low frequency timing capacitor α to receive the low frequency ramp voltage. Vlst ' generates a low frequency PWM signal at its output by comparing the direct current dimming signal Vdim with the low frequency ramp voltage vlst. An embodiment of the low frequency p-signal is shown in Figure 2, each period T (= l / fl 〇 sc) It includes a consistent energy period TJ)N and a disable period T_0FF. The feedback control circuit 464 is coupled to the low frequency PWM comparator 463 to receive the low frequency PWM signal. During the enable period of the low frequency p-long signal Vipwm, TJ)N' generates a drive signal vdry at the output of the feedback control circuit 464 to drive the switch circuit 31' to operate the inverter 30 to generate an AC voltage viamp having a frequency of fh〇sc. In the disable period TJ) FF of the low frequency PWM signal Vlpwm, the drive signal Vdrv is not generated at the output of the feedback control circuit 464, that is, the drive signal Vdrv is zero and the switch circuit 31' cannot be driven. The inverter 30 does not operate, and the AC voltage Vlamp is zero at this time. The CCFL cannot be driven to emit light (i.e., dimmed). The output of the AC signal generator 465 is coupled to the low frequency, and the first end of the battery C1 provides an alternating current la at the output of the parent signal generator 465. Therefore, the charging current of the frequency capacitor C1 is the original DC current ratio plus the alternating current la' such that the low frequency ramp voltage Vlst generated at the output of the low frequency 461 or the low frequency timing capacitor ci is dependent on the alternating current. The size of the ia is disturbed, and the low frequency pwm signal Vlpwm generated at the output of the low frequency rain comparator 463 is disturbed. The disturbed low frequency PWM signal Vlpwm extends the signal energy of the inverter 30 to a relatively wide frequency range by the feedback control circuit 464, thereby improving the converter 3 致 during the enable period of the low frequency PWM signal Vlpwm T_0N And the electromagnetic interference generated when the T_OFF is converted during the disable period. The feedback control circuit 464 includes an error amplifier 4641, a high frequency oscillator 4642, a high frequency timing circuit 4643, a high frequency PWM comparator 4464, a control logic circuit 4645, and an output driving circuit 4646. The error amplifier 4641 enable terminal (ie, the feedback control circuit 464 enable terminal) ^ receives the low frequency PWM signal Vlpwm ' during the enable period T_0N, the error amplifier 4641 operates normally to generate the drive signal Vdrv; and during the disable period T_0FF, the error The amplifier 4641 does not operate and cannot generate the drive signal Vdrv or the drive signal Vdrv is zero. When the error amplifier 4641 operates normally, the error amplifier 4641 generates an error voltage Vea at its output by comparing the current feedback signal Visen with the reference voltage Vref. The high frequency oscillator 4642 generates a ramp voltage in a manner similar to the low frequency oscillator 461, that is, the output of the high frequency oscillator 4642 is coupled to the high frequency timing circuit 4643 (which includes the high frequency timing resistor R2 and the high frequency timing capacitor C2). 'Generate a high frequency ramp voltage vhst at its output with a frequency of fhosc and proportional to l/(R2xC2). Then, the high frequency comparator 4464 generates a high frequency PWM signal Vhpwm at its output by comparing the high frequency ramp voltage Vhst and the error voltage Vea, and the control logic 994529520 circuit 4645 generates the driving signal Vdrv according to the high frequency PWM signal Vhpwm. The switching of the switching circuit 31 is controlled so as to generate an alternating voltage Vlamp having a frequency fhosc during the enabling period T__〇N as shown in FIG. The general drive signal Vdrv will enhance its drive capability through an output drive circuit 4646 such as an open dipole, open collector or totem pole. In addition, the low frequency oscillator 461, the low frequency PWM comparator 463, the error amplifier 4641, the high frequency oscillator 4642, the high frequency PWM comparator 4644, the control logic circuit 4645, and the output driving circuit 4646 can be combined and packaged into an integrated circuit, such as 0Z9938. In order to simplify the design.

In the present embodiment, the control circuit 46 further includes a comparator 466 and a switch 467. The first input terminal of the comparator 466 receives the DC dimming signal Vdim, and the second input terminal receives the first set voltage Vpl. The first set voltage is the peak voltage of the low frequency ramp voltage vist. The switch 467 is, for example, a PNP bipolar junction transistor having a first end (or emitter terminal) coupled to the output of the AC signal generator 465 and a second end (or collector terminal) coupled to the low frequency timing capacitor.

The first end of ci's control terminal (or base terminal) is coupled to the output of comparator 466. When the DC dimming signal Vdim is greater than or equal to the first set voltage Vpl, that is, the DC dimming number & address is greater than or equal to the peak voltage of the low frequency ramp voltage Vlst, and the enabling period TJM of the low frequency p-view signal Vlp is Maximum (ie τ—0N=T) without the disable period TJ) FF, there is no problem of electromagnetic interference generated during the transition between the enable period Τ_0Ν and the disable period T_0FF. Therefore, the output of the comparator 466 can be used for energy saving. The output signal control switch 467 is turned off to disconnect the output of the AC signal generator 465 and the first end of the low frequency timing capacitor a. When the DC dimming signal Vdim is smaller than the first set voltage Vpl, the comparator 46g terminal output signal control switch 467 is turned on, so that the AC signal generator galvanically supplies the timing capacitor n α to the first end. Correction, if the exchange of professional production &quot; 仏 backflow design, you must provide a one-way conduction function between the open w 467 and the low frequency (four) capacitor ci, two body di, as shown in Figure 4, the diode D1 _ end reduction At the low ant time capacitor or 'set the diode between the switch 467 and the AC signal generator (not shown) 201029520 201029520 The cathode end of the diode is coupled to the anode end of the pole and coupled to the output of the AC signal generator 465 End, to the first end of the switch 467. FIG. 5 is a circuit diagram of another embodiment of the control circuit 36 of FIG. At the same time, the difference between the control circuit 56 and the control circuit 46 is only to control whether or not the word trickle signal la is supplied to the low frequency timing capacitor C1. The control circuit 洸 compares the DC dimming signal Vdiff1 and the first set voltage Vpl with a ratio 466 to output a control signal control switch 567. The switch 567 is, for example, a circular bipolar junction transistor, j, the first end (or collector terminal) is connected to the AC signal to generate the output terminal and the diode 跄罾1^ extreme 'the second end (or the emitter end) Turning to the ground potential Vgnd, its control terminal (or base is connected to the comparison H 466 output. When the DC dimming signal Vdim is greater than or equal to the first 疋 voltage Vpi, the comparator 466 round-trip output signal control switch 567 is turned on, 5 diode? The anode end is switched to the ground potential _, so the diode D2 is turned off and the output of the AC generator 465 is disconnected from the low frequency timing capacitor C1 。. Conversely, when the straight = dimming 仏 ¥ ¥ (11111 is smaller than the first set voltage Vpl, the comparator 466 output output control switch 567 is turned off, and the output of the AC signal generator 465 is recorded to the first end of the low frequency timing capacitor ci. - ❹I is shown in Fig. 6 3 is a circuit diagram of a specific embodiment of the control circuit 36. Please simultaneously *', 4 and 6, the difference between the control circuit 66 and the control circuit 46 is only the implementation of the low frequency oscillation mountain and the low frequency timing circuit. The output of the low frequency oscillator 661 of circuit 66 has a first round Terminal and second output. Low-frequency timing circuit 662 of control circuit 66 = low-sensitivity resistor 11 R1 and low-frequency timing capacitor H G1, low-voltage resistor R1 first, lightly connected and low-oscillation $ 661 first-round The low-frequency timing capacitor C1帛-end consumes the second output end of the frequency-shocking device 661, and the low-sensitivity resistor R1 and the low-frequency timing capacitor π/7 are all coupled to the ground potential Vgn (the low-frequency oscillator 661 provides the DC current) Ic's frequency 疋Chip capacitor C1 is charged' and the low frequency timing resistor R1 determines the DC current Ic size. At this time, the low frequency PWM comparator 463 second input terminal and the AC signal generator 465 201029520 output is supplemented to the low frequency oscillation H 661 second The output terminal and the surface timing capacitor C1 have a first end 'not secret to the low frequency oscillator 661 帛 - the output terminal and the low frequency timing resistor 耵. Fig. 7 is a circuit diagram of a specific embodiment of the AC signal generator 465 shown in Fig. 4. Please refer to FIG. 7 'AC signal generator 765 includes a Wayne bridge vibrator (5) side oscillator) 765 of which Wayne bridge oscillator 7651 is operated amplifier 〇pA, resistors R4 R R7 and capacitors C3 ~ C6 The composition. Wayne bridge vibrator 765 1 output is switched to resistor R3 'so the sine wave voltage signal outputted from its output terminal passes through resistor r ac current la. In summary, the control circuit of the inverter using PWM dimming of the present invention utilizes AC The signal generator generates an alternating current of appropriate size and frequency to charge the low frequency timing capacitor, so the low frequency correction capacitor _ charging current is the current of the county current plus the low frequency ramp voltage generated by the current at the output of the low frequency oscillator according to the alternating current The size creates a disturbance that causes the low frequency pwM signal generated at the output of the low frequency PWM comparator to be disturbed. The disturbed low-frequency PWM signal extends the signal energy of the inverter to a relatively wide frequency range through the feedback control circuit, thereby improving the instantaneous conversion of the converter during the enabling period and the disable period of the low-frequency compensation signal. Electromagnetic interference. While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A is a block diagram of a conventional cold cathode fluorescent lamp power supply system. FIG. 1B is a block diagram of a conventional cold cathode fluorescent lamp power supply system of the LIPS architecture. 2 is a waveform diagram of an input and output signal of an inverter of the LIPS power supply system shown in FIG. 1B. 12 201029520 FIG. 3 is a block diagram of an inverter using PWM dimming in accordance with an embodiment of the present invention. 4 is a circuit diagram of a specific embodiment of the control circuit of FIG. Figure 5 is a circuit diagram of another embodiment of the control circuit of Figure 3. Figure 6 is a circuit diagram of still another embodiment of the control circuit of Figure 3. Figure 7 is a circuit diagram of a specific embodiment of the parent flow generator shown in Figure 4. [Main component symbol description]

1, 2: CCFL power system 12: bridge rectifier 14 · standby power converter 16, 26: inverter 31: switching circuit 33. Spectral circuit 35: current sensor 46 661: low frequency oscillator 463: low frequency PWM comparator 4641: error amplifier 4643: high frequency timing circuit 4645: control logic circuit 465, 765: AC signal generator 467, 567: switch 11: electromagnetic interference (EMI) filter 13: power factor corrector (pfC) 15 25: main power converter 30: inverter 32: transformer 34: voltage sensor 36, 46, 56, 66: control circuit 462, 662: low frequency timing circuit 464: feedback control circuit 4642 · local frequency vibration 4644: high frequency PWM comparator 4646: output drive circuit 466: comparator 7651: Wayne bridge oscillator 13 201029520

Vbus : DC voltage Vvsen : Voltage sensing signal Vdrv : Drive signal Vlpwm : Low frequency PWM signal Vlst : Low frequency ramp voltage Vref : Reference voltage Vpl : First set voltage Vgnd : Ground potential Ic · DC current R1 : Low frequency timing resistor R3 ~ R7: Resistor C2: South Frequency Timing Capacitor|§

Dl, D2: Diode Τ_0Ν : Low frequency PWM signal enable period flosc : Low frequency PWM signal frequency

Vlamp: AC voltage (or CCFL voltage)

Vi sen : current sensing signal

Vdim: dimming signal

Vhpwra: high frequency PWM signal

Vhst : high frequency ramp voltage

Vea: error voltage

Vdd: DC power supply

Ilamp : CCFL current la : AC current R2 : High frequency timing resistor C1 : Low frequency timing capacitor C3 ~ C6 : Capacitor T : Low frequency PWM signal period T_0FF : Low frequency PWM signal disable period fhosc : High frequency PWM signal frequency

Claims (1)

201029520 VII. Patent Application Range·· 1. A control circuit for an inverter using pulse width modulation dimming, comprising: a low frequency timing circuit comprising a low frequency timing resistor and a low frequency timing capacitor, the low frequency timing resistor determining a DC current that charges the low frequency timing capacitor. The low frequency timing capacitor has a first end and a second end, and the second end of the low frequency timing capacitor is connected to a ground potential; a low frequency oscillator, An output end coupled to the low frequency ringing resistor and the first end of the low frequency timing capacitor, controlling the low frequency timing capacitor to be repeatedly charged and discharged to generate at the first end of the low frequency timing capacitor a low frequency ramp voltage comparator; a low frequency pulse width modulation comparator 'having a first input terminal, a second input terminal and an output terminal'; the first input end of the low frequency pulse width modulation comparator receives the DC current dimming signal, The second input end of the low frequency pulse width modulation comparator is coupled to the first end of the low frequency timing capacitor 'in the low frequency pulse width modulation comparison a low-frequency pulse width modulation signal is generated at the output end of the low-frequency pulse width modulation signal. Each period includes a uniform energy period and a disable period φ; a feedback control circuit 'having a uniform energy end and an output end, a feedback control circuit enabling end is connected to the output of the low frequency pulse width modulation comparator, and during the enabling period, a driving signal is generated at the output of the feedback control circuit, during the disable period, the feedback control circuit The output signal is not generated at the output end; and the AC signal generator has an output end coupled to the first end of the low frequency timing capacitor, and an alternating current is provided at the output of the alternating current signal generator . 2. The control of the inverter using pulse width modulation dimming as described in claim 1 of the patent scope 15 201029520 circuit, further comprising: a comparator having a first input terminal, a second input terminal and an output The first input end of the comparator receives the DC dimming signal, the second input end of the comparator receives a set voltage, the set voltage is a peak voltage of the low frequency ramp voltage, and a switch has a first end, a second end and a control end, the first end of the switch is coupled to the output of the AC signal generator, the second end of the switch is coupled to the first end of the low frequency timing capacitor, and the switch control end is coupled to the comparison The output end of the comparator, wherein when the DC dimming signal is greater than or equal to the set voltage, the output signal of the comparator output controls the switch to be turned off, so that the output of the AC signal generator and the first end of the low frequency timing capacitor are broken. When the DC dimming signal is less than the set voltage, the output signal of the comparator output controls the switch to be turned on, so that the output of the AC signal generator is coupled to the low frequency A first end of the capacitor. 3. The control circuit of the inverter using pulse width modulation dimming as described in claim 2, further comprising: a diode having an anode end and a cathode end, the anode end of the diode being coupled To the second end of the switch, the cathode end of the diode is coupled to the first end of the low frequency timing capacitor. 4. The control circuit of the inverter using pulse width modulation dimming as described in claim 2, further comprising: a diode having an anode end and a cathode end, the anode end of the diode being coupled To the output of the AC signal generator, the cathode end of the diode is coupled to the first end of the switch. 5. The control circuit of the inverter using pulse width modulation dimming as described in claim 1, further comprising: a comparator having a first input terminal, a second input terminal, and an output terminal; The first input end of the comparator receives the DC dimming signal, and the second input end of the comparator receives a 201029520 singular electric skill 'chaotic electric calendar for the peak of the low frequency slope electric waste; and a diode Having an anode end and a cathode end, the first end of the frequency timing capacitor; and the cathode end of the diode is connected to the low switch 'having a first end, a second end and a control end, the switch first ^ The alternating current signal generates a chirp output end and the diode anode end, the second is connected to the ground potential, and the switch control end is connected to the comparator output end, wherein when the direct current dimming signal is greater than or equal to the When the voltage is set, the comparator output terminal outputs an output signal to control the switch to conduct 'couples the anode end of the diode to the ground potential, and when the DC dimming signal is less than the set voltage, the comparator output output signal control The control circuit of the inverter using pulse width modulation dimming as described in claim 1, wherein the low frequency timing resistor has a first end and a second end, the low frequency The first end of the timing resistor is connected to the DC power source, and the second end of the low frequency timing resistor is connected to the low frequency oscillator output end and the first end of the low frequency timing capacitor. 7. The control circuit of the inverter using pulse width modulation dimming as described in claim 1, wherein the low frequency oscillator output comprises a first output end and a second output end, the low frequency timing The resistor has a first end and a second end, the first end of the low frequency timing resistor is coupled to the first output end of the low frequency oscillator, and the second end of the low frequency timing resistor is coupled to the ground potential, the low frequency timing The first end of the capacitor is coupled to the second output of the low frequency oscillator. 17