TWI404458B - Controller circuit of inverter using pulse width modulation (pwm) dimming - Google Patents

Controller circuit of inverter using pulse width modulation (pwm) dimming Download PDF

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Publication number
TWI404458B
TWI404458B TW98102080A TW98102080A TWI404458B TW I404458 B TWI404458 B TW I404458B TW 98102080 A TW98102080 A TW 98102080A TW 98102080 A TW98102080 A TW 98102080A TW I404458 B TWI404458 B TW I404458B
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end
low frequency
output
coupled
comparator
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TW98102080A
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Chinese (zh)
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TW201029520A (en
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Li Wei Lin
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Top Victory Invest Ltd
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Abstract

A controller circuit of an inverter using pulse-width modulation (PWM) dimming includes a low-frequency (LF) timing capacitor, an LF oscillator, an LF PWM comparator, a feedback controller and an alternating-current (AC) generator. An output of the LF oscillator is coupled to the LF timing capacitor and an input of the LF PWM comparator, and an output of the LF PWM comparator is coupled to the feedback controller. The AC generator generates an AC current having appropriate magnitude and frequency to charge the LF timing capacitor. The charging current of the LF timing capacitor includes a direct-current (DC) current and the AC current. An LF ramp voltage generated at the output of the LF oscillator is fluctuated according to the magnitude of the AC current; and further, an LF PWM signal generated at the output of the LFPWM comparator is fluctuated according to the fluctuated LF ramp voltage. The fluctuated LF PWM signal is input to the feedback controller, and the spectrum of signal energy of the inverter is expanded to a wider frequency range; therefore, it improves electromagnetic interference (EMI) generated at the transition of an enable period and a disable period of the LF PWM signal.

Description

Control circuit for inverter using pulse width modulation dimming

The present invention relates to a control circuit for an inverter, and more particularly to a control circuit for an inverter using Pulse Width Modulation (PWM) dimming.

1A is a block diagram of a conventional Cold Cathode Fluorescent Lamp (CCFL) power supply system. Referring to FIG. 1A, after the AC mains input is input to the conventional power supply system 1, the electromagnetic interference (Electromagnetic Interference (EMI) filter 11 is used to filter out the noise, and then rectified by the bridge rectifier 12 to become a DC ripple signal. In order to comply with the harmonic specification, the DC pulse signal of the power system input power greater than 75W must be corrected by the Power Factor Corrector (PFC) 13 to correct the current harmonic distortion and become a stable DC voltage of 400Vdc. The standby power converter 14 and the main power converter 15 are supplied with power. The standby power converter 14 changes the DC voltage Vbus to a power supply of a typical value of 5 Vdc, and supplies power to a main board Micro Controller Unit (MCU) in a standby mode to maintain the operation of the remote control receiver, and The PFC 13 and the main power converter 15 are turned off to reduce standby power consumption. The main power converter 15 converts the DC voltage Vbus into a power source of a typical value of 12Vdc, 14Vdc or other voltage to supply power to an audio, video, control module or other module, and becomes a power source of a typical value of 24Vdc to supply power to the inverter. 16. The inverter 16 changes the power supply of a typical value of 24 Vdc supplied from the main power converter 15 to an AC voltage Vlamp of a typical value of 1800 Vac to start the CCFL, and from 1800 Vac to 800 Vae after startup is sufficient to stabilize the CCFL.

In order to reduce manufacturing costs and improve conversion efficiency, a CCFL power system with LIPS architecture was developed, and LIPS is short for Lcd Integrated Power Supply. FIG. 1B is a block diagram of a CCFL power system of the existing LIPS architecture. Please also refer to the map 1A and FIG. 1B, the inverter 16 of the conventional power supply system 1 is no longer powered by the main power converter 15, and the inverter 26 of the LIPS power system 2 is directly powered by the DC voltage Vbus of a typical value of 400 Vdc provided by the PFC 13. Therefore, the electric energy for driving the CCFL reduces the first-order energy conversion, that is, the loss of the first-stage conversion efficiency is saved, and the design power and the structural complexity of the main power converter 25 can be reduced, thereby improving the heat dissipation problem and reducing the manufacturing cost. However, since the LIPS power supply system 2 lacks the voltage stabilizing effect of the main power converter 25, its stability is relatively insufficient, especially when the inverter 26 uses pulse width modulation (PWM) dimming at the PFC 13. Excessive transient AC changes occur on the DC voltage Vbus.

2 is a waveform diagram of input and output signals of the inverter 26 of the LIPS power supply system 2 shown in FIG. 1B. Referring to FIG. 1B and FIG. 2 simultaneously, the inverter 26 uses PWM dimming, so the received dimming signal is the low frequency PWM signal Vlpwm. PWM dimming is currently the most common dimming method due to its wide dimming range, good dimming linearity and easy circuit implementation. Each period T of the low frequency PWM signal Vlpwm includes a coincidence period T_ON and an disable period T_OFF. During the enable period T_ON, the converter 26 operates normally, which generates an AC voltage Vlamp having a frequency fhosc to drive the CCFL to illuminate (ie, brighten); and during the disable period T_OFF, the inverter 26 does not operate, and the AC voltage at this time Vlamp is zero and cannot drive CCFL illumination (ie darken). The frequency flosc of the low-frequency PWM signal Vlpwm is usually designed to be higher than 100Hz. Under the influence of the temporary storage of human vision, it can not be seen that the CCFL becomes brighter and darker, and only the light and dark changes can be seen. (ie, adjusting the ratio of the enable period T_ON and the disable period T_OFF) can achieve the purpose of dimming. Since the LIPS power supply system 2 lacks the voltage stabilizing effect of the main power converter 25, when the inverter 26 uses PWM dimming, the commutation period T_ON and the disable period T_OFF of the low-frequency PWM signal Vlpwm are instantaneously converted, and the commutation is performed. The device 26 is instantaneously loaded or unloaded, so that the transient voltage change of the DC voltage Vbus provided by the PFC 13 occurs. The transient AC change of the DC voltage Vbus is likely to map the frequency of the AC change through the inductor in the PFC 13, and the EMI effect on the low-band spectrum of the fundamental frequency of the band.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a control circuit for an inverter using pulse width modulation dimming to improve electromagnetic interference generated by an inverter during a transition period between an enable period and a disable period of a low frequency pulse width modulation signal.

In order to achieve the above and other objects, the present invention provides a control circuit for a converter using pulse width modulation dimming, which includes a low frequency timing circuit, a low frequency oscillator, a low frequency pulse width modulation comparator, a feedback control circuit, and an alternating current. Signal generator. The low frequency timing circuit includes a low frequency timing resistor and a low frequency timing capacitor. The low frequency timing resistor determines the magnitude of the direct current and the direct current is used to charge the low frequency timing capacitor. The low frequency timing capacitor has a first end and a second end and the second end is coupled to Ground potential. The low frequency oscillator has an output end coupled to the low frequency timing resistor and the first end of the low frequency timing capacitor, the low frequency oscillator controlling the low frequency timing capacitor to be repeatedly charged and discharged to generate a low frequency ramp voltage at the first end of the low frequency timing capacitor. The low frequency pulse width modulation comparator has a first input end, a second input end and an output end, the first input end of the low frequency pulse width modulation comparator receives the DC dimming signal, and the low frequency pulse width modulation comparator is coupled to the second input end Connected to the first end of the low frequency timing capacitor, a low frequency pulse width modulation signal is generated at the output of the low frequency pulse width modulation comparator, wherein the low frequency pulse width modulation signal includes a uniform energy period and an inactive period. The feedback control circuit has an enable end and an output end, and the feedback control circuit enable end is coupled to the output end of the low frequency pulse width modulation comparator, and generates a drive signal at the output of the feedback control circuit during the enable period, and disables During the period, no drive signal is generated at the output of the feedback control circuit, wherein the drive signal is used to drive the switching of the switch circuit in the inverter. The AC signal generator has an output coupled to the first end of the low frequency timing capacitor, and an alternating current is provided at the output of the AC signal to charge the low frequency timing capacitor.

The invention utilizes an alternating current of appropriate size and frequency to charge the low frequency timing capacitor, so that the charging current of the low frequency timing capacitor is the original direct current plus the alternating current, so that the low frequency ramp voltage generated at the output of the low frequency oscillator is based on the alternating current. The magnitude of the current creates a disturbance, which in turn causes the low-frequency pulse width modulation signal to perturb, and the signal energy of the converter is extended to a relatively wide frequency range, thereby improving the converter's low-frequency pulse width modulation signal. Electromagnetic interference generated during the transition period between the energy period and the disable period.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

3 is a block diagram of an inverter using PWM dimming in accordance with an embodiment of the present invention. Referring to FIG. 3, the inverter 30 adopts the architecture of the LIPS power system 2 as shown in FIG. 1B. Therefore, the inverter 30 is directly powered by a DC voltage Vbus of a typical value of 400 Vdc provided by the PFC, and outputs an AC voltage Vlamp to drive. CCFL. In the present embodiment, the inverter 30 includes a switching circuit 31, a transformer 32, a resonant circuit 33, a voltage sensor 34, a current sensor 35, and a control circuit 36. The switching circuit 31 is, for example, a full bridge type, a half bridge type switching circuit or other switching circuit for converting the direct current voltage Vbus into an alternating current voltage in the form of a square wave. Transformer 32 is used to boost the alternating voltage in the form of a square wave. The resonant circuit 33 is configured to filter the AC voltage in the form of a boosted square wave into an AC voltage Vlamp that approximates a sine wave, and to provide a resonant voltage and current to cause the switching circuit 31 to have a zero voltage/zero current switching characteristic. The voltage sensor 34 and the current sensor 35 respectively sense the voltage Vlamp and the current Ilamp of the CCFL and output the voltage sensing signal Vvsen and the current sensing signal Visen. The control circuit 36 uses the PWM dimming mode to adjust the CCFL brightness according to the dimming signal Vdim, and outputs the driving signal Vdrv according to the current sensing signal Visen to feedback the switching of the control switch circuit 31 to stabilize the CCFL brightness, and according to the voltage sensing signal Vvsen To protect the circuit. Since the PWM dimming can be divided into external PWM dimming and internal PWM dimming, if the inverter 30 uses external PWM dimming, the dimming signal Vdim is a low frequency PWM signal; and if the inverter 30 uses internal PWM dimming, then The dimming signal Vdim is a DC signal, and the control circuit 36 generates a low frequency PWM signal according to the DC signal. The internal PWM dimming is often used because it is relatively simple in design.

4 is a circuit diagram of a specific embodiment of the control circuit 36 of FIG. 3, wherein CMP is an abbreviation of a comparator, and EA is an abbreviation of an error amplifier (Error Amplifier). Referring to FIG. 4, the control circuit 46 includes a low frequency oscillator 461, a low frequency timing circuit 462, a low frequency PWM comparator 463, a feedback control circuit 464, and an alternating current signal generator 465. The low frequency timing circuit 462 includes a low frequency timing resistor R1 and a low frequency timing capacitor C1. In this embodiment, the first end of the low frequency timing resistor R1 is coupled to the DC power supply Vdd, and the second end of the low frequency timing resistor R1 is coupled to the low frequency oscillation. The output of the device 461 and the first end of the low frequency timing capacitor C1, and the second end of the low frequency timing capacitor C1 are coupled to the ground potential Vgnd. The DC power source Vdd generates a DC current Ic through the low frequency timing resistor R1 for charging the low frequency timing capacitor C1, and the low frequency timing resistor R1 determines the magnitude of the DC current Ic. The low frequency oscillator 461 controls to stop charging and start discharging when the voltage at the output terminal or the first terminal of the low frequency timing capacitor C1 is charged to the first set voltage Vp1, and stops discharging and starts charging when discharging to the second set voltage Vp2. . Therefore, the voltage on the first end of the low frequency oscillator 461 or the low frequency timing capacitor C1 will rise and fall repeatedly, forming a low frequency ramp voltage Vlst whose waveform is a triangular wave or a sawtooth wave, and the peak voltage thereof is the first set voltage Vp1, the trough The voltage is the second set voltage Vp2, the frequency of which is flosc and is proportional to 1/(R1×C1).

In the present embodiment, the inverter 30 uses internal PWM dimming, so the dimming signal Vdim is a DC signal. The first input end of the low frequency PWM comparator 463 receives the DC dimming signal Vdim, and the second input end is coupled to the first end of the low frequency timing capacitor C1 to receive the low frequency ramp voltage Vlst, by comparing the DC dimming signal Vdim and the low frequency ramp voltage Vlst A low frequency PWM signal Vlpwm is generated at its output. An embodiment of the low frequency PWM signal Vlpwm is shown in FIG. 2, and each period T (=1/flosc) includes a coincidence period T_ON and a disable period T_OFF. The feedback control circuit 464 is coupled to the output of the low frequency PWM comparator 463 to receive the low frequency PWM signal Vlpwm. During the enable period T_ON of the low frequency PWM signal Vlpwm, a drive signal Vdrv is generated at the output of the feedback control circuit 464 to drive the switch circuit 31, so that the inverter 30 operates normally to generate an AC voltage Vlamp having a frequency of fhosc. The CCFL is illuminated; and during the disable period T_OFF of the low frequency PWM signal Vlpwm, the drive signal Vdrv is not generated at the output of the feedback control circuit 464, that is, the drive signal Vdrv is zero and the switch circuit 31 cannot be driven, so that the inverter 30 does not operate. At this time, the AC voltage Vlamp is zero, and the CCFL cannot be driven to emit light (ie, darken). The output of the AC signal generator 465 is coupled to the first end of the low frequency timing capacitor C1, and the AC current Ia is provided at the output of the AC signal generator 465. Therefore, the charging current of the low-frequency timing capacitor C1 is the original DC current Ic plus the alternating current Ia, so that the low-frequency ramp voltage Vlst generated at the output of the low-frequency oscillator 461 or the first end of the low-frequency timing capacitor C1 depends on the magnitude of the alternating current Ia. A disturbance is generated which causes the low frequency PWM signal Vlpwm generated at the output of the low frequency PWM comparator 463 to cause a disturbance. The disturbed low frequency PWM signal Vlpwm extends the signal energy of the inverter 30 to a relatively wide frequency range by the feedback control circuit 464, thereby improving the enabler T_ON and disabling of the low frequency PWM signal Vlpwm during the inverter 30 During the period T_OFF, the electromagnetic interference generated by the conversion is instantaneous.

The feedback control circuit 464 includes an error amplifier 4641, a high frequency oscillator 4642, a high frequency timing circuit 4643, a high frequency PWM comparator 4464, a control logic circuit 4645, and an output driving circuit 4646. The error amplifier 4641 enable terminal (ie, the feedback control circuit 464 enable terminal) receives the low frequency PWM signal Vlpwm. During the enable period T_ON, the error amplifier 4641 operates normally to generate the drive signal Vdrv; and during the disable period T_OFF, the error amplifier 4641 does not work and cannot generate the drive signal Vdrv or the drive signal Vdrv is zero. When the error amplifier 4641 operates normally, the error amplifier 4641 generates an error voltage Vea at its output by comparing the current sense signal Visen with the reference voltage Vref. The high frequency oscillator 4642 generates a ramp voltage in the same manner as the low frequency oscillator 461, that is, the output end of the high frequency oscillator 4642 is coupled to the high frequency timing circuit 4643 (which includes the high frequency timing resistor R2 and the high frequency timing capacitor C2). A high frequency ramp voltage Vhst is generated at its output, the frequency of which is fhosc and is proportional to 1/(R2 x C2). Next, the high frequency PWM comparator 4644 generates a high frequency PWM signal Vhpwm at its output by comparing the high frequency ramp voltage Vhst and the error voltage Vea, and the control logic circuit 4645 generates a drive signal Vdrv according to the high frequency PWM signal Vhpwm to control the switch circuit 31. Switching so as to generate an AC voltage Vlamp having a frequency of fhosc during the enable period T_ON as shown in FIG. The general drive signal Vdrv will enhance its drive capability through an output drive circuit 4646 such as an open drain, open collector or totem pole. In addition, the low frequency oscillator 461, the low frequency PWM comparator 463, the error amplifier 4641, the high frequency oscillator 4642, the high frequency PWM comparator 4644, the control logic circuit 4645, and the output driving circuit 4646 can be combined and packaged into an integrated circuit, such as OZ9938. In order to simplify the design.

In the embodiment, the control circuit 46 further includes a comparator 466 and a switch 467. The first input terminal of the comparator 466 receives the DC dimming signal Vdim, and the second input terminal receives the first set voltage Vp1, and the first set voltage is the peak voltage of the low frequency ramp voltage Vlst. The switch 467 is, for example, a PNP bipolar junction transistor having a first end (or emitter terminal) coupled to the output of the AC signal generator 465 and a second end (or collector terminal) coupled to the low frequency timing capacitor C1. At one end, its control terminal (or base terminal) is coupled to the output of comparator 466. When the DC dimming signal Vdim is greater than or equal to the first set voltage Vp1, that is, the DC dimming signal Vdim is greater than or equal to the peak voltage of the low frequency ramp voltage Vlst, the enabling period T_ON of the low frequency PWM signal Vlpwm is maximum (ie, T_ON= T) Without the disable period T_OFF, there is no problem that electromagnetic interference occurs instantaneously during the transition period between the enable period T_ON and the disable period T_OFF. Therefore, in order to save energy, the output signal of the comparator 466 output control switch 467 is turned off. The output of the AC signal generator 465 and the first end of the low frequency timing capacitor C1 are disconnected. On the contrary, when the DC dimming signal Vdim is smaller than the first set voltage Vp1, the output signal of the comparator 466 is controlled to be turned on, so that the output of the AC signal generator 465 is coupled to the first end of the low frequency timing capacitor C1. In addition, if the AC signal generator 465 does not have a design to prevent signal backflow, the diode D1 must be provided between the switch 467 and the low frequency timing capacitor C1 to provide a unidirectional conduction function, as shown in FIG. 4, the anode end of the diode D1. The second end of the diode D1 is coupled to the first end of the low frequency timing capacitor C1; or a diode (not shown) is disposed between the switch 467 and the AC signal generator 465, The anode end of the polar body is coupled to the output of the AC signal generator 465, and the cathode end of the diode is coupled to the first end of the switch 467.

FIG. 5 is a circuit diagram of another embodiment of the control circuit 36 of FIG. Referring to FIG. 4 and FIG. 5 simultaneously, the difference between the control circuit 56 and the control circuit 46 is only the embodiment of controlling whether or not the alternating current Ia is supplied to the low frequency timing capacitor C1. The control circuit 56 compares the DC dimming signal Vdim with the first set voltage Vp1 by the comparator 466 to output a control signal control switch 567. The switch 567 is, for example, an NPN bipolar junction transistor, the first end (or collector terminal) of which is coupled to the output of the AC signal generator 465 and the anode end of the diode D2, and the second end (or the emitter end) is coupled. Connected to the ground potential Vgnd, its control terminal (or base terminal) is coupled to the output of the comparator 466. When the DC dimming signal Vdim is greater than or equal to the first set voltage Vp1, the output signal of the output of the comparator 466 is controlled to be turned on, so that the anode end of the diode D2 is coupled to the ground potential Vgnd, so that the diode D2 is turned off. The output of the AC signal generator 465 is disconnected from the first end of the low frequency timing capacitor C1. On the contrary, when the DC dimming signal Vdim is smaller than the first set voltage Vp1, the output signal of the comparator 466 is controlled to be turned off, and the output of the AC signal generator 465 is of course coupled to the first end of the low frequency timing capacitor C1.

FIG. 6 is a circuit diagram of still another embodiment of the control circuit 36 of FIG. Referring to FIG. 4 and FIG. 6 simultaneously, the difference between the control circuit 66 and the control circuit 46 is only the embodiment of the low frequency oscillator and the low frequency timing circuit. The output of the low frequency oscillator 661 of the control circuit 66 has a first output and a second output. The low frequency timing circuit 662 of the control circuit 66 includes a low frequency timing resistor R1 and a low frequency timing capacitor C1. The first end of the low frequency timing resistor R1 is coupled to the first output end of the low frequency oscillator 661, and the first end of the low frequency timing capacitor C1 is coupled to the low frequency. The second output end of the oscillator 661, the low frequency timing resistor R1 and the second end of the low frequency timing capacitor C1 are coupled to the ground potential Vgnd. The low frequency oscillator 661 provides a direct current Ic to charge the low frequency timing capacitor C1, and the low frequency timing resistor R1 determines the magnitude of the direct current Ic. At this time, the second input end of the low frequency PWM comparator 463 and the output end of the AC signal generator 465 are coupled to the second output end of the low frequency oscillator 661 and the first end of the low frequency timing capacitor C1, and are not coupled to the low frequency oscillator 661. Output and low frequency timing resistor R1.

FIG. 7 is a circuit diagram of a specific embodiment of the AC signal generator 465 of FIG. Referring to FIG. 7, the AC signal generator 765 includes a Wien bridge oscillator 7651, wherein the Wayne bridge oscillator 7651 is composed of an operational amplifier OPA, resistors R4 to R7, and capacitors C3 to C6. . The output end of the Wayne bridge oscillator 7651 is coupled to the resistor R3, so the sine wave voltage signal outputted from the output terminal generates the alternating current Ia through the resistor R3.

In summary, the control circuit of the PWM dimming converter of the present invention uses an AC signal generator to generate an AC current of appropriate size and frequency to charge the low frequency timing capacitor, so the charging current of the low frequency timing capacitor is the original DC current. In addition to the alternating current, the low frequency ramp voltage generated at the output of the low frequency oscillator will be disturbed according to the magnitude of the alternating current, causing the low frequency PWM signal generated at the output of the low frequency PWM comparator to be disturbed. The disturbed low-frequency PWM signal extends the signal energy of the inverter to a relatively wide frequency range through the feedback control circuit, thereby improving the instantaneous conversion of the converter during the enabling period and the disable period of the low-frequency PWM signal. Electromagnetic interference.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

1, 2. . . CCFL power system

11. . . Electromagnetic interference (EMI) filter

12. . . Bridge rectifier

13. . . Power Factor Corrector (PFC)

14. . . Standby power converter

15,25. . . Main power converter

16, 26. . . Inverter

30. . . Inverter

31. . . Switch circuit

32. . . transformer

33. . . Resonant circuit

34. . . Voltage sensor

35. . . Current sensor

36, 46, 56, 66. . . Control circuit

461, 661. . . Low frequency oscillator

462, 662. . . Low frequency timing circuit

463. . . Low frequency PWM comparator

464. . . Feedback control circuit

4641. . . Error amplifier

4642. . . High frequency oscillator

4643. . . High frequency timing circuit

4644. . . High frequency PWM comparator

4645. . . Control logic

4646. . . Output drive circuit

465, 765. . . AC signal generator

466. . . Comparators

467,567. . . switch

7651. . . Wayne Bridge Oscillator

Vbus. . . DC voltage

Vlamp. . . AC voltage (or CCFL voltage)

Vvsen. . . Voltage sensing signal

Visen. . . Current sensing signal

Vdrv. . . Drive signal

Vdim. . . Dimming signal

Vlpwm. . . Low frequency PWM signal

Vhpwm. . . High frequency PWM signal

Vlst. . . Low frequency ramp voltage

Vhst. . . High frequency ramp voltage

Vref. . . Reference voltage

Vea. . . Error voltage

Vp1. . . First set voltage

Vdd. . . DC power supply

Vgnd. . . Ground potential

Ilamp. . . CCFL current

Ic. . . DC

Ia. . . Alternating current

R1. . . Low frequency timing resistor

R2. . . High frequency timing resistor

R3 ~ R7. . . Resistor

C1. . . Low frequency timing capacitor

C2. . . High frequency timing capacitor

C3 ~ C6. . . Capacitor

D1, D2. . . Dipole

T. . . Low frequency PWM signal period

T_ON. . . Low frequency PWM signal enable period

T_OFF. . . Low frequency PWM signal disable period

Flosc. . . Low frequency PWM signal frequency

Fhosc. . . High frequency PWM signal frequency

1A is a block diagram of a conventional cold cathode fluorescent lamp power supply system.

FIG. 1B is a block diagram of a conventional cold cathode fluorescent lamp power supply system of the LIPS architecture.

2 is a waveform diagram of an input and output signal of an inverter of the LIPS power supply system shown in FIG. 1B.

3 is a block diagram of an inverter using PWM dimming in accordance with an embodiment of the present invention.

4 is a circuit diagram of a specific embodiment of the control circuit of FIG.

Figure 5 is a circuit diagram of another embodiment of the control circuit of Figure 3.

Figure 6 is a circuit diagram of still another embodiment of the control circuit of Figure 3.

Figure 7 is a circuit diagram of a specific embodiment of the AC signal generator of Figure 4.

46. . . Control circuit

461. . . Low frequency oscillator

462. . . Low frequency timing circuit

463. . . Low frequency PWM comparator

464. . . Feedback control circuit

4641. . . Error amplifier

4642. . . High frequency oscillator

4643. . . High frequency timing circuit

4644. . . High frequency PWM comparator

4645. . . Control logic

4646. . . Output drive circuit

465. . . AC signal generator

466. . . Comparators

467. . . switch

Vvsen. . . Voltage sensing signal

Visen. . . Current sensing signal

Vdrv. . . Drive signal

Vdim. . . Dimming signal

Vlpwm. . . Low frequency PWM signal

Vhpwm. . . High frequency PWM signal

Vlst. . . Low frequency ramp voltage

Vhst. . . High frequency ramp voltage

Vref. . . Reference voltage

Vea. . . Error voltage

Vp1. . . First set voltage

Vdd. . . DC power supply

Vgnd. . . Ground potential

Ic. . . DC

Ia. . . Alternating current

R1. . . Low frequency timing resistor

R2. . . High frequency timing resistor

C1. . . Low frequency timing capacitor

C2. . . High frequency timing capacitor

D1. . . Dipole

Claims (7)

  1. A control circuit for a converter using pulse width modulation dimming, comprising: a low frequency timing circuit comprising a low frequency timing resistor and a low frequency timing capacitor, the low frequency timing resistor determining a magnitude of the current flowing, the direct current pair The low frequency timing capacitor is charged, the low frequency timing capacitor has a first end and a second end, the second end of the low frequency timing capacitor is coupled to a ground potential; a low frequency oscillator has an output, the low frequency oscillator output The end is coupled to the low frequency timing resistor and the first end of the low frequency timing capacitor, and controls the low frequency timing capacitor to be repeatedly charged and discharged to generate a low frequency ramp voltage at the first end of the low frequency timing capacitor; a low frequency pulse width modulation comparison The first input end, the second input end and the output end, the first input end of the low frequency pulse width modulation comparator receives a DC dimming signal, and the second input end of the low frequency pulse width modulation comparator Coupling to the first end of the low frequency timing capacitor, generating a low frequency pulse width modulation signal at the output of the low frequency pulse width modulation comparator, the low frequency pulse width modulation Each cycle of the signal includes a uniform energy period and a disable period; a feedback control circuit having a uniform energy end and an output end, the feedback control circuit enabling end coupled to the low frequency pulse width modulation comparator output end a driving signal is generated at the output of the feedback control circuit during the enabling period, and the driving signal is not generated at the output of the feedback control circuit during the disable period; and an AC signal generator having an output terminal The AC signal generator output is coupled to the first end of the low frequency timing capacitor, and an AC current is provided at the AC signal generator output.
  2. The control circuit of the inverter using pulse width modulation dimming as described in claim 1, further comprising: a comparator having a first input end, a second input end and an output end, the comparison The first input end of the device receives the DC dimming signal, the second input end of the comparator receives a set voltage, the set voltage is a peak voltage of the low frequency ramp voltage, and a switch has a first end and a second end And a control end, the first end of the switch is coupled to the output of the AC signal generator, the second end of the switch is coupled to the first end of the low frequency timing capacitor, and the switch control end is coupled to the output end of the comparator Wherein, when the DC dimming signal is greater than or equal to the set voltage, the output signal of the comparator output controls the switch to be disconnected, so that the output of the AC signal generator and the first end of the low frequency timing capacitor are disconnected. When the DC dimming signal is less than the set voltage, the output signal of the comparator output controls the switch to be turned on, so that the output end of the AC signal generator is coupled to the first end of the low frequency timing capacitor.
  3. The control circuit of the inverter using the pulse width modulation dimming as described in claim 2, further comprising: a diode having an anode end and a cathode end, wherein the anode end of the diode is coupled to the The second end of the switch is coupled to the first end of the low frequency timing capacitor.
  4. The control circuit of the inverter using the pulse width modulation dimming as described in claim 2, further comprising: a diode having an anode end and a cathode end, wherein the anode end of the diode is coupled to the An output of the AC signal generator, the cathode end of the diode being coupled to the first end of the switch.
  5. The control circuit of the inverter using pulse width modulation dimming as described in claim 1, further comprising: a comparator having a first input end, a second input end and an output end, the comparison The first input end of the comparator receives the DC dimming signal, the second input end of the comparator receives a set voltage, the set voltage is a peak voltage of the low frequency ramp voltage; and a diode has an anode end and a cathode end, a diode cathode end coupled to the first end of the low frequency timing capacitor; and a switch having a first end, a second end, and a control end, the first end of the switch being coupled to the output of the AC signal generator And the second end of the diode is coupled to the ground potential, the switch control end is coupled to the output of the comparator, wherein when the DC dimming signal is greater than or equal to the set voltage, the The output signal of the comparator output controls the switch to be turned on, so that the anode end of the diode is coupled to the ground potential. When the DC dimming signal is less than the set voltage, the output signal of the comparator output controls the switch to be turned off.
  6. The control circuit of the inverter using pulse width modulation dimming as described in claim 1, wherein the low frequency timing resistor has a first end and a second end, and the first end of the low frequency timing resistor is coupled The second end of the low frequency timing resistor is coupled to the low frequency oscillator output and the first end of the low frequency timing capacitor.
  7. The control circuit of the inverter using pulse width modulation dimming as described in claim 1, wherein the low frequency oscillator output comprises a first output end and a second output end, the low frequency timing resistor having a a first end and a second end, the first end of the low frequency timing resistor is coupled to the first output end of the low frequency oscillator, the second end of the low frequency timing resistor is coupled to the ground potential, and the low frequency timing capacitor is first The end is coupled to the second output of the low frequency oscillator.
TW98102080A 2009-01-20 2009-01-20 Controller circuit of inverter using pulse width modulation (pwm) dimming TWI404458B (en)

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US8548336B2 (en) * 2011-12-02 2013-10-01 Semtech Corporation Closed loop optical modulation amplitude control
TWI507084B (en) * 2013-02-05 2015-11-01 Univ Nat Kaohsiung Applied Sci Zero current switching module

Citations (3)

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Publication number Priority date Publication date Assignee Title
TWI252062B (en) * 2005-04-20 2006-03-21 Himax Tech Inc Method for driving a fluorescent lamp and inverter circuit for performing such a method
TW200707362A (en) * 2005-08-09 2007-02-16 Coretronic Corp Control circuit of backlight source and its method
TWI302808B (en) * 2006-04-14 2008-11-01 Gigno Technology Co Ltd Digital control circuit and system for lighting module

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI252062B (en) * 2005-04-20 2006-03-21 Himax Tech Inc Method for driving a fluorescent lamp and inverter circuit for performing such a method
TW200707362A (en) * 2005-08-09 2007-02-16 Coretronic Corp Control circuit of backlight source and its method
TWI302808B (en) * 2006-04-14 2008-11-01 Gigno Technology Co Ltd Digital control circuit and system for lighting module

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