201027891 . 六、發明說明： . 【發明所屬之技術領域】 本發明係有陳-種具動驗啟動之功率@數校正控制電路，藉由在 • 輸人級(I_ stage)及功率因數調整級(pFC血职）中連接一控制電路之設 計’令能控制切換功率開關的導通週期來使得輸入阻抗呈現電阻性，即輸 入電流與輸人電壓同相位’來提高功率因數，並且消除負載(bad)變動， 適用於電源供應器或類似結構者。 ❹【先前技術】 現今科技的發達，在有關電源的部份利也絲越歧，越來越多的 • 產品都會使用到電源供應器’尤其是在個人電腦、工業用電腦、交換機、 收銀機、印表設備·.....等等中需求AC/DC轉換電源，而藉由開關式結構來 ' 啟閉電源。 多數電器其工作電壓為直流電，其電源供應器第一級就是作交直流 (ACM)C)交換’常㈣方法就是彻二極體橋式整流器錢波電容來完 成，這個方法有著結構簡單和成本低廉的優點，但是因為阻抗非線性的關 係’將導致功因值低落，因此在整流後需加裝功因修正電路來改善功音值。 功因修正電路大致分為被動式(PassivePFC)及主動式(ActivePFC)，被動式 功因修正電路已非主流，而主動式功因修正電路係利用主動元件來控制輸 入電流波形，藉此達到提升功因值的目的。 在第1圖所示，係為習知升壓型功因修正電路(BoostPFC)之示意圖， 該升壓型功因修正電路大致上包括一輸入電路(Input circuital 〇 1、一前 調卽器(pre-regulator) 1 〇 4 及一輸出電路(output circuit) 1 〇 5。其中，在 3 201027891 -該前調節器1 0 4中包括一開關（switch)l Ο 6，逆向跨接一二極體i JL 〇 . 及一快恢復二極體1 Ο 8。在該功因修正電路中，切換損失(switchingl〇ss) 係源自於該開關1 0 6與快恢復二極體1 〇 8的切換動作，尤其是在如第！ •圖中電路中，當—交流電源(AC s_e)輸人至—橋式整脑（diGde bridge _fler)整流後’輸出直流至該前調節器1 04。該前調節器包括-由壹驗 ·'曰曰曰體開關1 0 6、一電感1 〇 7、-快恢復二極艘i 〇 8及一輸出電容丄 0 9構成的硬切換升麼轉換器。#開關i◦6關閉時，流經該電感丄〇 7 ®的電流至後級的輸出負載電路！◦5。上述電晶體工〇 6的開及關由閑極 G電壓控制。當開Q 6關閉時，因為該開〇 6的電壓上升，而流 過該開關的電流需要回復時間(a finite time)才麟到零，兩者產生有交越面 、積而造成切換損失(switching 1挪)者。 然，其上述架構操作時，會因交越面積而造成切換損失而發生效率低， 乃為其最主要之缺失。 . 本發明人有鑑於上述缺失，期能提供一種利用在輸入級(Inpmstage)及 H 功率因數校正級(pFC stage)中連接一控制電路之設計，達到提高效率之效 能，乃潛心研思、設計組製，以提供消費大眾使用，為本發明所欲研創之 發明動機者。 【發明内容】 本發明之主要目的係在提供一種具動態軟啟動之功率因數校正控制電 路，藉由在輸入級(Input stage)及功率因數校正級(PFC stage)中連接一控制 電路之設計’當PFC導通後，檢測準位(VEA0)若其為輕載(Hght 1〇ad)， 將改變内部之參考點使其電壓調降成設定電壓，以達提高效率者。 4 201027891 - 本發明之次一目的在提供一種具動態軟啟動之功率因數校正控制電 ' 路’藉由在輸入級(InPut stage)及功率因數校正級(pfc stage)中連接一控制 電路之設計’當橋式整流器電壓小於比較點電壓時’會將設定點之電壓切 換為2V ’以達到軟啟動(soft-start)之功能，以減少在動態時造成大電流現象 - 者。 ·· 為達上述之目的’本創作其主要係包括有：一開機軟啟動功率因數校 正電路（Soft-start)、一動態（Dynamic)軟式功率因數校正電路、一輕載 〇 (LlghtLoad)檢測開關電路及一校正電路；以電壓誤差放大器輸出端產生一 參考準位(VEAO)，該參考準位(VEA〇)具有控制提供給功率因數校正級 (PFC stage)之能量功能並檢測參考準位(VEA〇)，於開機前將其準位鉗位 ' (Clamp)於一低電壓，可使其將輸出的能量控制住，達到軟啟動(soft-start) • 的功能，藉此，當檢測準位(VEAO)為輕載(Light Load)，將使輕載(Light 、 Load)檢測開關電路中的開關調整内部回授分壓(VFB)，將功率因數輸出級 ， 之降至設定的電壓，以達零電壓電路(ZVS)之效能而提高效率者。 || 本發明之其他特點及具體實施例可於以下配合附圖之詳細說明中，進 一步瞭解。 【實施方式】 請參考第2、3圖，係為本發明之昇壓型轉換器動作電路圖，該具動 態軟啟動之功率因數校正控制電路係連接於輸入級(Input stage)l Q及功 率因數校正級(PFCstage)2 0中，而該輸入級(Inputstage) 1 0係設有橋式 整流電路1 1，以將輸入的交流電源（AC) 1 2轉換成直流電乂輸出者。 該功率因數校正級(PFC stage) 2 0係設有一升壓電感2 1、一功率開關2 5 201027891 '2、一快恢復一極體2 3、—輸出電容器2 4及-負載2 5 ’該升>1電感 2 1串聯功率卿2 2，而整流二極體2 3與輸出電容n 2 4串聯後再與 功率開關2 2並聯’且輸出電容！^ 4再並聯—負載2 5，以供調整功率 •因數提昇用電效率使電磁干擾（Electromagnetic Interfrence，EMI)雜訊 ·: (Pow—)簡合環保標準者。而該功率因數校正級(PFCstage) .· 2 0中的功率_ 2 2係為金屬氧化層半導體元件（MetaR)xide_201027891 . VI. Description of the Invention: [Technical Field] The present invention is a power-number correction control circuit with a start-up test, with an input stage (I_stage) and a power factor adjustment stage. (pFC blood) in the design of a control circuit to enable the control of the switching power switch's on-period to make the input impedance resistive, that is, the input current is in phase with the input voltage' to improve the power factor and eliminate the load (bad ) Changes, for power supplies or similar structures. ❹[Prior Art] Nowadays, the development of technology is becoming more and more different in terms of power supply. More and more products will use power supplies, especially in personal computers, industrial computers, switches, and cash registers. In the case of printing equipment, etc., AC/DC conversion power is required, and the switching structure is used to 'turn on and off the power supply. Most electrical appliances have a working voltage of direct current, and the first stage of the power supply is used for AC-DC (ACM) C) exchange. The (four) method is completed by the diode-bridge rectifier money-wave capacitor. This method has a simple structure and cost. The advantage of low cost, but because of the nonlinear relationship of impedance 'will lead to a low value of the work factor, it is necessary to add a power factor correction circuit to improve the work sound value after rectification. The power factor correction circuit is roughly classified into passive (Passive PFC) and active (ActivePFC). The passive power factor correction circuit is not mainstream, and the active power factor correction circuit uses active components to control the input current waveform, thereby improving the power factor. The purpose of the value. In the first figure, it is a schematic diagram of a conventional boost type power factor correction circuit (BoostPFC). The boost type power factor correction circuit generally includes an input circuit (Input circuital 〇1, a front modulator (pre- Regulator 1 1 及 4 and an output circuit 1 〇 5. Among them, in 3 201027891 - the front regulator 1 0 4 includes a switch l Ο 6, reverse bridging a diode i JL 〇. and a quick recovery diode 1 Ο 8. In the power factor correction circuit, the switching loss (switchingl〇ss) is derived from the switching action of the switch 1 0 6 and the fast recovery diode 1 〇8, Especially in the circuit as shown in Fig. • When the AC power supply (AC s_e) is input to the bridge (diGde bridge _fler), the output is DC to the front regulator 104. The front regulator Including - by the test · 'body switch 1 0 6, an inductor 1 〇 7, - fast recovery dipole i 〇 8 and an output capacitor 丄 0 9 constitute a hard switching converter. #开关i When ◦6 is off, the current flowing through the inductor 丄〇7 ® is output to the output load circuit of the subsequent stage! ◦ 5. The above-mentioned transistor work 6 is turned on and Controlled by the idler G voltage. When the open Q 6 is turned off, since the voltage of the opening 6 rises, the current flowing through the switch requires a recovery time (a finite time) to reach zero, and the two have a crossover. In the case of the above-mentioned architecture operation, the switching loss caused by the crossover area is inefficient, which is the most important deficiency. The present inventors have In the absence of the design, it is possible to provide a design that uses a control circuit in the input stage (Inpmstage) and the H power factor correction stage (pFC stage) to improve the efficiency. It is a research and design system to provide the consumer. The present invention is directed to providing a power factor correction control circuit with dynamic soft start by using an input stage and power factor correction. In the PFC stage, the design of a control circuit is connected. When the PFC is turned on, the detection level (VEA0), if it is a light load (Hght 1〇ad), will change the internal reference point to reduce the voltage to a set. The voltage is increased to improve efficiency. 4 201027891 - The second object of the present invention is to provide a power factor correction control circuit with dynamic soft start by using an input stage (InPut stage) and a power factor correction stage (pfc stage) In the design of a control circuit connected to 'When the bridge rectifier voltage is less than the comparison point voltage', the voltage at the set point is switched to 2V' to achieve the soft-start function to reduce the large current caused by dynamics. Phenomenon - person. ··············································································································· a circuit and a correction circuit; generating a reference level (VEAO) at the output of the voltage error amplifier, the reference level (VEA〇) having an energy function for controlling the power factor correction stage (PFC stage) and detecting the reference level ( VEA〇), clamping its level to a low voltage before turning it on, it can control the output energy to achieve the soft-start function. Bit (VEAO) is Light Load, which will adjust the internal feedback voltage division (VFB) of the switch in the light load (Light, Load) detection switch circuit, and reduce the power factor output stage to the set voltage. Improve efficiency by the efficiency of the zero voltage circuit (ZVS). Other features and embodiments of the present invention will be further understood from the following detailed description of the drawings. [Embodiment] Please refer to Figures 2 and 3, which are circuit diagrams of the boost converter of the present invention. The power factor correction control circuit with dynamic soft start is connected to the input stage (Q) and the power factor. In the correction stage (PFCstage) 20, the input stage 10 is provided with a bridge rectifier circuit 1 1 to convert the input AC power (AC) 12 into a DC output. The power factor correction stage (PFC stage) 20 is provided with a boosting inductor 2 1 , a power switch 2 5 201027891 '2, a fast recovery diode 2 3, an output capacitor 2 4 and a load 2 5 ' l > 1 inductor 2 1 series power 2 2, and the rectifier diode 2 3 is connected in series with the output capacitor n 2 4 and then connected in parallel with the power switch 2 2 'and output capacitance! ^ 4 and then parallel - load 2 5, for adjustment of power • Factor to improve the efficiency of electricity to make electromagnetic interference (Electromagnetic Interfrence, EMI) noise ·: (Pow -) simple environmental standards. And the power factor correction stage (PFCstage) .. 2 power _ 2 2 is a metal oxide semiconductor component (MetaR) xide_
Semiconductor)、接合面場效電晶體⑽τ)、金屬氧化物半導體場效電晶 ❹體（MOSFET)等其中任—者^其中該第2及3圖所示為—升壓型轉換器 (Boostconverter)型，態’由於其昇壓電感2 1直接與輸入電流_聯，因此升 壓電感21電流即為輸入電流’不但可以吸收輸入電源端的突波，且藉由 著升壓電感21電流即是輸入電流去控制電感電流追隨著輸入電壓的波 形’即可獲得高功率因數。而其動作原理可由一個切換週期内，功率開關 2 2的導通(ON)或截止(0FF)分為兩種狀態，其一(如第2圖所示），當功 率開關2 2為導通(ON)狀態時則輸入電壓VlN直接對升壓電感2丄充電， 6使得電感電壓vL等於輸入電壓VlN，此時快恢復二極體2 3是截止的，負 載2 5能量由輸出電容器2 4 (電容c)提供。其二（如第3圖所示），當 就是功率開關2 2切換到截止(off)狀態時，因為電感電流是連續的，使得 快恢復二極體2 3導通，輸入電壓vIN對輸出電容器2 4 (電容c)充電， 升麼電感2 1上的電壓VfVwV。為貞值，升壓電感2 1 Jl的電流里線性 下降，基於上述之原理，為了使功率開關2 2的導通時間保持一定，以避 免輸入錢產生失真，故整個系統迴路的交越頻率必須遠小於輸入電壓之 頻率，藉此，以使功率開關2 2導通能達到功因修正與輸出電壓穩壓的目 6 201027891 . 的0 研參考第4、5圖，係為本發明之具動態軟啟動之功率因數校正控制 電路之電路圖，該具動態軟啟動之功率因數校正控制電路係連接於輸入級 (Input Stage) 1 Q及功率因數校正級(PFC stage) 2 0中，該控制電路3 〇包 • 3有開機軟啟動功率因數校正電路(Soft-start) 3 1、一動態(Dynamic)軟 式功率因數校正電路3 2、-域(LightLoad)檢綱關電路3 3及-校正 電路3 4 ;該開機軟啟動功率因數校正電路(s〇ft_start)3丄係設有二開關3 ❷1 1、3 1 2、-過載保護比較器(〇VP)3 1 3及-稽納二極體(zenerdiode) 3 14該過載保護比較器3 1 3—輸入端係連接功率因數校正級(PFC： Stage)2 0的輸出端所感測的回饋電壓(VFB)2 6，該回鑛電壓（Vfb) 2 6 係由輸出電壓分流器& 2 7和R22 8所感測者，而過載保護比較器3工3 輸出端係連至第-開關311，以提供訊號啟閉電源輸入用，而第一開 11再提供-訊號至第二開關312，以供啟閉用，該第二開關31 2串連-稽納二極體3 i 4，以供形成穩壓，該稽納二極體3 η係連接 蠡於電壓誤差放大器泊㈣輸出端的準位(爾〇>，而該準位(徽。廊可 控制提供給功率因數校正級(PFC_Stage)之能量，於開機前將其準位鉗位 ㈣mP)於-低，可使則繼_量控舰，物軟啟動㈣細） 的功能，而當功率因數校正級(PFC_Stage)2 〇之輸出電壓達到所需之要求 P時’將其準位鉗位(clamp)釋放。該動態軟功率因數校正電路伽amic soft PFC)3 2係設有一比較器（CMp)3 2 1、一偏壓電路3 2 2，該比較器3 2 1係將偏壓電路3 2 2中產生的訊號與相對參考低電壓(α5ν)比較，而 產生一訊號進邏輯電路之反或閘’故，當橋式電壓小於比較點電麼時，會 201027891 - 將設定點之電壓切換為2V，以達到軟啟動（soft-start)之功能，例如：原本需 要達到380V之電壓，只要將其降低至3〇〇v即可，以減少在做動態時造成 之大電流情況。該輕載(Light Load)檢測開關電路3 3係設有二比較器 (CMP) 3 3 1、3 3 2、一邏輯電路(Logic circuit) 3 3 3、一電壓誤差放 -·· 大器（GMV)3 3 4及一開關3 3 5，該第一比較器3 3 1係將輸入電壓 *' (Vrms)與低參考電壓（1.75V)比較產生一訊號進邏輯電路3 3 3之反及 閘’而第二比較器3 3 2係將電壓誤差放大器3 3 4輸出端的準位(veao) 0 3 3 6與咼參考電壓（2.25V)比較產生一訊號進邏輯電路3 3 3之反及 閘’再從反及閘產生一訊號進邏輯電路3 3 3之反或閘，與動態軟式功率 因數校正電路3 2中所輸出之訊號比較，並從邏輯電路3 3 3之反或閘輸 ' 出一訊號來提供開關3 3 5切換設定的電壓，且該訊號再送入電壓誤差放 - 大器3 3 4之正輸入端，而電壓誤差放大器（GMv)3 3 4之負輸入端係連 • 接功率因數校正級(PFC Stage) 2 0的輸出端所感測的回饋電壓（VFB) 2 - 6，再從電壓誤差放大器3 3 4之輸出端產生一參考準位(VEAO)3 3 6， 0 故，當PFC導通後，檢測電壓誤差放大器3 3 4之輸出端的參考 準位(VEA0)3 3 6 ’若其為輕載(Light Load)，將改變内部之參考點使其 電壓降下成設定電壓’以達到提高效率之功能。該校正電路3 4係設有一 增益調制器（gain Modulator)3 4 1、一電流誤差放大器（GMI)3 4 2及一 比較器（CMP)3 4 3，該增益調制器3 4 1係將電壓誤差放大器3 3 4之 輸出端產生的參考準位(VEAO)3 3 6、輸入電壓(Vrms)及交流電流(IAC) 經偏壓電路3 2 2所產生的訊號作一調制，而增益調制器（gain Modulator) 3 4 1輸出一訊號給電流誤差放大器（GMI)3 4 2，該電流誤差放大器 8 201027891 - (GMI)3 4 2再與通過電阻之電流相比較’進而產生一訊號至比較器（cmp) - 3 4 3中再與斜波(Ramp)電壓比較，比較後輸出一控制訊號(pFC OUT)， 以控制功率因數校正級(PFC stage) 2 0中的功率開關2 2導通/截止者。 請參考第6、7、8圖，其中該動態軟式功率因數校正電路之偏壓電 - 路322係為基本電流鏡(current mirror)(如第4圖所示），該電流鏡設有二 ·- 個電晶體Q 1、Q2，假設該電晶體Q 1與電晶體<32均操作在飽合區， 則我們可由飽和區電晶體的電流公式推導出，因此若是希！Iin=i〇ut只要使 參電晶體Q1、Q2的尺寸相等便可以達到。但是實際並非如此，在電路的 操作上，要得到百分之百的電流相等，電晶體Q1、〇2的尺寸相等的條 件是不夠的，因為我鑛略了電晶、Q2的二階效應—通道長度調 變效應(channel length mod ulation)，若是把此一效應寺慮進來電流的比 值不在簡單的尺寸比，與電晶體Q i、q 2汲極(恤)和原極(晴⑹的電 -壓差亦有關係，換句話說’從電晶體q工、Q 2的祕看到的輸出電阻為 •有限值’而且當vds錢動時，將造成流過電晶體Q工、Q 2的電流也隨之 ©變化’因此’使用電流鏡來作偏壓電路3 2 2可以使電路對電源供應變動 .與溫度變動所造成的效應較不靈敏。另該偏壓電路3 2 2亦可為威爾遜電 流鏡Cent mirror)(如第5圖所示），該電流鏡設有三個電晶體Q 3、Q 4、 Q 5者。另其中該校正電路3 4中進—步設有一振盪器（⑽m敵）3 4 4、 及邏輯電路3 4 5，該邏輯電路3 4 5設有反及閘(NAND)及正反器(Fiip F1〇P)34 6 ’該振盪器3 4 4—端係連接斜波產生器(Ramp)，—端係連接 邏輯電路3 4 5之反及閘及正反器3 4 6，而校正電路3 4中之比較器3 4 3所輸出訊號係輸入邏輯電路3 4 5之反及閘，且邏輯電路3 * $之反 9 201027891 訊號至正反11 3 4 6中，岐反㈣4 6中繼-控㈣ 號⑽制辨因數校酬Prcstage)2 Q饰力侧2 2導通/截止， 確保每-切換週期只有一次脈波輸出，減少雜訊干擾，因此可看出經由主 動式肌所得之平均電流波形為一完整之弦波，且其相位與AC電源同相者。 由以上可知，以本發明之結構，具有如下之優點··Semiconductor, bonded field effect transistor (10) τ), metal oxide semiconductor field effect transistor (MOSFET), etc., where the second and third figures are - boost converters (Boostconverter) Type, state 'Because its boost inductor 2 1 is directly connected to the input current _, the boost inductor 21 current is the input current' not only can absorb the surge at the input power supply terminal, but also the current through the boost inductor 21 The input current is used to control the inductor current to follow the waveform of the input voltage' to achieve a high power factor. The operation principle can be divided into two states, one (as shown in FIG. 2), when the power switch 22 is turned on (ON), in one switching cycle, the power switch 22 is turned on or off (0FF). In the state, the input voltage VlN directly charges the boosting inductor 2丄, 6 so that the inductor voltage vL is equal to the input voltage VlN, at which time the fast recovery diode 2 3 is turned off, and the load 25 energy is output capacitor 2 4 (capacitance) c) Provided. Second, as shown in Fig. 3, when the power switch 2 2 is switched to the off state, since the inductor current is continuous, the fast recovery diode 2 is turned on, and the input voltage vIN is applied to the output capacitor 2 4 (capacitor c) charge, rise the voltage VfVwV on the inductor 2 1 . For the 贞 value, the current of the boost inductor 2 1 Jl decreases linearly. Based on the above principle, in order to keep the on-time of the power switch 2 2 constant, to avoid distortion of the input money, the crossover frequency of the entire system loop must be far. The frequency is less than the input voltage, so that the power switch 2 2 can be turned on to achieve the power factor correction and the output voltage voltage regulation. The reference is shown in Figures 4 and 5, which is a dynamic soft start of the present invention. A circuit diagram of the power factor correction control circuit, the power factor correction control circuit with dynamic soft start is connected to an input stage 1 Q and a power factor correction stage (PFC stage) 20, the control circuit 3 • 3 has a soft-start power factor correction circuit (Soft-start) 3 1. A dynamic soft power factor correction circuit 3 2. A domain (LightLoad) calibrator circuit 3 3 and a correction circuit 3 4 ; Start-up soft-start power factor correction circuit (s〇ft_start) 3丄 is equipped with two switches 3 ❷ 1 1 , 3 1 2, - overload protection comparator (〇 VP) 3 1 3 and - zener diode (zenerdiode) 3 14 overload protection comparator 3 1 3 - lose The end is connected to the feedback voltage (VFB) 2 sensed by the output of the power factor correction stage (PFC: Stage) 20, and the return voltage (Vfb) 2 6 is output voltage shunts & 2 7 and R22 8 The sensor, and the overload protection comparator 3 output 3 is connected to the first switch 311 to provide signal input and output power input, and the first switch 11 provides a signal to the second switch 312 for opening and closing. The second switch 31 2 is connected in series with the sigma diode 3 i 4 for forming a voltage regulation, and the sigma diode η is connected to the level of the voltage error amplifier (4) output terminal. >, and the level (the emblem. The gallery can control the energy supplied to the power factor correction stage (PFC_Stage), and clamp its position (four) mP) to - low before starting the machine, so that it can continue to control the ship. Soft start (4) fine) function, and when the output voltage of the power factor correction stage (PFC_Stage) 2 达到 reaches the required requirement P, 'release its clamp clamp. The dynamic soft power factor correction circuit is provided with a comparator (CMp) 3 2 1 and a bias circuit 3 2 2 , and the comparator 3 2 1 is a bias circuit 3 2 2 The signal generated in the signal is compared with the relative reference low voltage (α5ν), and a signal is generated into the inverse of the logic circuit. Therefore, when the bridge voltage is less than the comparison point, 201027891 - the voltage of the set point is switched to 2V. In order to achieve the soft-start function, for example, the voltage needs to reach 380V, as long as it is reduced to 3〇〇v, to reduce the large current caused by the dynamics. The light load detection switch circuit 3 3 is provided with two comparators (CMP) 3 3 1 , 3 3 2, a logic circuit (3 3 3), a voltage error amplifier-·· GMV)3 3 4 and a switch 3 3 5, the first comparator 3 3 1 compares the input voltage *' (Vrms) with a low reference voltage (1.75V) to generate a signal into the logic circuit 3 3 3 The second comparator 3 3 2 compares the level of the output of the voltage error amplifier 3 3 4 (veao) 0 3 3 6 with the reference voltage (2.25V) to generate a signal into the logic circuit 3 3 3 The gate then generates a signal from the inverse gate to the inverse of the logic circuit 3 3 3, compares it with the signal outputted by the dynamic soft power factor correction circuit 32, and reverses or gates from the logic circuit 3 3 3 ' A signal is sent to provide the switch 3 3 5 to switch the set voltage, and the signal is sent to the positive input of the voltage error amplifier 3 3 4, and the negative input of the voltage error amplifier (GMv) 3 3 4 is connected. The feedback voltage (VFB) 2 - 6 sensed at the output of the power factor correction stage (PFC Stage) 20 is generated from the output of the voltage error amplifier 3 3 4 A reference level (VEAO) 3 3 6, 0, when the PFC is turned on, the reference level (VEA0) 3 3 6 ' of the output of the voltage error amplifier 3 3 4 is detected. If it is a light load, Change the internal reference point to lower the voltage to the set voltage 'to achieve the function of improving efficiency. The correction circuit 34 is provided with a gain modulator 3 4 1 , a current error amplifier (GMI) 3 4 2 and a comparator (CMP) 3 4 3 , the gain modulator 34 1 is a voltage The reference level (VEAO) 3 3 6 , the input voltage (Vrms) and the alternating current (IAC) generated at the output of the error amplifier 3 3 4 are modulated by the signal generated by the bias circuit 32 2, and the gain modulation is performed. Gain Modulator 3 4 1 output a signal to the current error amplifier (GMI) 3 4 2, the current error amplifier 8 201027891 - (GMI) 3 4 2 and then compare with the current through the resistor 'and then generate a signal to compare (cmp) - 3 4 3 is compared with the ramp voltage, and a control signal (pFC OUT) is output after comparison to control the power switch 2 2 in the power factor correction stage (PFC stage) 20 Deadline. Please refer to Figures 6, 7, and 8, wherein the bias voltage circuit 322 of the dynamic soft power factor correction circuit is a basic current mirror (as shown in Fig. 4), and the current mirror is provided with two - A transistor Q 1 , Q2, assuming that both the transistor Q 1 and the transistor < 32 operate in the saturation region, we can derive from the current formula of the saturation region transistor, so if it is! Iin=i〇ut can be achieved by making the dimensions of the reference transistors Q1 and Q2 equal. But this is not the case. In the operation of the circuit, to obtain 100% of the current is equal, the conditions of the equal size of the transistors Q1 and 〇2 are not enough, because I have a second-order effect of the electro-crystal, Q2-channel length modulation. Effect (channel length mod ulation), if the ratio of the current into this effect temple is not a simple size ratio, and the electro-pneumatic difference between the transistor Q i, q 2 bungee (shirt) and the original pole (clear (6) It is related, in other words, 'the output resistance seen from the crystal q, the secret of Q 2 is finite value' and when the vds move, it will cause the current flowing through the transistor Q and Q 2 to follow. ©Change 'so' uses a current mirror as the bias circuit 3 2 2 to make the circuit supply power supply changes. The effect caused by temperature fluctuations is less sensitive. The bias circuit 32 2 can also be Wilson current The mirror (as shown in Fig. 5) is provided with three transistors Q3, Q4, and Q5. In addition, the correction circuit 34 is further provided with an oscillator ((10)m enemy) 3 4 4 and a logic circuit 34 5 , and the logic circuit 3 4 5 is provided with a NAND and a flip flop (Fiip) F1〇P)34 6 'The oscillator 3 4 4 - the end is connected to the ramp generator (Ramp), the end is connected to the logic circuit 3 4 5 and the gate and the flip-flop 3 4 6, and the correction circuit 3 The comparator 3 4 3 output signal is the inverse of the input logic circuit 3 4 5, and the logic circuit 3 * $ counter 9 201027891 signal to the positive and negative 11 3 4 6 , 岐 反 (4) 4 6 relay - Control (4) No. (10) Discrimination factor Prcstage) 2 Q trim side 2 2 on/off, ensuring only one pulse output per switching cycle, reducing noise interference, so the average current obtained through active muscle can be seen The waveform is a complete sine wave and its phase is in phase with the AC power supply. From the above, it can be seen that the structure of the present invention has the following advantages:
1、 本發明係為輸出負載（卿utload)大而參考準位（vEA〇)相對大， 而回饋電壓（VPB)為霸，_輯（GutputlGad)小醇考準位 (VEAO)相對小，而回饋電壓（Vfb)為3_，以提高效率者。 2、 本發鶴當橋式電壓小槪無電壓時，會將設定點之電壓切換為 以達到軟啟動(soft-start)之功能，例如：原本需要達到38〇v之電壓， 只要將其降低至3〇OV即可，以減少在做動態時造成之大電流情況者。 由以上詳細說明，可使熟知本項技藝者明瞭本發明的確可達成前述目 的’實已符合專利法之規定，爰提出專利申請。 惟以上所述者，僅為本發明之較佳實施例而已，#不能以此限定本創 6 作實施之範圍；故，凡依本發明申請專利範圍及發明說明書内容所作之簡 單的等效變化與修飾’皆應仍屬本發明專利涵蓋之範圍内。 【圖式簡單說明】 201027891 . 第1圖係為習知升壓型功因修正電路(BoostPFC)之示意圖。 第2圖係為本發明之升壓型轉換器導通動作電路之示意圖。 第3圖係為本發明之升壓型轉換器截止動作電路之示意圖。 • 第4圖係為本發明之具動態軟啟動之功率因數校正控制電路之方塊圖 ： 第5 ®係林發明之具_軟聽之辨目雜正控魏路之電路圖。 ·· 第6圖係為本發明之偏壓電路第一示意圖。 第7圖係為本發明之偏壓電路第二示意圖。1. The present invention is that the output load (clear utload) is large and the reference level (vEA〇) is relatively large, and the feedback voltage (VPB) is the tyrant, and the guttap (GutputlGad) small alcohol test level (VEAO) is relatively small, and The feedback voltage (Vfb) is 3_ to improve efficiency. 2. When there is no voltage in the bridge type voltage, the voltage of the set point is switched to achieve the function of soft-start. For example, the voltage of 38〇v is required to be reduced. It can be up to 3〇OV to reduce the large current caused by dynamics. From the above detailed description, it will be apparent to those skilled in the art that the present invention can indeed achieve the above-mentioned objectives. However, the above description is only a preferred embodiment of the present invention, and # does not limit the scope of implementation of the present invention; therefore, the simple equivalent change made by the scope of the patent application and the contents of the invention description of the present invention And the modifications 'should be within the scope of the invention patent. [Simple description of the drawing] 201027891 . Fig. 1 is a schematic diagram of a conventional boost type power factor correction circuit (BoostPFC). Fig. 2 is a schematic view showing the on-operation circuit of the boost converter of the present invention. Figure 3 is a schematic diagram of the step-down operation circuit of the boost converter of the present invention. • Figure 4 is a block diagram of the power factor correction control circuit with dynamic soft start of the present invention: The circuit diagram of the fifth invention of the invention is based on the circuit diagram of the invention. · Figure 6 is the first schematic diagram of the bias circuit of the present invention. Figure 7 is a second schematic view of the bias circuit of the present invention.
第8圖係為本發明之具動態軟啟動之功率因數校正控制 路圖。 電路之另― 態樣電 【主要元件符號說明】 1 0 1、輸入電路(Input circuit) 1 0 4、前調節器(pre-regulator) 1 0 5、輸出電路(output circuit) 1 0 6、開關 ^ 1 0 7、電感 ‘ 1 0 8、快恢復二極體 109、輸出電容 110、二極體 1 0、輸入級(InPut stage) 11、 橋式整流電路 12、 交流電源 11 201027891 2 0、功率因數校正級(PFC stage) 21、升壓電感 2 2、功率開關 2 3、快恢復二極體 - 2 4、輸出電容器 2 5、負載 2 6、回饋電壓(vFB) ❻ 2 7、電壓分流器 2 8、電壓分流器 3 0、控制電路 3 1、開機軟啟動功率因數校正電路（Soft-start) 311、 開關 312、 開關 3 1 3、過載保護比較器（OVP) 办 3 1 4、稽納二極體(zener diode) ‘ 3 2、動態(Dynamic)軟式功率因數校正電路 3 2 1、比較器（CMP) 3 2 2、偏壓電路 3 3、輕載(Light Load)檢測開關電路 3 3 1、比較器（CMP) 3 3 2、比較器（CMP) 3 3 3、邏輯電路(Logic circuit) 12 201027891 . 3 3 4、電壓誤差放大器（GMV) . 3 3 5、開關 3 3 6、參考準位(VEAO) 3 4、校正電路 參 - 3 4 1、增益調制器（gainModulator) · 3 4 2、電流誤差放大器（GMI) 3 4 3、比較器（CMP) ❹ 3 4 4、振盪器（osciltator) 3 4 5、邏輯電路 3 4 6、正反器（Flip Flop) - Q1、電晶體 . Q2、電晶體 ~ Q 3、電晶體 - Q4、電晶體 φ Q5、電晶體 13Figure 8 is a power factor correction control road diagram with dynamic soft start of the present invention. Another mode of the circuit - the main component symbol description 1 0 1. Input circuit 1 0 4, pre-regulator 1 0 5, output circuit 1 0 6, switch ^ 1 0 7. Inductance '1 0 8. Fast recovery diode 109, output capacitor 110, diode 10, input stage (InPut stage) 11, bridge rectifier circuit 12, AC power supply 11 201027891 2 0, power Factor correction stage (PFC stage) 21, boost inductor 2, power switch 2 3, fast recovery diode - 2 4, output capacitor 2 5, load 2 6, feedback voltage (vFB) ❻ 2 7, voltage shunt 2 8, voltage shunt 3 0, control circuit 3 1, start soft start power factor correction circuit (Soft-start) 311, switch 312, switch 3 1 3, overload protection comparator (OVP) to do 3 1 4, Jen Zener diode ' 3 2. Dynamic soft power factor correction circuit 3 2 1. Comparator (CMP) 3 2 2. Bias circuit 3 3. Light load detection switch circuit 3 3 1. Comparator (CMP) 3 3 2. Comparator (CMP) 3 3 3. Logic circuit 12 201027891 . 3 3 4. Voltage Error Amplifier (GMV) . 3 3 5, Switch 3 3 6. Reference Level (VEAO) 3 4. Correction Circuit Reference - 3 4 1. Gain Modulator (3) 4. Current Error Amplifier (GMI) 3 4 3. Comparator (CMP) ❹ 3 4 4. Osciltator 3 4 5. Logic circuit 3 4 6. Flip Flop - Q1, transistor. Q2, transistor ~ Q 3. Transistor - Q4, transistor φ Q5, transistor 13