TW201027100A - Test system for testing a signal path and method for testing a signal path - Google Patents

Abstract

A test system for testing a signal path comprises a test signal generator and a signal processing means. The test signal generator comprises a modulator and a phase-locked loop, wherein the phase-locked loop of the test signal generator is configured to provide a test signal and couple it into the signal path under test. The modulator of the test signal generator is configured to enable a phase modulation of the test signal. The signal processing means is configured to receive and process the test signal, wherein the signal path under test extends from the phase-locked loop of the test signal generator to the signal processing means. A method for testing a signal path comprises the steps of generating a test signal by a test signal generator, coupling the test signal into the signal path, receiving the test signal by the signal processing means and assessing the test signal received.

Description

201027100 VI. Description of the invention: [Technical employee domain to which the invention pertains] According to the invention (4) of the present invention, a test system in which the test system includes - (PLL), and a method of path. Phase-modulated phase-locked loop

Test of PIX (4) (4) c = RF integrated circuit). Other embodiments in accordance with the present invention relate to measurements that use the phase change of the PLL to perform a mismatch with the initial/quadrature phase (I/Q). BACKGROUND OF THE INVENTION Testing the undesirable, non-linear, asymmetrical or mismatched signal paths of an integrated circuit (for example) or evaluating the quality of a signal path is an important factor in ensuring that the circuit operates correctly. For this reason, there is often a lot of effort to test the signal path of the integrated circuit by means of accumulation self-test or by some expensive external test control. An example of a known test equipment for an RFIC is shown in Figures 2 and 3. Figure 2 shows a block diagram of RFIC 200 showing the component equipment of RFIC 200. Here, the transmitter 210 and the receiver 250 of the RFIC 200 are illustrated in the upper and lower halves, respectively. Transmitter 210 includes an in-phase branch 212 and a quadrature phase branch 214. The in-phase branch 212 of the transmitter 210 is passed through the in-phase/quadrature phase mixer 218 to the combiner 230 by a low pass ferrite 216 (LPF). The quadrature phase branch 214 of the transmitter 210 is passed through the in-phase/quadrature phase mixer 218 to the combiner 230 by an additional low pass filter 216. The inphase/quadrature phase mixer 3 201027100 218 is provided with an in-phase signal from a phase-locked loop 220 (PLL) and a phase-shifted signal through a phase shifting unit 222 (e.g., twist/90 degrees). Combiner 230 superimposes the signals in in-phase branch 212 to align the signals in phase branch 214 and allows the overlapped signals to be utilized by programmable gain amplifier 224 (PGA). The programmable gain amplifier 224 is coupled to one of the outputs of the transmitter TX via a power amplifier 226 (PA). At the input (RX), the receiver includes a low noise amplifier 266 (LNA) coupled to a programmable gain amplifier 264. After the programmable gain amplifier 264, the split 270 is formed into an in-phase branch 252 and a quadrature phase branch 254', wherein the in-phase branch 252 and the quadrature phase branch 254 comprise a phase/quadrature phase mixer 258 and each include A low pass filter 256. The in-phase/quadrature phase mixer 258 is coupled to a phase locked loop 260 via a phase shifting unit 262. Suitably, Figure 3 shows a known test system 300 for testing the RFICi signal path, wherein the signal path is extended by the transmitter to the receiver. Used here 'requires two precision excitations 31〇, 32〇 (Stiml, Stim2) such as function generator (AWG=arbitrary wave generator) for generating test signals, and requires two precision response analyzers 34〇, 35 〇 (Respl, Resp2) such as a digitalizer (DTZ) to evaluate the test signal. In addition, in this example, the (four) path between the receiver and the transmitter has an attenuator 33A (Au) to adjust the high τχ power level (τχ: transmitter or transmission) to a low rx power level (RX). : Receiver or Receive). Thus, a so-called loopback test can be used, for example, to test the evaluation response and the degree of non-linearity as an indicator of whether rfic functions to a certain degree of significance. 201027100 The use of function generators 310, 320 for generating test signals and the use of precision analyzers 340, 350 for evaluating test signals indicates that implementation is labor intensive and expensive. This also applies to the direct integration of function generators and analyzers into the circuit, as well as for controlling the integrated circuit by an external function generator and/or evaluating the test signals by an external analyzer. For example, in ES Erdogan, S. Ozev, "Integrated SBIST Solution for IQ Modulated RF Transceivers", a method is shown, assuming in-phase in-phase/quadrature phase (I/Q) digits to Analog converters (DACs) and integrated in-phase/quadrature phase analog to digital converters (ADCs), or hypothetical (expensive) external instrumentation to generate precision inputs for TX in-phase/quadrature phase inputs The waveform is used to accurately digitize the in-phase/quadrature phase RX output waveform. In conjunction with the RFIC illustrated in Figure 2, Figure 4 shows a block diagram of the RPIC 400, such as the asymmetry or mismatch that may occur when using the in-phase/quadrature phase architecture. For example, such asymmetry is a phase mismatch 410, 430 between the in-phase branch 212 and the quadrature phase branch 214, and a gain mismatch 420, 440 in the in-phase branch 212 and the quadrature phase branch 214. For example, such interference may occur independently of the transmitter (Τχ) and the receiver (RX). For example, this equivalent phase/quadrature phase mismatch causes distortion of the transmitted signal or test signal and is therefore of considerable importance for measurements used for testing or calibration. Measurements of in-phase/quadrature phase mismatch in such RF transceivers, for example, can be performed without the need for expensive equipment or calibration. As shown in Figure 4, the phase mismatch of the transmitter (TX), the phase mismatch of the receiver 201027100 (RX), the gain mismatch of the transmitter (TX), and the gain mismatch of the receiver (RX), for example, indicate that Value. I: SUMMARY OF THE INVENTION 3 SUMMARY OF THE INVENTION It is an object of the present invention to provide a test system and method for a simple and cost effective test signal path. This item can be solved by applying the device of the first item of the patent scope and the method of claim 12 of the patent application. Embodiments of the present invention provide a test system for testing a signal path, including a test signal generator and a signal processing device, wherein the test signal generator includes a modulator and a phase locked loop. Here, the phase locked loop of the test signal generator is configured to provide a test signal and couple the test signal to the signal path to be tested. The modulator of the test signal generator is coupled to the phase locked loop of the test signal generator and is configured to allow phase modulation of the test signal. The signal processing device is configured to receive and process test signals. The signal path to be tested here extends from the phase locked loop of the test signal generator to the signal processing device. According to still another embodiment of the present invention, a method for testing a signal path is provided. First, a test signal generator is used to generate a test signal, wherein the test signal generator includes a modulator and a phase locked loop. The phase locked loop of the test signal generator is configured to provide a test signal and couple the test signal to the signal path, and wherein the test signal generator is configured to allow phase of the test signal Modulation. Subsequently, the test signal is coupled to the signal path, and then the test signal is received by a 201027100 signal processing device, wherein the signal processing device is configured to receive and process the signal, and the path of the signal is determined by The test letter of the ship n is an extension of the money processing device. An evaluation of the test signals received from the signal processing device is then performed to perform a signal path evaluation. Embodiments in accordance with the present invention are based on the central concept described below, using a phase-locked loop to provide a test signal and to connect the test signal

丄—^ ”, after the heart has passed the signal path to be tested, and is received and processed by the ## processing device. The test signal is provided by using a phase-locked phase-locked number generator: no longer needed The expensive phase of the phase is modulated by the "phase loop, and the circuit is already present in the lock signal without any phase modulation = _ test signal path. The extra effort can easily change the 1 integral circuit The use of this is less, through the use of phase-modulated phase-locked, ^~ phase-locked loops. This is the test system of this benefit. This can reduce the cost of providing a simple and versatile generator. A test device (e.g., a function in accordance with a number of implementations of the present invention to perform the evaluation of the money path by evaluating the configuration quality of the processing device to evaluate the signal path to a number of implementations in accordance with the present invention. a transformer and a phase-locked loop, wherein the 仏d仏 processing device includes a configuration to provide a reference signal, and a phase-locked loop system configuration of the second processing device to allow the modulator to lock the signal processing device Interest Phase modulation. 7 201027100 According to several additional embodiments of the present invention, including a low pass ferrite disposed in the signal path, wherein the low pass chopper comprises a base of a phase locked loop that is less than the test signal generator Frequency cutoff frequency (also known as angular frequency). The signal processing device then evaluates the quality of the signal path, for example by evaluating the filtered test signal. In some embodiments according to the invention, the mixer is disposed in the signal path, and Is configured to mix the test signal with a reference signal. The signal processing device then evaluates the quality of the signal path by, for example, evaluating the mixed test signal. BRIEF DESCRIPTION OF THE DRAWINGS The implementation of the present invention will be described in detail hereinafter with reference to the accompanying drawings For example, Figure 1 is a block diagram of a test system for testing signal paths; Figure 2 is a block diagram of an RFIC; Figure 3 is a block diagram of a known test system for testing the signal path of an RFIC. Figure 4 is a block diagram of a significant non-ideal isophase/quadrature-based RFIC; Figure 5 is a modulated ADPLL (ADPLL = full digital phase lock) Block diagram of Figure 6; Figure 6 is a block diagram of a test system for testing the signal path for determining the frequency dependence asymmetry of the signal path; Figure 7 is a spectrum of the test signal after passing the ideal signal path; Figure 8 is a block diagram of a test signal after passing a signal path with frequency dependence asymmetry, 201027100 Figure 9 is a block diagram of a test system for testing a signal path with a device for compensating for time delay; Figure 10 is a block diagram of a test system used to test the nonlinearity of the signal path to test the 仏 path; Figure 11 is a spectrum of a test signal after passing through a signal path with non-linearity; Figure 12 Block diagram for LINC Transmitter (LINC = Linear Amplification with Nonlinear Components); ® Figure 13 is a block diagram of a test system for LINC-based RFICs used to test signal paths; Figure 14 is a polar modulation Block diagram of the transmitter; v Figure 15 is a block diagram of a test system for testing a signal path based on a polarity-based RFIC; Figure 16 is an RFIC for in-phase/quadrature-based phase Block diagram of the test system used to test the signal path; φ Figure 17 is a schematic model of the in-phase/quadrature-phase RFIC with loopback test configuration; Figure 18 is a diagram for determining two phase-modulated locks A schematic model description of a test system with interesting slopes; Figure 19 is an illustration of a device for providing equal signal levels. Figure 2 is a flow chart of a method for testing a signal path. [Implementation of Cold Mode] Detailed Description of the Preferred Embodiments Fig. 1 is a block diagram showing a test system 100 for testing the Cree Parker 201027100 102 according to the embodiment of the present invention. The test system 100 includes a test signal generator 110 and a signal processing device 140. The test signal generator 110 includes a modulator 120 and a phase locked loop 130. The phase locked loop 130 of the test signal generator 110 is configured to provide a test signal and to connect the test signal to the signal path 102 to be tested. The test signal generator 1 1 is coupled to the phase locked loop 13 of the test signal generator 110 and is configured to allow phase modulation of the test signal. Signal processing device 14 is configured to receive and process the test signal. Here, the signal path 102 to be tested is extended by the phase locked loop 130 of the test signal generator 110 to the signal processing device 14A. ® Here, the function generator for generating the test signal for the test signal path 1〇2 is no longer required. The test system 100 can thus be easily or cost effectively manufactured or assembled. - For example, the integrated circuit implementation test system 100 is easy to implement because, in many integrated circuits, a phase-modulated phase-locked loop already exists for testing the signal path. In the integrated circuit without a phase-modulated phase-locked loop, the accumulation of the modulator and the phase-locked loop becomes possible with a small amount of extra effort. The phase-modulated phase-locked loop 130 can be configured, for example, as an ADPLL (all-digital phase-locked loop). An example of an example of a modulated ADPLL 500 is shown in Figure 5. The ADPLL 500 includes a modulator 120 (Mod), a phase accumulator 510 (phase accum), a time to digital converter 520 (TDC), a low pass filter 530, and a digitally controlled oscillator 540 (DCO). . To generate a test signal at output 542 of digitally controlled oscillator 540, reference signal 502 (REF) is provided to phase accumulator 510 and time to digital converter 10 201027100 520. The phase accumulator 510 and the output signal of the time-to-digital converter 52 重叠 overlap the # sign (p(t)' of the s-variant 120 and are provided through the low-pass filter 530 after further overlapping the signal φ(1) of the modulator 12〇. The digitally controlled oscillator 540. In addition, the output signal of the digitally controlled oscillator 54 is returned to the digital converter 520. With this configuration, the output is provided to the output 542 of the digitally controlled oscillator 540. The modulated test signal (eg sin(tot+<p(t)) ° is not like the analog analog phase-locked loop, ADPLL 5〇〇 can be digitally phase-modulated due to the digitally controlled oscillator input signal and The phase error is a digital character, allowing for simple but extremely accurate and non-intrusive modulation (for testing purposes). This also applies to the component-N phase-locked loop to a lower degree where the steady-state phase is fine Post-control, but dynamic phase modulation is affected by analog loop dynamics. Figure 6 shows a test system for testing signal paths for determining frequency dependence asymmetry in signal paths in accordance with the present invention. 600 square The test system 6A includes the modulator 12A (M〇d), a phase locked loop 130 (PLL), a circuit under test 61 (CUT) which is part of the signal path, and a mixer 620, a low pass filter 63 〇 (LpF), and a detector 640 (Det) 'where the detector 64 〇 belongs to the signal processing device 14 。. Here, the signal path from the phase lock The loop 13〇 extends through the circuit under test 61〇, through the mixer 620, and through the low-pass filter 63〇 to the detector 64〇. As a result, the output of the 忒 phase-locked loop 130 is coupled to the signal path to be tested, and is transmitted through An additional path 602 is coupled directly to the input of the mixer 62. The mixer 6200 is configured to mix the test signal ι(ι) that proceeds along the signal path and interacts with the 201027100 circuit 610 to be tested, with the original test signal Φ(1) (for example, Φ(1)=cos(0)t+(P(1))' where φ(1) corresponds to the phase modulation signal of the modulator 120, and the original test signal Φ(1) is directly derived from the lock through the extra path 6〇2. The phase loop 13 〇. The mixed test signal X(t) is filtered by the low pass filter 63 and then Provided to the detector 640. Here, the low pass filter 63A includes a cutoff frequency smaller than the fundamental frequency of the phase locked loop 13A. Thereby, the frequency portion and the higher frequency portion of the original test signal are filtered out.

The filtered test signal y(t) is then tested by the detector 640 of the signal processing device i4 and can be evaluated to detect the frequency dependence asymmetry of the signal path so as to be related to the quality of the signal path. statement.

After passing through the ideal signal path, the spectrum 7〇〇 of the test signal is shown as an example of Figure 7. The test signal remains unchanged as it passes through the ideal signal path. As such, the mixer 620 mixes the signal with itself. Here, except for the DC voltage portion 704, only the frequency portion 702 of the double range of the fundamental frequency 73 锁 of the phase locked loop appears. The fundamental frequency 720 of the phase locked loop is labeled ω. Further, in Fig. 7, the example shows the characteristic 71 of the low pass filter (LPF). The ideal signal path or the performance of the ideal circuit under test, which is part of the signal path, can be expressed mathematically as follows, for example: ψ(1)=Φ(1) jc(t)=<I>2(t)=cos2((〇t+cp(t )) =0,5 l + cos(2<yi + 2 furnace (〇

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Filtered _〇ut y(t)=0,5 12 201027100 As such, the mixed and filtered test signal 7(1) is only the Dc signal. Figure 7 shows that the spectrum before filtering by the low-pass filter has the following values: ω=2π·43 φ(〇=0,2·8ΐη(2π·3·ΐ) φ'(1)=cp(t) aptly, Figure 8 shows the spectrum of the test signal after passing through a signal path with a frequency dependence asymmetry. In other words, the circuit or the signal path to be tested has a non-mature or non-flat frequency response. This means that when passing the signal path When the frequency of the spectrum of some or all of the test signals is amplified or attenuated with different intensities, the phase modulation with the frequency Ω is obtained symmetrically centered on the fundamental frequency of the phase lock (also referred to as the carrier (frequency)). This symmetry is destroyed by the circuit under test or the signal path to be tested with different attenuations on both sides of the frequency 1^^ and ω+1ίΩ 0, resulting in low frequency content in the mixed and filtered test signal y(t) Figure 8 shows the mixed test signal (1) before the filtering, for example, if the stored circuit is a first-stage low-pass Butterworth chopper with carrier frequency (the fundamental frequency of the phase-locked loop) Angle frequency, or if there is a cutoff frequency (angle The second stage low pass Butterworth filter in the carrier frequency range is set in the signal path to be tested. The spectrum 800 shows the test signal ψ(1) asymmetrically attenuated via the mixed test signal φ(1). The frequency portion 802 of the double frequency range of the phase loop fundamental frequency includes a similar form as the ideal signal path. However, the non-pair 13 201027100 weighed attenuation also obtains the low frequency frequency portion 8 〇 4. After the chop hybrid type test number, The signal processing device or detector can evaluate the quality of the low frequency solution part of the stool signal ratio.

Thus, for example, the signal path to be tested or the cheek of the circuit under test (eg, RFIC): The age or flatness of the response can be measured. For this = purpose 'tested age-old control circuit is simply phase change ^ ( (phase modulated carrier) money, the general signal path or the test to be just a test of the county mixed test (four), The mixed _ test money passes through the low pass chopping wave, and the activity of the mixed and pulsed test signal is used as the measured value of the quality of the signal path to be tested or the circuit to be tested. Since the phase-locked loop that has been modulated is used as an excitation, there is no external excitation = 2 such as a function generator. The filtered signal mirror y丨 of the filter output signal contains only asymmetrical or non-ideal glitch (except for the DC component) and is therefore much easier to measure than a small, non-ideal, large signal. In addition, the dynamics are significantly improved' and do not need to be digitized because pure power detection or maximum value detection is sufficient.

For example, 'pair-time integrated power detector (diode), pair-given time abS(.) (integral of the absolute value of the quantity), or maximum fixed detection (maximum value detection) may detect Activity of (mixed and filtered signals). The use of digital to analog converters (ADCs) with lower requirements, such as resolution requirements, is also expected to be (four) miscellaneous, the original time in the silk and/or the rate is reduced because the details of the spectrum are not needed as long as they do not contain any The unambiguity of the solution phase, such as the amplitude dependence gain 14 201027100, does not expose itself to the filtered signal y(t) in this example. Figure 9 shows a block diagram of a test system 900 for testing signal paths with a means for compensating for time delays or adjusting delays through the circuit under test, in accordance with an embodiment of the present invention. If the signal path to be tested or the circuit under test 610 as part of the signal path contains a delay (for example, ideally ψ(〇=Φ(ί-τ)), the time delay can be compensated by delay modulation of the reference signal, reference Signal Φ '(1) = Φ(ί_τ) (eg <J>'(t)=cos((〇t+cp,(t)), also referred to as the second carrier. Here test system 900 has the same as Figure 6 Similar equipment of the test system shown. However, the mixer 620 is supplied with a reference signal of the second phase-locked loop 93, instead of the original test signal from the phase-locked loop 13 of the sigma generator 11 The second modulator 920, which is coupled to the second phase locked loop 930, allows phase modulation of the reference signal. If the delay is unknown 'the change is used to obtain the lowest activity of the mixed and filtered signal y(t) The modulation delay can obtain the desired result (delay value). Figure 10 shows a test system for testing the signal path for determining the nonlinearity of the signal path according to the embodiment of the present invention. Fig. Test system 1G_ is established according to the similar principle of test secret shown in Figure 6. In the ##路杈, the mixer is not set (so W=X(1))° at the end of the signal path' test signal is directly filtered by the low-pass filter 630, and the detector of the feed device is provided _. Ground, the nth figure 1 is passed through a letter with non-linearity: the non-talking spectrum. Here, for example, the nonlinearity is the amplitude-dependent gain, and the linearity mainly does not contain your frequency dependence. Displaying the frequency portion 1120 of the original signal in the range of the fundamental frequency 720 of the phase-locked loop of the test signal generator of the test signal generator, the frequency portion 1130 of the baseband frequency 730 doubled by the nonlinearity caused by the nonlinearity, and also by The low frequency portion 1110 caused by the nonlinearity is apparently known by the characteristic 71 of the low pass filter, and is in the frequency portion of the range of the baseband 720 of the phase locked loop and the doubling range of the fundamental frequency 730 of the phase locked loop. Filter out. Then the signal processing device or detector detects and evaluates the low frequency frequency portion 1110, thus detecting the nonlinearity of the signal path. It should be noted here that the odd-order nonlinearity is typically not shown in the low frequency. The low-frequency alternating modulation product is generated between the signal path or the even-order nonlinearity of the circuit to be tested and the tonality (frequency) of the test signal, and is also indicated as the modulated excitation waveform φ(ί). The filtered test signal is visible. Figure 11 shows an example of the spectrum of the test signal X(t) before being filtered by the low-pass filter used for the signal path with even nonlinearity or the circuit under test. The test signal (carrier) is excited by the signal path or the circuit to be tested, and then passed through the signal path or the circuit to be tested, and then the low-pass wave-reducing signal is used, and the filter output activity is used (filtered test signal is used). Active), such a signal path or a non-linearity measurement of the circuit under test can be used, for example, as a measure of the quality of the signal path or circuit under test. For the ideal signal path or ideal circuit to be tested, the filtered test signal y(1) is zero. Figure 12 shows an example of a known LINC transmitter 12 〇〇 (linc = linear amplification using nonlinear components). As shown in the block diagram, the LINC transmitter 12A includes two phase-modulated phase-locked loops 1210, 1220 coupled to a combiner 1230. The combiner 1230 is configured to overlap signals from both of the phase locked loops 121A, 1220 and provide the 201027100 overlapped signal to a power amplifier 1250 through the programmable gain amplifier 124A. The two phase-modulated phase-locked loops 121A, 1220' of the transmitter 1200 can cause phase-modulated signals in the common mode phase modulation (through the combiner 1230). In the differential phase modulation, amplitude modulation can be generated. Since there is already a phase-modulated phase-locked loop, in a system including a transmitter, a test system for testing a signal path is easily implemented. Figure 13 shows an embodiment of the present invention, A block diagram of a test system 1300 for testing a signal path based on a LINC-based RI® IC. The R FIC is structured similarly to the principle illustrated in Figure 2, wherein the transmitter portion does not include an in-phase/quadrature phase architecture. Instead, it contains the LINC architecture, as shown in Figure 12. One of the two phase-modulated phase-locked loops 13 of the LINC transmitter is used to generate the test signal. To test from the second phase-locked loop 122 to The signal path of the combiner 1230, the second phase locked loop 1220 can be used to generate a test signal. The output device (Τχ) of the transmitter portion is coupled to the input device (RX) of the receiver portion, whereby the signal path is from the transmitter to the transmitter The receiver, for example, thereby allows a loopback test of the LINC based RFIC. As shown in Fig. 2, the receiver portion of the test system 1300 is also implemented in the in-phase/father-phase architecture, but instead of the one shown in Figure 2 Phase lock back The phase-locked loop 132' is configured to provide a reference signal φ'(1) using the tunable transformer 1310 for phase modulation. Thus, the signal path to be tested is derived from the test signal generator 11. The phase-modulated phase-locked loop 130 extends through a combiner 123, a programmable gain amplifier 1240, a power amplifier 1250, a low noise amplifier 266, and a pre-programmed gain amplifier 264 a phase/quadrature phase mixer 620, and extending therefrom to a low pass filter 630, wherein a low pass filter, wave 630 is disposed in the same phase branch 252' and another low pass filter 63 is provided Quadrature phase branch 254. The two low pass filters 630 are each coupled to a detector 640 that is part of the signal processing device 140. The phase modulated phase locked loop 1320 and associated modulator 131 The configuration is configured to provide a reference signal, which also forms part of the signal processing device 14. Through the phase shifting unit 262, the phase-modulated phase-locked loop 132 is coupled to the in-phase/quadrature phase mixer 620, thus providing The test signal is applied to the in-phase/quadrature phase bit mixer 620. Additionally or alternatively, the (signal processing device 14) phase shifting unit 262 can be directly connected to the phase-locked loop of the test signal, for example, to provide the county test. The signal is fed to the in-phase/quadrature phase mixer 62〇. - For example, the apparatus described in Figure 13 can implement a test system for detecting the frequency dependence asymmetry in the signal path, as shown in Fig. 6. Show. Replace the original 3 丨 test [No. 'If the reference signal contains the same phase modulation, then #

The reference L number can also be used to combine test signals through the signal path. The phase delay between the Q and the reference signal can also be compensated by the method described in Figure 9. If the phase-modulated reference signal existing in the _bit/quadrature phase mixer 62G or the original test signal is replaced by a constant signal (but not equal to zero), then (4) will be compared with the system shown in the figure (1). Corresponding, and can be used to detect nonlinearities in the signal path. The phase-locked loop of the receiver, which is modulated by the phase-locked loop 1320, is deployed as a stimulus for the transmission of the modulated pLL. Such as 18 201027100 This does not need to be responsible for the function generator. As explained earlier, there is no need for an expensive analyzer for signal processing because only the low frequency portion of the test signal can be tested. For example, instead of a LINC based transmitter, a transmitter with polarity modulation can be used. Figure 14 shows a block diagram of a polar modulation transmitter 1400, wherein the transmitter 1400 includes a phase modulated phase locked loop 1410, a programmable gain amplifier 1420, and a tunable one power amplifier 1430. The amplitude and phase are independently modulated. Suitably, Fig. 15 shows a block diagram of a test system for testing a signal path of one of the polarity-based RFICs in accordance with an embodiment of the present invention. The equipment and operating modes of the test system 15 are corresponding to the equipment and mode of operation of the test system described in the figures. The only difference is the use of different transmitter architectures. However, the phase-modulated phase-locked loop 130 of the already existing transmitter module is used to generate a test signal. The additional cost of the test system used to implement the test signal path is kept extremely low. Again, the modulated PLL of the transmitter is used as an excitation to check and balance. Another possibility is to implement a transmitter in an in-phase/quadrature phase architecture. For purposes of this project, Figure 16 shows a block diagram of a test system 1600 for testing a signal path based on an in-phase/quadrature phase RFIC (I/Q-based RFIC), in accordance with an embodiment of the present invention. The equipment and operating modes of the test system 1600 are similar to those shown and described in Figures U and 15. The difference is in the use of in-phase/quadrature phase transmission benefits as already explained in Figure 2. The phase-locked loop of the existing transmitter module is here replaced by a phase-modulated phase-locked loop 130, or extended to provide a phase-modulated test signal of 201027100. The signal path to be tested in turn extends from the phase locked loop 130 of the test signal generator 110 to the signal processing device 140, wherein the signal path portion includes an in-phase branch and a quadrature phase branch. The input A 1610 of the in-phase branch 212 and the input B 1620 of the quadrature phase branch 214 are supplied with a constant signal, such as a logical OR or a logic 1 for testing the signal path. It is easy to maintain these levels without any additional cost, as the signal is available in the circuit. By appropriately selecting the input terminal A 1610 of the in-phase branch 212 and the input terminal 16 1620 of the quadrature phase branch 214 (for example), the in-phase branch or the quadrature phase branch 214 of the transmitting module or a combination of two branches can be tested. . For example, by applying logic 1 to input A 1610 of in-phase branch 212 and applying logic 〇 to input B 1620 of quadrature phase branch 214, in-phase branch 212 becomes active. In addition, the in-phase branch 252 of the receiver can be tested by evaluating the detector 642 coupled to the output of the low pass ferrite 630 of the in-phase branch 252 of the receiver module. The quadrature phase branch 254 of the receiver can be tested by evaluating the detector 640 coupled to the output of the low pass filter 63A of the quadrature phase branch 254. In this way, according to the principle of Fig. 6 and the 〇 diagram, the system for detecting the frequency dependence __ face degree can be realized. The phase-modulated phase-locked loop 13 is used as an excitation to generate a test signal. The same phase/quadrature phase mixer _ down-frequency is used to compensate for the frequency dependence. Symmetry, the mix. The 62G is supplied to receive the phase-modulated signal of the phase-modulated phase-locked loop I% of n (such as the system (4) of Figure 6), and the second reference of the reference signal of the 20th 201027100. It is a non-zero constant), for example to detect non-linearity' whereby the test signal is not down-converted (this corresponds to a test system such as Figure 10). The baseband input signal (TX BB input) of the transmitter and the signal at the input terminal a 1610 and the signal at the input terminal B 1620 may contain any value. But for example, simply use logic 1 and / or logic. In-phase branch 212 or quadrature phase branch 214 can also be selected in this manner. Other fixed numerical results result in the test signal φ at a different phase < Kt). For example, an ADPLL (full digital phase-locked loop) with digital phase control can be used for modulation. The analog phase-locked loop can also function but it is more difficult to achieve (the phase-locked loop of the test signal generator 110) the transmitter (τχ) is equal to the receiver of the signal-sense unit 14 (the phase-locked loop 132 of the signal processing device 14) - Modulation. As already mentioned, a modulated (analog) phase-locked loop can also be used and routed through to two purposes (on the one hand, the test signal is coupled to the signal path, and on the other hand the test signal is provided). The mixer 620 serves as a reference signal). For this project, for example, a modified phase-locked loop can also be used. For example, an NCO (Numerical Controlled Invigorator) can be used as a sinusoidal phase modulation source (modulator). Other waveforms are also useful, but NC〇 is easier. In addition, the roles played by the in-phase branch and the quadrature phase branch can be exchanged to verify both the in-phase and quadrature phase transmit and receive paths. The symmetry of the phase modulation path of the transmitter section (ΤΧ) and the receiver section (RX) can be tested. It is possible to verify that the signal path has not died by modulating the phase difference between the sources (the phase-locked loops with different phases). For example, offsets rely on the same modulation. For example, a non-ideal 21 201027100 case may occur in an in-phase/quadrature-based circuit, such as described in FIG. Such non-ideal conditions such as phase mismatch (phase difference) or gain mismatch (gain difference) between the in-phase branch and the quadrature phase branch can be developed by a small difference between the two branches, due to the small difference resulting in two branches The symmetry was destroyed. In conjunction with the test system shown in the example of Figure 16, FIG. 17 shows a schematic model 1700 based on in-phase/quadrature phase RFIC with a loopback configuration, in accordance with an embodiment of the present invention. Model 1700 contains only those components that are important for measuring in-phase/quadrature phase mismatch. Other components are ignored or added to the constant parameters. For example, the low pass filter of the transmitting portion is not taken into consideration because the input signal A 1610 and the input signal B 1620 in this example are fixed (time constant) during the signal path test. Further, two 0 degree/90 degree phase shifting units respectively disposed between the phase locked loop and the inphase/quadrature phase mixers 218, 620 are considered, and the consideration is based on the use of the in-phase branches 212, 252. Sine function (eg a(t)=sin(Qt+cp(tT)), u(t)=sin(Qt+cp(tT)), where φ([-τ) and φ〇Τ) respectively represent the lock The phase modulation signal of the phase loop) and the cosine function for the quadrature phase branches 214, 254 (eg b(1)=cos(Qt+(p(tT), v(t)=cos(Qt+cp(tT))) Where φ 〇 τ) and φ 〇Τ) represent the phase modulation signal of the phase locked loop). In Fig. 17, the test signal in the in-phase branch 212 of the transmitting portion in front of the in-phase/quadrature phase mixer 218 of the transmitting portion is denoted by a(t), and the in-phase/quadrature phase mixer in the transmitting portion The test signal in the quadrature phase branch 214 of the transmit portion in front of 218 is labeled b(t), and the test signal at the output of the transmit portion behind the combiner 230 is labeled s(t), which is in phase with the receiver portion at 201027100. The test signal preceding the input of the quadrature phase mixer 620 at the receiver portion is labeled 1·(1), and the reference signal of the in-phase branch 252 of the receiver portion is in front of the in-phase/quadrature phase mixer 620 of the receiver portion. Labeled as u(t), the reference signal of the quadrature phase branch in front of the receiver/phase quadrature phase mixer 620 at the receiver portion is not v(t), in phase with the receiver portion / The test signal of the in-phase branch 252 of the quadrature phase mixer behind the receiver portion is labeled φ X(1), and the in-phase/quadrature phase mixer 620 of the receiver portion is followed by the quadrature phase branch 254 of the receiver portion. Test signal denoted as y (t). Gain imbalance 1770, 1780 (gain mismatch) can also be inserted into either of the other mixers (input or output). In other words, the _ ' gain difference of the transmit portion can also be inserted in front of or behind the in-phase/quadrature phase mixer 218 of the in-phase/quadrature phase mixer 218 of the quadrature phase branch 214 or the in-phase branch 212. Similarly, the gain difference of the receiver portion can be inserted into the in-phase/quadrature phase mixer 剞 620 、 in the in-phase branch 252 of the receiver portion, behind the mixer 620, or the mixer 620 and the signal processing device 140. The phase locked loop is between 1320. The phase imbalance is modeled over time delays because the modulation is also delayed. Between either of the two mixers 218, or between the mixer 218 and the phase locked loop 130 of the test signal generator 110, the transmitter phase imbalance 1750 is also modeled. The receiver phase imbalance 1760 can also be modeled prior to either of the two mixers 620, or between the s 620 and the phase locked loop 1320 of the signal processing device 140. The receiver's low-pass filter 630 (L(co), L) is modeled as ideal. 23 201027100 with angular frequency ω/2, perfect for passing the fundamental frequency and suppressing the upper image. The signal path gain and the loopback attenuation are stacked into the gain parameter G 1702. The signal path and the loopback delay are stacked in parameter γ 1704. In contrast to the test system shown in Figure 16, the signal processing device 14A includes an additional combiner 1710 for the schematic model 1700. The combiner 171 is configured to overlap the signal of the signal X(1) of one of the output terminals 1720 of the low pass filter 630 of the in-phase branch 252 of the receiver section and the output terminal 1730 of the low pass filter 63 of the quadrature phase branch 254. Y(t), and to provide an overlap signal B to the output 1740. 10 Such a measure of the transmitter (TX) skew δ 1750 (phase difference), the transmitter (TX) gain mismatch g 1770, the receiver (rx) skew ε 176 〇 (phase. The gain of the receiver (RX) does not match h 1780, where the loopback delay γ 1704 and the loopback gain G 1702 are unknown. Here, the controllable input is the phase τ (in time) of the transmitter (precise), which is established by the phase-locked loop 13〇(〇sc) of the test signal generator 11,, the receiver (accurate) The phase T (in units of time) is established by the phase locked loop 丨320 (0sc) of the signal processing device 140, and the signal A at the input terminal 1610 of the same phase reference branch 212 of the transmitter is positive to the transmitter. The signal B at the input 162 of the phase branch 214 (e.g., the most accurate logic level and logic 1 level can be generated). Thus, the phase value can be converted into a corresponding time value. The level or activity of x, Y', Z' (at the outputs 1720, 1730 of the two low pass filters 630 and the output 1740 of the combiner 1710) is obtained as available evaluation information (eg, Accurately measure "inactive"). Four mismatched components (δ, g, ε) can be calculated and/or obtained via 24 201027100 available information (X, Υ, Z) collected under various combinations of available input signals (τ, T, a, b). , h). The result of each combination results in an equation that does not match the component. All mismatched components can be determined by using a sufficient amount of each combination. Several embodiments in accordance with the present invention are directed to a method of measuring the phase difference between two hybrid phase-locked loops via a control phase. For this project, Figure 18 shows a schematic model illustration of a test system for determining the phase difference between two phase-modulated phase-locked loops. The model illustration 1800 shows a first phase modulated phase locked loop 1810 and a second phase modulated phase locked loop 1820 whose output signals are mixed by a mixer 1830. The mixed signal x(t) is filtered by a low pass filter 1840, and the filtered signal X(1) is provided at the output of the low pass filter 1840. For this project, first, the signal X(1) at the output of the low-pass filter 1840 must be calculated as the skew a 1850 and the phase φ(1) (of the first phase-locked loop 1810) and the phase ψ(1) of the second phase-locked loop 1820. The function. α(ί)=8ΐη(Ωί+φ(ί-τ)) r(t)=a(ta) r(t)=sin(Qt~n ΑΓ+φ(ί-α-τ)) u(t) =sin(Qt+Y(t)) x(t)=r(t).u(t)

GG = yC〇s(y(i)-^?(iar) + Qa)+^· cos(2QQ + ...) X(t) = ^2 cos(^(0-φ{ί-α-τ) + Ωα) Using this result, by controlling its phase ^t) and ψ(ί), the skew between the two phase-modulated phase-locked loops can be measured in two different ways (X (phase also 25 201027100 difference). Measuring the skew between carriers (signals) may involve using a static phase adjustment. φ(〇=Ωτ, ψ(ί)=ΩΤ The filtered output signal X is a DC voltage signal. If Τ and / or τ are adjusted If the filtered output signal X reaches the maximum value, the phase difference will be obtained (X 1850. ex = Τ - τ. In addition, the filtered output signal X can also be adjusted to the minimum value, or adjusted to χ = ο. Another item of skewing of the transition may involve the use of dynamic phase adjustment. ψ(ί)=φ(〇X (〇= y cos(^i) ~φ{ΐ-α-τ) + αα) The output 仏 is 动态 is the dynamic signal. The pair becomes static. So skewed (X 1850 can be determined by adjusting τ, where τ is adjusted so that the activity of the wave output 彳s X reaches the minimum value (or zero). In addition, τ can also be adjusted for The maximum activity of the signal X. Here, for example, the fact that the ADPLL allows for extremely accurate phase adjustment and extremely accurate phase modulation via digital control is possible. However, the method can also be applied to analog phase-locked loops. The configuration also appears in the test system model 1700' shown in Fig. 17, wherein the phase-modulated phase-locked loop mG system corresponds to the phase-locked loop 130 of the test signal generator 11〇, and the second phase is modulated. The phase lock loop 1820 corresponds to the phase lock (four) 132〇 of the signal processing device 14〇, and the hybrid 201027100 combiner 1830 corresponds to the in-phase/quadrature phase mixer 620 of the receiver portion, and the low pass filter 1840. Corresponding to the low pass filter 630 of the in-phase branch 252 and the quadrature phase branch 254. Thus, the loopback delay γ 1704 can be determined by the method. According to several embodiments of the present invention, a measurement is based on in-phase/positive A method of phase imbalance in a phased RFIC, such as shown schematically in Figure 17. Emitter (ΤΧ) and receiver of the in-phase/quadrature phase mixer 630 ▲ at the receiver portion (RX) (RX) skew between phase modulation (test signal and reference signal) and tied to signal X (output 1720 of low pass filter 630 of phase branch 252) and low pass filtering of quadrature phase branch 254 The output Y of the 630 'output 1730' depends on the transmitter (TX) and the receiver (RX).

Phase imbalance, loopback delay, input signal A 1610 of in-phase branch 212, and input signal B 1620 of quadrature phase branch 214, wherein input of input signal A 1610 and quadrature phase branch 214 of in-phase branch 212 can be controlled Signal B 1620 and transmitter (TX) modulation (test signal) are independent of the combination of the same phase division φ branch 212 or the quadrature phase branch 214 or the two branches. For the set values of the input signals A 1610 and B 1620, the measurement of the modulation skew at the output terminals 1720, 1730 (X and Y) of the low pass filter 630 allows the operation of the transmitter (TX) and the receiver (RX). Phase imbalance (the phase difference between the test signal and the reference signal in different branches). For example, the emitter in-phase branch 212 (A=l, B=0) and the transmitter measured at the output of the same low-pass filter 630 (on the same branch of the receiver, such as the output signal X 1720). The phase shift imbalance between the quadrature phase branches 214 (A = 0, B = 1) shows the phase imbalance of the transmitter 175 〇 27 201027100 (the phase between the in-phase branch 212 and the quadrature phase branch 214 of the transmitter portion is not Balance 1750). In a similar manner, the phase modulation of any transmitter can be displayed by comparing the modulation skew between the in-phase branch 252 (output signal X 1720) of the receiver and the quadrature phase branch 254 (output signal γ 1730) of the receiver. The phase difference of receiving benefits is 1760. An additional embodiment in accordance with the present invention is directed to a method for measuring gain imbalance. For example, as illustrated schematically in the figure, such an approach can be used for in-phase/quadrature phase based RFICs. The carrier phase of the receiver (the test signal arriving at the receiver) depends on the weight of the input signal a 1620 of the in-phase branch 212 of the transmitter (TX), and the input signal b 620 of the quadrature phase branch 214 of the transmitter (TX). The weight, the gain imbalance of the quadrature phase branch 214 of the transmitter (TX) g 1770, and the phase imbalance of the transmitter (TX) δ 1750. The input signal A 1610 of the in-phase branch 212 and the input signal B 1620 of the quadrature phase branch 214 are set to a value, and the output signal X 1720 of the same phase branch of the receiver section or the output signal of the quadrature phase branch γ 1730 The measurement of the carrier skew (test signal skew) allows a gain imbalance of the transmitter (TX) g 1770 for the known phase imbalance δ 1750 of the transmitter (τχ). For example, the carrier phase difference between the state having the input signals A = 1 and B = 0 and the state having the input signals A = 1 and B = 1 is equal to 45 degrees. The deviation depends on the phase of the transmitter (TX) and on the gain imbalance of the transmitter (τχ) g 1770. The gain imbalance of the transmitter (ΤΧ) g Π 70 can be calculated for the known phase imbalance δ 1750 of the transmitter (τχ) 201027100. The carrier skew measurement of the in-phase branch 252 (RX 1} of the receiver and the quadrature phase branch 254 (RX Q) of the receiver is ideally (10) degrees, and the deviation is caused by the phase and gain imbalance of the receiver. The carrier skew of any input carrier phase (test signal phase) measured at the receiver's in-phase branch 252 and quadrature phase branch 254 output signal 172〇' 173〇 allows for the phase of the known receiver (RX) Unbalanced ε 1760 arithmetic receiver (rx) gain imbalance h 178 〇 For example, 45 degree carrier skew causes the signal Z=XY=〇 of the combiner output 1740. Adjust the receiver ( The phase of rx) (phase of the reference signal) to the output signal Ζ = 0, allowing the known phase imbalance ε 1760 of the receiver (rx) to operate the gain imbalance of the receiver (RX) h 1780. According to the invention Several embodiments relate to a deductive rule or method for determining phase imbalance and gain imbalance, comprising: - determining a loopback delay; - determining a phase imbalance of a transmitter portion (TX); - determining a receiver portion (RX) Unbalanced phase; - calculating the gain imbalance of the transmitter portion (TX); - calculating the gain imbalance of the receiver portion (RX). Several embodiments according to the invention relate to an RFIC for determining in-phase/quadrature phase based The method of returning the delay γ 1704 is shown, for example, in Figure 17. Here, in the first step, the input signal is set (for example, A=1, Β=〇, non-constant (p(t), \|/(t = (p(t), Τ = 0) 0 29 201027100 Then τ is adjusted until the output signal ?^ + τ = τι of the in-phase branch 252 of the receiver portion is constant. Then γ = τι. Mathematically, it can be expressed as follows: s(t)=sin(Qt+9(tx)) r(t)=G · s(t~Y) r(t)= G · sin(Qt-QY+cp(ty —τ)) u(t)=sin(Qt+9(t)) x(t)=r(t) · u(t)

GQ = y COs{(p{t) ~(p{tYz) + ay) + ~ c〇s(2Q t-¥...) x (0 = -jC〇s(<p(t) ~φ (ί-γ-τ) + Ωγ) X(t)=const=>Ti=-y An additional embodiment according to the present invention relates to a phase imbalance in an RFC based on in-phase/quadrature phase The method of δ 1750, such as shown schematically in Figure 17. Here, first, the input signal is set (for example, A = 0, B = 1, cp (t), τ = - γ,

ψ(〇=φ(ί)). Subsequently, the phase of the phase locked loop I320 of the signal processing device 140 is adjusted until the output signal X of the output 1720 of the in-phase branch 252 of the receiver portion is constant for Τ = Τ 2 . Then δ=Τ2 ° can be expressed mathematically as follows: s(t)=g cos(Qt-Q5+9(t-S+Y)) r(t)=Gs(ty) r(t)=Ggsin( Qt-Q5-QY+ 如卜δ)) 3〇201027100 u(t)=sin(Qt+ φ(ί-Τ)) x(t)=r(t) · u(t)

GG =cos(^?(i— 2^)—(pit — S) + Ω,ό + Ω^1) + cos(20 ? + ...) X(t) = cos(ff>(t — T ) — φ( ί — S) -\r Ωό + Ω^)

X(t)=const=>T2=S According to several embodiments of the present invention, a method for determining

A method of phase imbalance ε 1760 in the phase/orthogonal phase RFIC, such as shown schematically in Figure 17. Here, first, an input signal is set (for example, A=1, Β=0, a very cp(t), τ=-γ, ψ(〇=φ(〇). Subsequently, the phase locked loop 1320 of the signal processing device 140 The phase is adjusted until the output signal Υ = Τ 3 of the output terminal 1730 of the quadrature phase branch 254 of the receiver portion is constant. Then ε = - Τ 3.

Mathematically, the formula can be expressed as follows: r(t)=G· sin(Qt-Qy+9(t)) v(t)=h cos(Qt+9(tT)) y(t)=r(t)- Hv(t-8) = r(t) .h.cos(Dt—Ωε+φ(ί_Τ_ε)) = sin(—Ω γ + ))+ Ωε — Γ—Γ — £)) +sin(2i2 ί + ...) Y (t) — 2 sin(^?(f) — φ(ί -7^-^) + — Ω 31 201027100 Y(t)=const=^T3=-£ According to an additional embodiment of the present invention A method for determining gain imbalance g 1770 in an RHC based on in-phase/quadrature phase, such as shown schematically in Figure 17. Here, first, an input signal is set (eg, Α=: ι, Β=1) , φ(1)=Ωγ, ψ(1)=ψ, a certain system corresponds to a signal that does not contain (phase) modulation).

Subsequently, the output signal X of the output 1720 of the in-phase branch 252 of the receiver portion is adjusted to include the maximum value of Ψ = Ψ 4. The gain imbalance g 1770 can then be calculated. For example, here, the phase p of the test signal r(t) first present in the in-phase/quadrature phase mixer 620 is computed as a function of the gain imbalance g 1770, mathematically expressed as: s(t)= Sin(Qt+Qy)+g cos(Qt-Q5+Qy) r(t)=Gs(ty) =G sin(Qt)+Gg cos(Qt-Q5)

=G sin(Qt)+Gg cos(Q6)cos(Qt)+Gg sin(Q6)sin(Qt) = [G+Gg sin(Q6)]sin(Qt)+Gg cos(Q6)cos(Qt) =R sin(Qt+p)

P = arctan g cos (QS) 1 + gsin (Q^) Then ' can be determined Ψ 4, where the output signal X at the output 172 of the in-phase branch 252 of the receiver portion contains the maximum value. Mathematically, it can be formulated as follows: r(t)=R sin(Qt+p) u(t)=sin(iit+y) 32 201027100 x(t)=r(t)-u(t) =R sin(Qt +p)sin(Qt+\)/)

R R =-J cos(p -ψ)-^· cos(2Q i + · ·)

R X(〇 = ycos(p-^) ψ4 = arg max X = p ψ Then the gain imbalance of the transmitter g 1770 can be calculated by ψ4, which can be mathematically formulated as follows:

Tan ψ4

Cos(Q5) + sin(Q6) g = cos(Q6) tan\|i4 1_ -sin(Q5)

Several embodiments in accordance with the present invention are directed to a method for determining gain imbalance h 1780 in an in-phase/quadrature-phase based RFIC, such as shown schematically in Figure 17. Here, first, an input signal is set (for example, A = 1, B = 0, φ (ί) = π / 4 + Ω γ, ψ (1) = ψ, which corresponds to a signal that is not (phase) modulated). Subsequently, the tether is adjusted until the output signal Z at the output 1740 of the combiner 1710 is zero = ψ 5 is zero. The gain imbalance h Π 80 can then be calculated. For this project, for example, firstly measured at the output 33 of the combiner 171〇, the output signal z of 201027100 1740 is a function of ’, which can be mathematically formulated as follows: s(t) = sini Qt + ^ +

r(t) = G · s(t - γ) = G sin[Qt + | x(1)=r(t) · u(t) =G sin^Qt + sin(Qt + ψ) _G f π] G —2 Cos Ψ — ear j 一 δ (2Ω ί Η —)

^(0 = r(t) -h-v(t-E) 4 ψ-Ωε- =Gh siJ Ωί + ^ I cos(Qi - Ωε+ψ)

Gh

Gh . ZW = jC〇s ψ 旬 旬 誓 sin[\|f - Ωε - * For ψ = ψ 5, Z is equal to zero: 〇 = seek. . Such as 5 -1) _ 苎 s+5 Ωε — !,

So again based on the gain imbalance of the Ψ5 arithmetic receiver h 1780 mathematically expressed as follows:

Sin^5-n£-|J In accordance with several embodiments of the present invention, the gain imbalance of the measurement transmitter (τχ) depends on the input signal Α and the input signal 等于 is equal! . (Input signal A and input money B) can be improved by applying (4) signal to input signal VIII and ^ 34 201027100 into signal B. For this item, Figure 19 shows a circuit diagram of a device for providing equal signal levels. Here, the level of logic or logic can be applied to the output signal a and/or the output signal B of the device by four switches 1910. Several embodiments in accordance with the present invention are directed to a method for testing signal paths, wherein the method is also applicable to RFIc with analog fundamental frequencies. Several additional embodiments in accordance with the present invention are directed to a method for testing a signal path in which neither an external waveform generator nor an external waveform analyzer is required. An additional embodiment in accordance with the present invention is directed to a test system for testing a signal path and a method for testing a signal path, wherein measurement accuracy is not limited to digital to analog converters (DACs) or analog to digital converters on a wafer. (ADC) inaccuracy is limited to the inaccuracy of the external waveform generator or external waveform analyzer. Determining when the value is zero/minimum/maximum or determining the minimum activity/maximum activity, for example, does not require linearity or (high) accuracy, but requires only a single tone. Only phase adjustments must be as linear and precise as possible, which is especially true for ADPLL. Several embodiments in accordance with the present invention relate to a method for testing a signal path in which the in-phase/quadrature phase imbalance can be measured by the phase-locked loop phase of the transmitter (of the test signal generator) and/or Or the phase change of the phase-locked loop of the receiver (of the signal processing device) is combined with a plurality of fundamental frequency input signal combinations A and B. To achieve this, for example, measurable output (X, Y, Z), the static phase can be adjusted to obtain the minimum or maximum output signal χ, υ, ζ, or the output k is said to be specific to zero; or phase modulation The delay 35 201027100 can be adjusted to obtain the minimum or maximum activity of the output X, Υ, Z. Several embodiments in accordance with the present invention relate to a method in which other combinations of values of input signals A, B are used in place of 0 and 1. For example, dynamic input signals A, B can be used instead of static signals. An additional embodiment in accordance with the present invention is directed to a method wherein the input signal is adjusted to obtain maximum activity of the output signals X, Y, Z rather than minimum activity. Adjust the output signal X, Y, Z to the minimum, maximum or equal to zero may be equal. For example, the output signals X, Y, Z can be measured instead of being adjusted to a minimum, maximum or zero, which is faster, but requires an accuracy measurement. In addition, the static transmitter phase adjustment is equal to the static receiver phase adjustment. To calculate the phase difference or phase imbalance and gain imbalance, use the following trigonometric formula as the basis: sin x sin y (cos(x - y)- cos(x + y)) sin x · cos y = ^ (sin(; c - y)- sin(x + y)) sinx-sin, = 2cos^sin^ cos(x - y) = cos x cos y + sin x sin ys + arctan — a

a sin x-\-b cos x = Figure 20 shows a flow chart of a method 2000 for testing a signal path in accordance with an embodiment of the present invention. First, a test signal generator is generated by the test signal generator, wherein the test signal generator includes a modulator and a phase locked loop. The phase locked loop of the test signal generator is configured to provide a test signal and couple the test signal to the signal path, wherein the test signal generator is configured to allow the phase of the test signal 36 201027100 Modulation. Subsequently, the test signal is coupled to the 2020 in-signal path, and the 2030 test signal is received by the signal processing device after passing through the signal path to be tested. Here, the signal processing device is configured to receive and process a test signal, wherein the signal path to be tested is extended by the phase locked loop of the test signal generator to the signal processing device. Subsequently, the test signal received by the signal processing device 2040 is evaluated, φ thus performing a comparison of the signal paths. Several embodiments in accordance with the present invention are directed to a method for testing a signal path in which a low pass filter is disposed. The low pass filter includes a cutoff 'frequency that is less than the fundamental frequency of the phase locked loop of the test signal generator. Thus, only the low frequency portion of the test signal reaches the signal processing device. For example, the non-linearity of the signal path can be detected via evaluation of the filtered test signal'. An additional embodiment in accordance with the present invention is directed to a φ method for testing a signal path, wherein the signal path includes a mixer and a low pass filter. The kiln is disposed in the signal processing direction of the signal path ' upstream of the low pass filter and configured to mix the test signal and the reference signal propagating along the signal path, and the mixed test signal is provided at the output. The low pass filter in turn contains a cutoff frequency that is less than the fundamental frequency of the phase locked loop of the test signal generator. The mixer mixes the test signal and the reference signal that have propagated along the signal path, wherein the reference signal corresponds to the original test signal provided by the phase locked loop of the test signal generator. The hybrid test signal is then filtered by the 2010 2010100 low pass filter and supplied to the signal processing device. By evaluating the mixed and filtered test signals, for example, the frequency dependence asymmetry of the detectable signal path. A number of embodiments in accordance with the present invention are directed to a method for testing a signal path, wherein the signal processing device includes a modulator and a phase locked loop, wherein the phase locked loop of the signal processing device is configured to provide a reference The signal, and the modulator of the signal processing device, are configured to allow phase modulation of the reference signal. In addition, the signal path packet-in-phase branch, a quadrature phase branch, a first in-phase/quadrature phase mixer, a second in-phase/quadrature phase mixer, a first low-pass filter, and A second low pass filter. Here, the first in-phase/quadrature phase mixer includes a same phase input terminal, a quadrature phase input terminal, an input terminal for a test signal, and an input terminal for a phase shift test signal, and is disposed on The signal path. The second in-phase/quadrature phase mixer includes an input of a reference signal and an input of a phase shift reference signal. The first low pass filter is disposed in the same phase branch and includes a cutoff frequency that is less than a fundamental frequency of the phase locked loop of the test signal generator. The second low pass filter is disposed in the quadrature phase branch and also includes a cutoff frequency that is less than a fundamental frequency of the phase locked loop of the test signal generator. The first in-phase/quadrature phase mixer is disposed on a signal path upstream of the second in-phase/quadrature phase mixer, and the first and second low-pass filters are disposed in the signal processing direction. Downstream of the phase/quadrature phase mixer. For testing the signal path, the signal is applied to the in-phase input and the quadrature-phase input of the first in-phase/quadrature phase 201027100-bit mixer, and the reference signal is applied to the second in-phase/quadrature phase mixer. And the test signal is coupled to the signal path. Subsequently, after passing the test path, the test signal is evaluated to perform the evaluation of the signal path. The evaluation of the signal path includes, for example, measurement of degree of non-ideality, non-linearity, frequency dependence asymmetry, phase difference, phase imbalance, gain difference, gain imbalance, phase mismatch, or gain mismatch. For example, such properties of the signal path may be from a test signal, a reference signal, a signal at the same phase input of the first in-phase/quadrature phase mixer, and/or a quadrature phase input of the first in-phase/quadrature phase mixer The difference in the signal of the end and the assessment. By phase modulation or phase change of the test signal and/or the reference signal, for example, a signal or a static signal may be generated at the output of the first low pass filter or the output of the second low pass filter or Minimum value by which the number of properties of the signal path such as degree of non-ideality, non-linearity, frequency dependence asymmetry, phase difference, phase imbalance, gain difference, gain imbalance, phase mismatch, or gain is not determined match. Here, for example, a static (time constant) signal is applied to the in-phase input and the quadrature phase input of the first in-phase/quadrature phase mixer. Several embodiments in accordance with the present invention relate to RFICs that include a transmitter portion and a receiver portion. However, the test system can be integrated into any circuit used to test the signal path. Several additional embodiments in accordance with the present invention are related to RFICs in which the receiver portion includes an in-phase branch and a quadrature phase branch, but is used to receive 39 201027100 p-knife - a non-inverting/quadrature phase architecture with a knife It is also possible. According to some implementations of the present invention, the test signal generator and the signal processing device are integrated on different devices that are lightly connected to each other through the signal path to be tested, for example, the domain path portion may also be a scale link or a light link. In accordance with several embodiments of the present invention, the signal is a device: a portion in which the device already includes a phase-locked loop that is modulated. This minimizes the extra effort required to implement the test system. Several embodiments in accordance with the present invention are applicable to charge sampling

The test system of the receiver' wherein the charge sampling receiver comprises a combination of a mixer and a low pass chopper. In the invention according to the present invention, the signal processing device includes a lock = loop 'where the base frequency system of the phase locked loop of the signal processing device corresponds to the fundamental frequency of the phase locked loop of the test signal generator, and has a tolerance soil 5%. If there is no phase modulation, the fundamental frequency of the phase-modulated phase-locked loop corresponds to the signal output frequency of the phase-locked loop.

In several embodiments in accordance with the invention, the signal path to be included includes an in-phase branch and a quadrature phase branch. In several additional embodiments in accordance with the invention, the signal waveform is, for example, a sinusoidal or cosine-based indicator signal such as a test signal or a reference signal. However, it is only intended as an example of a possible signal waveform. In the test system, the signal path between the phase locked loop of the test signal generator and the signal processing device is tested. However, as indicated by several embodiments, e.g., the right is known to be free of signal path representation of the circuit under test, the circuitry disposed on the signal path can also be tested. 40 201027100 In this case, the same component symbols are used for objects and functional units of the nature. Prime _ or similar work

In particular, it should be noted that depending on the situation, the system of the present invention can also be implemented on a bribe, and (4) has a disc or CD that can be electronically == signals, which can be communicated with a planable computer system: The corresponding method is thus executed. In general, the invention thus comprises a computer program product having a program code stored on a machine readable carrier for performing the invention when the computer program product runs on a computer. In other words, the present invention can be implemented as a computer program having a program code for executing the method when the computer program product is run on a computer. [Simple diagram of the diagram] Figure 1 is a block diagram of the test system used to test the signal path; Figure 2 is a block diagram of the RFIC; Figure 3 is a block diagram of a known test system for testing the signal path of the RFIC. Figure 4 is a block diagram with significant non-ideal isophase/quadrature phase rfk; Figure 5 is a block diagram of the modulated ADPLL (ADpLL: ^ digital phase-locked loop); Figure 6 is for A block diagram of the test system used to test the signal path for determining the frequency dependence asymmetry of the signal path; Figure 7 is the spectrum of the test signal after passing the ideal signal path; Figure 8 is the asymmetry through the frequency dependence. After the signal path, the spectrum of a test signal; 41 201027100 Figure 9 is a block diagram of a test system for testing the signal path with a device to compensate for the time delay; Figure 10 is a non-linearity for testing the signal path A block diagram of the test system used to test the signal path; Figure 11 is the spectrum of a test signal after passing through a signal path with non-linearity; Figure 12 is a LINC transmitter (LINC = using a nonlinear line) Block diagram of linear amplification of components; Figure 13 is a block diagram of a test system for testing signal paths based on LINC-based RFICs; Figure 14 is a block diagram of polar modulation transmitters; Figure 15 is a diagram of A block diagram of a polarity-based RFIC for testing a test signal path; Figure 16 is a block diagram of an in-phase/quadrature-based RFIC for testing a signal path; Figure 17 A schematic model of an in-phase/quadrature-phase RFIC with a loopback test configuration; Figure 18 is a schematic model illustration of a test system for determining the skew between two phase-modulated phase-locked paths; A circuit diagram of a device for providing equal signal levels; and a second diagram is a flow chart of a method for testing a signal path. [Main component symbol description] 100··.Test system 110...test signal generator 102...1⁄4 path 120...Mod, modulator 42 201027100

13 (X "PLL, phase-locked loop 140 ... signal processing device 200 - RFIC, RF integrated circuit 210.. transmitter 212 · · · phase branch 214 ... quadrature phase branch 216 ... LPF, low-pass filter 218.. Isophase/quadrature phase mixer 220.. PLL, phase-locked loop 222... phase shifting unit 224...PGA, programmable gain amplifier 226.. PA, power amplifier 230.. combiner 250. . Receiver 252.. In-phase branch 254.. Orthogonal phase branch 256... Low pass filter 258.. In-phase/quadrature phase mixer 260.. PLL, phase-locked loop 262...phase shift Unit 264...PGA, programmable gain amplifier 266..LNA, low noise amplifier 270.. split 300...known test system 310·.1, function generator 320...excitation 2, function generator 330. .Att, attenuator 340...Precision response analyzer 1 350...Precision response analyzer 2 400.. .RFIC, RF integrated circuit 410...Transmitter phase mismatch 420...Transmitter gain mismatch 430·.·Receiver Phase mismatch 440··· Receiver gain mismatch 500... ADPLL modulated, fully modulated digital phase-locked loop 502 ... REF, reference signal 510... phase accumulator 520...TDC, time to digital converter 530.. LPF, low pass filter 540...DCO, digitally controlled vibrator 542...output signal 600...test system 602· Additional path 610 - CUT, circuit under test 620 · Hybrid | §, in-phase / quadrature phase mixer 630.. LPF, low-pass filter 640 · · detector 700 ... spectrum 702 ... frequency part 704.. DC voltage section 43 201027100 710.. Low-pass filter characteristic 720.. Fundamental frequency 730.··Double fundamental frequency 800.. Spectrum 802... Frequency part 804... Low frequency part 900.. Test System 920...second modulator 930·.. second phase locked loop 1000...test system 1110...low frequency portion 1120··.frequency portion 1130···frequency portion 1200.. LINC transmitter 1210·.·phase Modulated phase-locked loop 1220... phase-modulated phase-locked loop 1230.. combiner 1240... programmable gain amplifier 1250... power amplifier 1300... test system 1310... modulator 1320... phase-modulated lock Phase loop 1400...polar modulation transmitter 141 (X "PLL, phase-locked loop 1420...PGA , can plan the gain amplifier 1430.. .PA 'power amplifier 1500... test system

1600.. Test system 1610·. Input signal A 1620... Input signal B 1700... Schematic model 1702 of RFIC based on in-phase/quadrature phase... Gain parameter, loopback gain g 1704... Gain parameter γ 1710.. combination 1720...output terminal 1730...output terminal 1740.··output terminal 1750.. transmit phase imbalance, skew 1760...receiver phase imbalance ε, skew 1770...gain difference, gain imbalance g 1780.. . Gain difference, gain imbalance h 1800···Method model 1810... First phase modulated phase lock _ 1820... 4th bit modulated phase-locked loop 1830.. Mixer, in-phase/orthogonal Phase Mixer 1840... Low Pass Ferrule 1850... Skew α, Phase Difference α 1900... Device Circuit Diagram 1910···Switch 2000.. . Method 2010-2040...Step

Claims (1)

201027100 VII. Patent application scope: 1. A test system for testing a signal path, comprising: a test signal generator comprising a modulator and a phase locked loop, wherein the phase lock of the test signal generator The loop is configured to provide a test signal and couple the test signal to the signal path to be tested, and the modulator of the test signal generator is coupled to the phase locked loop of the test signal generator, and is configured To allow phase modulation of the test signal; and a signal processing device configured to receive and process the test signal, wherein the signal path to be tested is extended by the lock-phase loop of the test signal generator to the signal processing Device. - 2. A test system for testing a signal path as claimed in claim 1 wherein the signal processing means is configured to perform an evaluation of the signal path based on the received test signal. 3. The test system for testing a signal path according to claim 1 or 2, wherein the signal path comprises a low pass filter, wherein the low pass filter comprises the test signal generator The cutoff frequency of the base frequency of the phase-locked loop is smaller. 4. The test system for testing a signal path according to any one of claims 1 to 3, wherein the signal path comprises a mixer, wherein the mixer is configured to use the test signal with a reference signal mixing. 5. A test system for testing a signal path as in claim 4, wherein the signal path comprises a phase branch and a quadrature phase branch and the mixer is a phase/quadrature phase mixer. 45 201027100 6. The test system for testing a signal path according to claim 4 or 5, wherein the signal processing device comprises a modulator and a phase locked loop, wherein the phase locked loop of the signal processing device A configuration is provided to provide a reference signal to an input of the mixer, and wherein the modulator of the signal processing device is configured to allow phase modulation of a phase locked loop of the signal processing device. 7. The test system for testing a signal path as claimed in claim 5 or 6, wherein the signal processing device comprises a combiner, wherein the combiner is configured to overlap one of the signals in the in-phase branch One of the orthogonal phase branches signals and outputs the overlapped signal. 8. The test system for testing a signal path according to any one of claims 5 to 7, wherein the signal path comprises a second in-phase/quadrature phase mixer disposed at the first The in-phase/quadrature phase mixer is in a signal path upstream of the signal processing direction, and includes a syn-phase input terminal and a quadrature-phase input terminal configured to mix the test signal and exist at the in-phase input terminal a signal, and configured to mix the test signal with a signal present at the quadrature phase input. 9. The test system for testing a signal path according to any one of claims 1 to 7, comprising an additional phase modulated phase-locked loop and a combiner, wherein the additional phase is modulated The phase locked loop is configured to provide an additional test signal, and wherein the combiner is disposed in the signal path and configured to overlap the test signal and the additional test signal and the output overlap signal. A test system for testing a signal path, as in any one of claims 1 to 7, wherein the signal path includes an amplifier configured to allow amplitude modulation of the test signal. A radio frequency integrated circuit (RFIC) having a test system according to any one of claims 1 to 10. 12. A method for testing a signal path, comprising: generating a test signal by a test signal generator, wherein the test signal generator includes a modulator and a phase locked loop, wherein the test signal generator The phase locked loop is configured to provide a test signal and couple the test signal to the signal path, and wherein the modulator of the test signal generator is configured to allow phase modulation of the test signal; The test signal is coupled to the signal path; the signal processing device is configured to receive the test signal, wherein the signal processing device is configured to receive and process the test signal, and wherein the signal path to be tested is determined by the test signal generator The phase locked loop extends to the signal processing device; the test signal received by the signal processing device is evaluated, and thus the evaluation of the signal path is performed. 13. The method for testing a signal path according to claim 12, wherein the test signal is filtered by a low pass filter disposed in the signal path, and the evaluation of the filtered test signal is performed. Used to evaluate the signal path. 14. The method for testing a signal path according to claim 13 wherein one of the signal paths disposed in the signal path upstream of the signal processing direction 47 201027100 mixes the test signal with a test signal a reference signal, wherein the mixed test signal is filtered by the low pass filter, and wherein the mixed and filtered test signal is evaluated by the signal processing device to perform the evaluation of the signal path. 15. The method for testing a signal path according to claim 12, wherein the signal processing device comprises a modulator and a phase locked loop, wherein the phase locked loop of the signal processing device is configured to provide a a reference signal, and wherein the modulator of the signal processing device is configured to allow phase modulation of the reference signal, and wherein the signal path to be tested comprises: a phase branch; a quadrature phase branch; a first in phase / Quadrature phase mixer with its package - the same phase input, a quadrature phase input, an input for the test signal and an input for the phase shift test signal; a second in phase / orthogonal a phase mixer comprising an input for one of the reference signals and an input for a phase shift reference signal; a first low pass filter disposed in the one of the in-phase branches and comprising less than the test signal generator a cutoff frequency of a fundamental frequency of the phase locked loop; and a second low pass filter disposed in the quadrature phase branch, and a base of the phase locked loop smaller than the test signal generator a cutoff frequency, wherein the first in-phase/quadrature phase mixer is disposed in a signal path upstream of the second in-phase/quadrature phase mixer, and the first low pass filter and the second low pass filter The device is disposed downstream of the second and 201027100 phase/quadrature phase mixers in the signal processing direction; the method further comprising: applying a first input signal to the first in-phase/quadrature phase mixer a phase input terminal; applying a second input signal to the quadrature phase input of the first in-phase/quadrature phase mixer; and applying the reference signal to the second in-phase/quadrature phase mixer. 16. A method for testing a signal path as in claim 15 wherein the first input signal at the in-phase input and the second input signal at the quadrature phase input are static signals. 17. The method for testing a signal path according to claim 15 or 16, wherein the test signal, the reference signal, and the first phase input of the first in-phase/quadraphase phase mixer are first The combination of the input signal, the change in the second input signal at the non-inverting input of the first in-phase/quadrature phase mixer, or the change in the signals is used to distinguish and evaluate different properties of the signal path. 18. The method for testing a signal path according to any one of claims 15 to 17, wherein a phase change of the test signal or a phase change of the reference signal is generated from an output of the first low pass filter. The maximum or minimum value of the signal or a static signal at one of the outputs of the second low pass filter or the like thereby allows the number of properties of the signal path to be determined. 19. The method for testing a signal path according to any one of claims 15 to 18, wherein the test signal is repeatedly coupled to the test signal, the two input signals are applied, and the test signal is applied after the test signal passes through the signal path. Reference 49 201027100 Signals and evaluation of the test signal and the like are performed by measuring different characteristics of the signal path and the different changes of the applied signal to evaluate the signal path. 20. A computer program having a code for executing a method as claimed in any one of claims 12 to 19 when the computer program is run on a computer or a microcontroller . ❿ 50