201025500 六、發明說明： 【發明所屬之技術領域】201025500 VI. Description of the invention: [Technical field to which the invention belongs]
本發明是有關於一種積體電路（integrated circuit，1C )製作方法，特別是指一種可杜絕電遷移（electr〇migrati〇n )現象發生的積體電路製作方法。 【先前技術】 電遷移現象是指在電場的作用下，可導電的金屬離子 運動而造成元件或電路失效的現象；隨著對積體電路的體 Φ 積尺寸持續縮減的需求，能否解決電遷移現象是積體電路 發展的主要限制之一。 參閱圖1，一般，積體電路包含一本體丨丨，及設置在該 本體11中並具有複數彼此成預定電連接之電路細胞ι21的 微電路集合12,藉著具有多數電路細胞ι21之微電路集合 的運算作動，發揮積體電路的電性功能。 參閲圖2，由於微電路集合12的電路細胞12ι動辄成 千上百，其中難免會出現有缺陷而無法運作的電路細胞121 • ’而使得積體電路無法發揮預定的電性功能；而基於成本 考量’積體電路當然不能因為其中某一電路細胞12ι出現 缺陷而整顆作廢，所以會於積體電路的微電路集合12中， 多設置複數電性功能與電路細胞121相同的預備電路細胞 122 (redundancy circuit cell)，及複數電連接該等電路細胞 121與預備電路細胞122的連接線路123，並在本體11上對 應於該等連接線路123的位置上開設至少一讓連接線路123 裸露出的開窗13，而當經過檢測發現有缺陷的電路細胞 201025500 121時即以雷射熔絲（iaser fuse)方式作用對應位於該開 窗13中的連接線路123,使得電通路由原本由行經該具有 缺陷的電路細胞121轉而行經該對應的預備 電路細胞122， 利用該預備電路細胞122取代有缺陷的電路細胞121，進而 保證微電路集合12的正常運作。 而這樣的方式，雖然可以預備電路細胞122取代有缺 陷的電路細胞121，而解決了積體電路不因單一電路細胞 121的缺陷而導致整顆機體電路失效的問題。 但是’隨著體積體電路的電性功能需求愈來愈龐大時 ，意味著其中微電路集合12的電路細胞121、預備電路細 胞122與連接線路123的密度愈來愈高，因此，位於開窗 中的連接線路123與連接線路123之間會因為密度提高、 間距縮減，且彼此間並未有任何防護措施而更容易產生金 屬離子的電遷移現象，進而導致積艎電路失效；特別是在 積體電路進入90奈米以下的高階製程，以及可預見的銅晶 片技術引入後，電遷移現象的產生將會是積體電路的主要 良率限制，而對此，目前並沒有注意到此一發展瓶頸，當 然也沒有人提出解決的方法。 【發明内容】 因此，本發明之目的’即在提供一種具有防金屬離子 遷移之隔離層的積體電路製造方法，用以生產製作不會產 生金屬離子電遷移的積體電路。 於是，本發明一種具有防金屬離子遷移之隔離層的積 體電路製造方法，包含以下三步驟。 201025500 首先以標準半導體製作製程製作一具有一本體與一設 置在該本體中之微電路集合的積體電路半成品，該微電路 集合並包括複數彼此成預定電連接的電路細胞、複數預備 電路細胞，及複數電連接該等電路細胞與預備電路細胞的 連接線路。 接著將該積體電路板成品的本體開設至少一將其中至 少一連接線路裸露的開窗。 最後將一自身玻璃轉換溫度不小於l50〇c的材料填覆該 φ 開窗’形成一將對應位於該開窗中的該連接線路埋覆的隔 離層’製得該具有防金屬離子遷移之隔離層的積體電路。 本發明之功效在於：提出完整、且不會污染已製作之 微電路集合的積體電路製造方法，解決目前積體電路之開 窗中的連接線路會發生電遷移而導致元件失效的問題。 【實施方式】 有關本發明之前述及其他技術内容、特點與功效，在 以下配合參考圖式之二個較佳實施例的詳細說明中，將可 φ 清楚的呈現。 在本發明被詳細描述之前，要注意的是，在以下的說 明内容中，類似的元件是以相同的編號來表示。 參閱圖3’本發明具有防金屬離子遷移之隔離層的積體 電路製造方法的一第一較佳實施例，包含三步驟以製作具 有防金屬離子遷移之隔離層的積體電路，解決積體電路進 入90奈米以下的高階製程，以及銅晶片技術引入後’電遷 移現象的產生問題。 5 201025500 參閱圖3、圖4，首先進行步驟31，製作如圖4所示之 具有一本體41與一設置在該本體41中之微電路集合42的 積體電路半成品，該微電路集合42並包括複數彼此成預定 電連接的電路細胞421、複數預備電路細胞422，及複數電 連接該等電路細胞421與預備電路細胞422的連接線路423 ，由於此步驟已為業界所週知之標準半導體製程，在此不 重複贅述。 參閲圖3、圖5,接著進行步驟32,將該積體電路半成 w的本體41開設至少—將其中至少_連接線路423裸露的 開窗43。 參閲圖3 ® 6’最後進行步驟33，將一自身玻璃轉換 溫度不小於丨耽的材料，例如聚酿亞胺（pQiymide)等耐 高溫、耐化學性之高分子材料填復該開窗43中，形成一將 對應位於該開窗43中的該連接線路423埋覆的隔離層44， 即&成該具有金屬離子遷移之隔離層的積體電路的製作 本步驟33 +，是利用材料本身在大於璃轉換溫度B 成液態的特性，保持該材料在大於15〇。〇的溫度下以㈣ 點膠機以轉方々純㈣冑43巾㈣塗覆方5 填覆該開自43後，厚度在。以上冷卻至低於。们 即固化成該隔離層44，谁茲 進而藉者隔離層44構成材料在低;5 玻璃轉換溫度時呈;★纟士 # & 1 A + 又卞主來結狀態如破璃狀而具有極小的自由旁 積’以及足夠的厚度钵 L卩該隔離層44表面至該連接線3 423的距離，至少靈η 1 、 /冷O.lMm)，而可阻擋二相鄰之連接線足 201025500 423間的例如銅等金屬離子的電遷移現象，進而有效達到杜 絕積體電路運作失效的情形發生。 由上述本發明第一較佳實施例的說明可知，本發明的 特點是更在現有的積體電路的製程之後’以精密點膠方式 ，或是旋佈塗覆方式，將自身玻璃轉換溫度不小於15(TC的 材料填覆在開窗43中而構成隔離層44,以阻擋連接線路 423間產生金屬離子的電遷移現象，過程在實施上不但快速 、便宜，且相較於現有的積體電路製程，僅相當於多增加 一道後製程，可簡單導入目前的積體電路製程中，而確實 解決電遷移現象發生導致積體電路良率降低的問題。 參閱圖7,本發明具有防金屬離子遷移之隔離層的積體 電路製造方法的一第二較佳實施例，包含四步驟以製作具 有防金屬離子遷移之隔離層的積體電路，解決積體電路以 預備電路細胞422取代具有缺陷之電路細胞42丨後，對應 位於開窗43中的連接線路423產生金屬離子電遷移現象， 而導致積體電路失效的問題。 先依序進行步驟71、步驟72，類似於第一較佳實施例 所述的步驟31、步驟32,製作具有本體41與設置在該本 體41中之微電路集合42的積體電路半成品，該微電路集 合42並包括複數彼此成預定電連接的電路細胞421、複數 預備電路細胞422 ’及複數電連接該等電路細胞421與預備 電路細胞422的連接線路423 ’然後將該積體電路半成品的 本體41開設至少一將其中至少一連接線路423裸露的開窗 43 ;由於此等步驟已為業界所週知之標準半導體製程，在 201025500 此不重複資述。 一般在製得積體電路半成品後，會進行電路細胞421 檢測的工作，檢測微電路集合42中的電路細胞421是否能 正常運作’所以在製得龍電路半成品後，隨即可經過^ 測而得知電路集合42中具有缺陷的電路細胞421的位置。 參閲圖7、圖8 ’接著進行步驟73’將具有缺陷之電路 細胞421對應位於該開窗43中的該連接線路423，以高能 量（雷射）作用而成一相間隔且可導電的導電段424，及— 連接該兩導電段424且具有高電阻值而使該二導電段424 成電不導通的熔燒段425，讓預備電路細胞422取代此具有 缺陷的電路細胞421，以維持該微電路集合42整體的運作 正常。 參閱圖7、圖9,最後進行步驟64,將一自身玻璃轉換 溫度不小於150X：的材料，例如聚醯亞胺（p〇lymide)等耐 高溫、耐化學性之高分子材料填覆該開窗43中，形成一把 對應位於該開窗43中的該連接線路423埋覆起來的隔離層 44，即完成該具有防金屬離子遷移之隔離層的積體電路的❹ 製作。 類似地’本發明的第二較佳實施例也是利用自身玻璃 轉換溫度約是150C的材料構成隔離層44，藉著隔離層5 阻擋經過高能量雷射作用之連接線路間的例如銅等金屬離 子的電遷移現象’進而避免積體電路在以預備電路細胞422 取代有缺陷的電路細胞421之後，微電路集合42運作失效 的情形發生，而更有效地提昇積體電路的製程良率。 8 201025500 同樣地，本發明是更在現有的積體電路的製程之後， 以精密點膠方式，或是旋佈塗覆方式，將自身玻璃轉換溫 * 度不小於15〇°C的材料填覆在開窗43中而構成隔離層44, 以阻擋經過高能量處理之連接線路423間產生金屬離子電 遷移現象的發生’；在施作上不但快速、便宜，且相較於現 ·· 有的積體電路製程，僅相當於多增加一道後製程，可簡單 導入目前的積體電路製程中，並同時解決電遷移現象發生 導致積體電路良率降低的問題。 φ 綜上所述’本發明是提出完整的積體電路的製造方法 ’在不影響現有的積趙電路製程下，以自身玻璃轉換溫度 不小於150°C的材料，填覆在積體電路的開窗形成覆蓋對應 位於開窗中之連接線路的隔離層的後製程，防止連接線路 間金屬離子電遷移現象的產生，有效達到杜絕積體電路運 作失效的情形發生，確實達到本發明的創作目的。 惟以上所述者’僅為本發明之較佳實施例而已，當不 能以此限定本發明實施之範圍，即大凡依本發明申請專利 • 範圍及發明說明内容所作之簡單的等效變化與修飾，皆仍 屬本發明專利涵蓋之範圍内。 【圖式簡單說明】 圖1是一俯視圖，說明現有的積體電路； 圖2是一俯視圖，說明現有的具有開窗並以預備電路 細胞取代有缺陷的電路細胞的積體電路； 圖3是一流程圖，說明本發明具有防金屬離子遷移之 隔離層的積體電路製造方法的一第一較佳實施例； 201025500 圖4 一俯視圖’說明實施圖3本發明之第一較佳實施 例之一步驟31時製作的一積體電路半成品； 圖5是一俯視圖，說明實施圖3本發明之第一較佳實 施例之一步驟32時，於一積體電路半成品上開設至少一開 窗； 圖6是一剖視示意圖，說明實施圖3本發明之第一較‘ 佳實施例之一步驟33時，於一開窗中形成一隔離層而完成 具有防金屬離子遷移之隔離層的積體電路的製作； 圖7是一流程圖，說明本發明本發明具有防金屬離子參 遷移之“離層的積體電路製造方法的一第二較佳實施例； 圖8是一剖視示意圖’輔助說明實施圖73本發明之第 二較佳實施例之一步驟73時，以雷射將連接線路作用成導 電段與溶燒段’而讓預備電路細胞取代具有缺陷的電路細 胞；及 圖9是一剖視示意圖，說明實施圖7本發明之第二較 佳實施例之一步驟74時，於一開窗中形成一隔離層，完成 具有防金屬離子遷移之隔離層的積體電路的製作。 應 10 201025500 【主要元件符號說明】 31 步驟 425 熔燒段 32 步驟 43 開窗 33 步驟 44 隔離層 41 本體 71 步驟 42 微電路集合 72 步驟 421 電路細胞 73 步驟 422 預備電路細胞 74 步驟 423 連接線路 424 導電段 ❹ 11The present invention relates to a method for fabricating an integrated circuit (1C), and more particularly to a method for fabricating an integrated circuit that eliminates the occurrence of electromigration (electr〇migrati〇n). [Prior Art] Electromigration refers to the phenomenon that the conductive metal ions move under the action of an electric field, causing component or circuit failure. With the demand for the body Φ product size of the integrated circuit, the power can be solved. Migration is one of the main limitations of the development of integrated circuits. Referring to FIG. 1, in general, an integrated circuit includes a body 丨丨, and a microcircuit set 12 disposed in the body 11 and having a plurality of circuit cells ι21 electrically connected to each other by a plurality of circuit cells ι21 The operation of the set operates to take advantage of the electrical function of the integrated circuit. Referring to FIG. 2, since the circuit cells of the microcircuit set 12 are tens of hundreds of cells, it is inevitable that defective circuit cells (121) can not function, and the integrated circuit cannot perform the predetermined electrical function; Based on the cost considerations, the integrated circuit can of course not be completely obsolete due to the defect of one of the circuit cells 121. Therefore, in the microcircuit set 12 of the integrated circuit, multiple preparatory circuits having the same electrical function as the circuit cell 121 are provided. a 122 (redundancy circuit cell), and a plurality of connection lines 123 electrically connecting the circuit cells 121 and the preparatory circuit cells 122, and at least one of the positions corresponding to the connection lines 123 on the body 11 to expose the connection lines 123 Opening the window 13, and when it is found that the defective circuit cell 201025500 121 is detected, it acts in the form of a laser fuse to correspond to the connecting line 123 located in the window 13, so that the electrical path is originally passed by The defective circuit cell 121 in turn passes through the corresponding preliminary circuit cell 122, and the defective circuit cell 122 is used to replace the defective battery The path cells 121, in turn, ensure proper operation of the microcircuit set 12. In this way, although the circuit cell 122 can be prepared to replace the defective circuit cell 121, the problem that the integrated circuit does not cause the failure of the entire body circuit due to the defect of the single circuit cell 121 is solved. However, as the electrical function requirements of the volume circuit become larger and larger, it means that the density of the circuit cells 121, the preparatory circuit cells 122, and the connection line 123 of the microcircuit set 12 is higher and higher, and therefore, the window is opened. The connection between the connection line 123 and the connection line 123 may be more likely to cause electromigration of metal ions due to increased density, reduced pitch, and no protective measures between them, thereby causing failure of the accumulation circuit; After the body circuit enters the high-order process below 90 nm, and the introduction of the foreseeable copper wafer technology, the generation of electromigration will be the main yield limit of the integrated circuit, and for this reason, this development has not been noticed. The bottleneck, of course, no one has proposed a solution. SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an integrated circuit manufacturing method having an isolation layer for preventing migration of metal ions for producing an integrated circuit which does not cause metal ion electromigration. Thus, the method of manufacturing an integrated circuit having an isolation layer for preventing metal ion migration comprises the following three steps. 201025500 Firstly, a semiconductor circuit manufacturing process having a body and a microcircuit assembly disposed in the body is fabricated in a standard semiconductor fabrication process, and the microcircuit assembly includes a plurality of circuit cells and a plurality of preparatory circuit cells that are electrically connected to each other. And a plurality of electrical connections connecting the circuit cells to the preparatory circuit cells. Then, the body of the finished integrated circuit board is opened with at least one open window in which at least one connecting line is exposed. Finally, a material having a self-glass transition temperature of not less than l50 〇c is filled to fill the φ window to form a spacer layer corresponding to the connection line buried in the window, and the metal ion migration is isolated. The integrated circuit of the layer. The effect of the present invention is to provide a method for manufacturing an integrated circuit which is complete and does not pollute the assembled microcircuit set, and solves the problem that the connection line in the open window of the integrated circuit can be electromigrated and the component fails. [Embodiment] The foregoing and other technical contents, features and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments of the drawings. Before the present invention is described in detail, it is noted that in the following description, similar elements are denoted by the same reference numerals. Referring to FIG. 3, a first preferred embodiment of the method for fabricating an integrated circuit having an isolation layer for preventing metal ion migration, comprising three steps for fabricating an integrated circuit having an isolation layer for preventing metal ion migration, and solving the integrated body The circuit enters a high-order process below 90 nm, and the problem of electromigration occurs after the introduction of copper wafer technology. 5 201025500 Referring to FIG. 3 and FIG. 4, step 31 is first performed to produce an integrated circuit semi-finished product having a body 41 and a microcircuit set 42 disposed in the body 41 as shown in FIG. 4, and the microcircuit set 42 is The circuit 421, the plurality of preparatory circuit cells 422, and the plurality of connection circuits 423 electrically connecting the circuit cells 421 and the preparatory circuit cells 422 are electrically connected to each other. Since this step is a standard semiconductor process well known in the industry, The details are not repeated here. Referring to Figures 3 and 5, proceeding to step 32, the body 41 of the integrated circuit half-w is opened at least - a window 43 in which at least the connection line 423 is exposed. Referring to Fig. 3 ® 6', finally step 33 is performed to fill a window 43 with a high temperature resistant chemical resistant material such as a material having a self-glass transition temperature of not less than 丨耽, such as polystyrene (pQiymide). Forming an isolation layer 44 corresponding to the connection line 423 located in the window 133, that is, forming the integrated circuit of the isolation layer having the metal ion migration. This step 33 + is to utilize the material. It is inherently greater than the glass transition temperature B to a liquid state, maintaining the material at greater than 15 〇. At the temperature of the crucible, the thickness is in the (4) dispensing machine with the rotating square 々 pure (four) 胄 43 towel (four) coated square 5 filled with the opening 43. The above is cooled to below. They are solidified into the isolation layer 44, which in turn borrows the spacer layer 44 to form a material at a low; 5 glass transition temperature; ★ gentleman # & 1 A + and then the main junction state is broken like a very small free product 'and a sufficient thickness 钵L卩 the distance from the surface of the isolation layer 44 to the connecting line 3 423, at least Ling η 1 , / cold O.lMm), and can block two adjacent connecting lines 201025500 The electromigration phenomenon of 423 metal ions such as copper is effectively achieved to prevent the failure of the integrated circuit operation. According to the description of the first preferred embodiment of the present invention, the present invention is characterized in that the temperature of the glass is not converted by the precise dispensing method or the rotary coating method after the process of the existing integrated circuit. Less than 15 (the material of the TC is filled in the window 43 to form the isolation layer 44 to block the electromigration phenomenon of metal ions generated between the connection lines 423, and the process is not only fast and inexpensive, but also compared with the existing integrated body. The circuit process is only equivalent to adding one more post process, which can be easily introduced into the current integrated circuit process, and indeed solves the problem that the electromigration phenomenon causes the integrated circuit to decrease in yield. Referring to FIG. 7, the present invention has metal ion prevention. A second preferred embodiment of the integrated circuit manufacturing method for the migrating isolation layer comprises four steps for fabricating an integrated circuit having an isolation layer for preventing metal ion migration, and solving the integrated circuit to replace the defective circuit cell 422 with a defective circuit After the circuit cells are 42 turns, the metal ion electromigration phenomenon is generated corresponding to the connection line 423 located in the window 133, which causes a problem of failure of the integrated circuit. Step 71 and step 72 are performed to form an integrated circuit semi-finished product having a body 41 and a microcircuit set 42 disposed in the body 41, similar to step 31 and step 32 of the first preferred embodiment. 42 includes a plurality of circuit cells 421, a plurality of preparatory circuit cells 422', and a plurality of connection circuits 423' electrically connected to the circuit cells 421 and the preparatory circuit cells 422, and then the body 41 of the integrated circuit semi-finished product is opened. At least one of the fenestrations 43 in which at least one of the connection lines 423 is exposed; since these steps are well-known standard semiconductor processes in the industry, this is not repeated in 201025500. Generally, after the integrated circuit semi-finished products are manufactured, the circuit is performed. The operation of the cell 421 detects whether the circuit cell 421 in the microcircuit set 42 can operate normally. Therefore, after the semi-finished product of the dragon circuit is fabricated, the position of the circuit cell 421 having the defect in the circuit set 42 can be known through the measurement. Referring to FIG. 7 and FIG. 8 'following step 73', the defective circuit cell 421 is corresponding to the connecting line located in the window 43. 423, with high energy (laser) acting as a phase-separated and electrically conductive conductive segment 424, and a fusion segment connecting the two conductive segments 424 and having a high resistance value to electrically non-conduct the two conductive segments 424 425, the preparatory circuit cell 422 is substituted for the defective circuit cell 421 to maintain the normal operation of the microcircuit set 42. Referring to FIG. 7 and FIG. 9, finally, step 64 is performed to convert a self glass to a temperature of not less than 150X: A material, such as a high temperature resistant chemical resistant polymer material such as p〇lymide, is filled in the fenestration 43 to form a connection line 423 corresponding to the fenestration 43. The isolation layer 44, that is, the fabrication of the integrated circuit that completes the isolation layer with metal ion migration prevention. Similarly, the second preferred embodiment of the present invention also utilizes a material having a self-glass transition temperature of about 150 C to form the spacer layer 44, and the barrier layer 5 blocks metal ions such as copper between the connecting lines through the high-energy laser. The electromigration phenomenon further prevents the integrated circuit from failing after the defective circuit cell 421 replaces the defective circuit cell 421, and the microcircuit assembly 42 fails to operate, thereby more effectively improving the process yield of the integrated circuit. 8 201025500 Similarly, the present invention fills the material of the glass with a temperature of not less than 15 ° C in a precise dispensing manner or a rotary coating method after the process of the existing integrated circuit. The isolation layer 44 is formed in the fenestration 43 to block the occurrence of metal ion electromigration between the high-energy-treated connection lines 423; not only is it fast and inexpensive, but also compared to the existing ones. The integrated circuit process is only equivalent to adding one more post process, which can be easily introduced into the current integrated circuit process, and at the same time solves the problem that the electromigration phenomenon causes the integrated circuit yield to decrease. φ In summary, the present invention is a method for manufacturing a complete integrated circuit, which is filled with a material having a glass transition temperature of not less than 150 ° C without affecting the existing product of the integrated circuit, and is filled in the integrated circuit. Opening the window to form a post-process covering the isolation layer corresponding to the connecting line in the window, preventing the occurrence of metal ion electromigration between the connecting lines, effectively achieving the occurrence of failure of the integrated circuit operation, and indeed achieving the creative purpose of the present invention . However, the above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, that is, the simple equivalent changes and modifications made by the scope of the invention and the scope of the invention. All remain within the scope of the invention patent. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view showing a conventional integrated circuit; FIG. 2 is a plan view showing a conventional integrated circuit having a window opening and replacing a defective circuit cell with a preparatory circuit cell; A flow chart illustrating a first preferred embodiment of a method for fabricating an integrated circuit having an isolation layer for preventing metal ion migration; 201025500 FIG. 4 is a top view of the first preferred embodiment of the present invention. An integrated circuit semi-finished product produced in a step 31; FIG. 5 is a plan view showing at least one open window on a semi-finished product of the integrated circuit when performing step 32 of the first preferred embodiment of the present invention; Figure 6 is a cross-sectional view showing the integration of an isolation layer having metal ion migration prevention by forming an isolation layer in a window when performing step 33 of the first preferred embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 7 is a flow chart illustrating a second preferred embodiment of the method for fabricating a discrete layer integrated circuit having metal ion barrier migration according to the present invention; FIG. 8 is a cross-sectional view </ RTI> Assisting in the implementation of step 73 of the second preferred embodiment of the present invention, the laser acts as a conductive segment and a burn-in segment by laser, and the preparatory circuit cells replace the defective circuit cells; 9 is a schematic cross-sectional view showing the formation of an isolation layer in an open window to complete the step 74 of the second preferred embodiment of the present invention, and completing the integrated circuit with the isolation layer for preventing metal ion migration. Production 10 should be 10 201025500 [Main component symbol description] 31 Step 425 Melting section 32 Step 43 Opening window 33 Step 44 Isolation layer 41 Body 71 Step 42 Microcircuit collection 72 Step 421 Circuit cell 73 Step 422 Preparation circuit Cell 74 Step 423 Connection Line 424 Conductive section ❹ 11