TW201023360A - Lateral diffused metal oxide semiconductor device - Google Patents

Lateral diffused metal oxide semiconductor device Download PDF

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Publication number
TW201023360A
TW201023360A TW097148654A TW97148654A TW201023360A TW 201023360 A TW201023360 A TW 201023360A TW 097148654 A TW097148654 A TW 097148654A TW 97148654 A TW97148654 A TW 97148654A TW 201023360 A TW201023360 A TW 201023360A
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region
conductivity type
deep well
substrate
well region
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TW097148654A
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TWI380447B (en
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Po-An Chen
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Nuvoton Technology Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

Abstract

A lateral diffused metal oxide semiconductor (LDMOS) device includes a substrate, a deep well region of a first conductivity type, a well region of a second conductivity type, a source region of the first conductivity type, a drain region of the first conductivity type, a channel region, a plurality of doped layers of the second conductivity type and a gate electrode. The deep well region and the well region are disposed in the substrate. The source region is disposed in the well region. The drain region is disposed in the deep well region. The channel region is disposed in a portion of the deep well region between the source region and the drain region. The doped layers are disposed in the deep well region between the channel region and the drain region to form a plurality of depletion regions and to increase depletion degree of the deep well region, and the depletion degree of the deep well region adjacent to the drain region is higher than that of other regions of the deep well region. The gate electrode is disposed on the substrate between the source region and the drain region and covers the channel region.

Description

201023360 fd 7 …—----/twf.doc/e 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體元件，且特別是關於一種橫向擴散金 氧半導體元件。 【先前技術】 橫向擴散金氧半（lateral diffused metal oxide semiconductor ; LDMOS)電晶體目前已廣泛地應用在各種電源積體電路或智慧型電源 積體電路上。一般而言，LDMOS電晶體在使用上需具有高崩潰電壓 (breakdown voltage)與低的開啟電阻(〇n_state如伽⑽；R〇n)，以提高 凡件之效能。為獲得高崩潰電壓，—種被稱之為減少表面電場 (Reduced Surface Field ; RESURF)結構之 LDM〇s 電晶體應運而生。 由於RESURF結構之橫向擴散金氧半導體電㉟體在操作時可以使 得源極區姐祕之間的深井區完全空乏，使源紐與錄區之間形 成均勻的電場’元件關潰電壓可因此而提升。然而，目前所發展的 RESURF結構之LDMQS電晶體具有開啟電阻無法進—步下降的問 題’而使LDMOS電晶聽紐得更佳的元件雜。故，此領絲需 一種具有高崩潰電壓和/或低開啟電阻的LDMOS電晶體，以提升 LDMOS電晶體的元件特性。 【發明内容】 本發明實施例提供—種具有高崩潰電壓和/或健通電阻之橫向 擴散金氧半導體元件。 依照本發明—實關，提*—種橫向擴散金氧半導體元件，其包 5 201023360,iWfd0C/e 括基底、具有第一導電型之深井區、具有第二導電型之井區、具有第 一導電型之源極區、具有第一導電型之汲極區、通道區、具有第二導 電型之多個摻雜層以及閘極。深井區與井區位於基底中。源極區位於 井區中。汲極區位於深井區中。通道區位於源極區與汲極區之間的部 分井區中。摻雜層位於通道區與汲極區之間的深井區中，使形成多個 空乏區域，以提高深井區之空乏程度，且鄰近汲極區之深井區相較於 深井區的其他部份具有較高的空乏程度。閘極位於汲極區以及源極區 之間的基底上並且覆蓋通道區。201023360 fd 7 ...-----/twf.doc/e IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor element, and more particularly to a laterally diffused MOS element. [Prior Art] Lateral diffused metal oxide semiconductor (LDMOS) transistors have been widely used in various power integrated circuits or smart power integrated circuits. In general, LDMOS transistors require a high breakdown voltage and a low turn-on resistance (〇n_state such as gamma (10); R〇n) to improve the performance of the device. In order to obtain a high breakdown voltage, an LDM〇s transistor called a reduced surface field (RESURF) structure has emerged. Due to the lateral diffusion of the RESURF structure, the MOS semiconductor body 35 can make the deep well region between the source region and the recording area completely depleted during operation, so that a uniform electric field is formed between the source and the recording area, and the component shutdown voltage can be Upgrade. However, the LDMQS transistor of the RESURF structure currently developed has a problem that the turn-on resistance cannot be stepped down and the LDMOS is better. Therefore, the lead wire requires an LDMOS transistor having a high breakdown voltage and/or a low on-resistance to improve the element characteristics of the LDMOS transistor. SUMMARY OF THE INVENTION Embodiments of the present invention provide a laterally diffused MOS device having a high breakdown voltage and/or a gate resistance. According to the present invention, a laterally diffused MOS device is provided, and the package 5 201023360, iWfd0C/e includes a substrate, a deep well region having a first conductivity type, a well region having a second conductivity type, and having a first a source region of a conductivity type, a drain region having a first conductivity type, a channel region, a plurality of doped layers having a second conductivity type, and a gate. The deep well area and the well area are located in the basement. The source area is located in the well area. The bungee area is located in the deep well area. The channel zone is located in a portion of the well zone between the source zone and the bungee zone. The doped layer is located in the deep well region between the channel region and the drain region, so that a plurality of depletion regions are formed to increase the degree of depletion in the deep well region, and the deep well region adjacent to the bungee region has a larger portion than the other portions of the deep well region. Higher levels of depletion. The gate is located on the substrate between the drain region and the source region and covers the channel region.

A 依照本發明另一實施例，提出一種橫向擴散金氧半導體元件，其 包括基底、具有第一導電型之深井區、具有第二導電型之井區、具有 第一導電型之源極區、具有第一導電型之汲極區、通道區、具有第二 導電型之至少一摻雜層以及閘極。深井區與井區位於基底中。源極區 位於井區中。汲極區位於深井區中。通道區位於源極區與汲極區之間 的部分井區中。摻雜層位於通道區與汲極區之間的深井區中，使形成 空乏區域，以提高深井區之空乏程度，且鄰近汲極區之摻雜層具有較 高的摻質濃度’使鄰近汲極區之深井區相較於深井區的其他部份具有 & 較高的空乏程度。閘極位於汲極區以及源極區之間的基底上並且覆蓋 通道區。 依照本發明再一實施例，提出一種橫向擴散金氧半導體元件，其 包括基底、具有第一導電型之深井區、具有第二導電型之井區、具有 第一導電型之源極區、具有第一導電型之汲極區、通道區、具有第二 導電型之多個摻雜層以及閘極。深井區與井區位於基底中。源極區位 於井區中。汲極區位於深井區中。通道區位於源極區與汲極區之間的 部分井區中。摻雜層位於通道區與汲極區之間的深井區中，每一摻雜 201023360 twfdoc/e 閘極位於没 層包括多個彼此分離的摻純塊，使形成多個空乏區域 極區以及源極區之_基底上並且覆蓋通道區。 壓和/或接通電阻 本發明上述實關所述之橫向舰金料導體元件巾，透過在深 =區中配置摻雜層的方式，可調整横向擴散金氧半導體元件的崩潰電 【實施方式】 【第一實施例】 ® 1為依照本發明之第—實施例崎示的橫向擴散錢半導體元 件的剖面構造示意圖。 請參關1，橫向雙擴散金氧半導體元件10包括基底1〇〇、具有 第導電型之深井區102、具有第二導電型之井區1〇4、具有第一導電 型之沒極區106、具有第_導電型之源極區1〇8、通道區ιι〇、具有第 -導電型之多個摻雜層ma、mb、此以及雜⑴。在本實施例 中’基底1GG例如可為具有第二導電型的基底。且，橫向雙擴散金氧 半導體元件ίο可更包括隔離結構116、具有第二導電型之接觸區ιι8 以及間隙壁122。第一導電型可為p型或N型，當第一導電型為p型 時，第二導電型為N型，而當第一導電型為N型時，第二導電型為p 型。在本實施例中，以N型來表示第一導電型，以p型來表示第二導 電型。 在本實施例中，基底1〇〇例如是p型基底，其可為矽基底磊晶層 或其他半導體基底。深井區102例如是N型深井區，位於基底1〇〇中。 井區104例如是P型井區，位於基底100中。隔離結構116可位於閘 極113與汲極區106之間，其例如是場氧化層(F〇x)結構或淺溝渠隔離 7 201023360,iwfdDC/e (STI)結構。 汲極區106例如是N型，位於深井區1〇2中。源極區1〇8例如是 N型，位於井區1〇4中。通道區11〇位於汲極區1〇6與源極區1〇8之 間的部分井區104中。接觸區118例如是P型接觸區，位於井區1〇4 中，作為井區104的訊號接頭(pickup)。閘極113位於汲極區1〇6以及 源極區108之間的基底1〇〇上，並且覆蓋通道區11〇。閘極113包括閘 導電層114與閘介電層120。在本實施例中，閘導電層114的材料例如 是多晶矽。閘介電層120配置於閘導電層114與基底100之間，其材 ® 料例如是氧化矽、氮化矽或其他合適的介電材料。再者，閘極113的 側壁配置有間隙壁122，間隙壁122的材料例如是氧化矽、氮化矽或 其他合適的介電材料。 請參照圖1，摻雜層112a、112b、112c例如是P型，位於通道區 110與汲極區106之間的N型深井區1〇2中。在本實施例中，摻雜層 112a、112b、112c的摻質濃度例如是相同。摻雜層112a、112b、U2c 彼此分離且與基底100之上表面100a之間的垂直距離不同。詳言之， 摻雜層112a、mb、112c的第一邊緣P1與通道區11〇之間的水平距 ® 離可隨著摻雜層112a、112b、112c與基底100之上表面l〇〇a之間的 垂直距離的增加而增加。且，摻雜層112a、n2b、ll2c的第二邊緣P2 在基底100的深度方向上實質上可為對齊。 在本實施例中，第二導電型的摻雜層112a、112b、112c可在具有 第導電型的深井區102中形成多個空乏區域(depletion region)，以提 南深井區102之空乏程度，且鄰近汲極區ι〇6之深井區i〇2相較於深 井區102的其他部分(諸如鄰近通道區11〇之深井區1〇2)具有較高的空 乏程度。更具體而言’深井區102中的空乏區域的數目由鄰近汲極區 201023360,iWfdoc/e 106之深井區102往鄰近通道區110之深井區102遞減，藉此，使深井 區102的空乏程度由鄰近汲極區106的部分至鄰近通道區11〇的部分 例如是逐漸下降。因此，鄰近汲極區106之深井區1〇2的高電場能大 幅下降且能使鄰近通道區110之深井區102具有較低的接通電阻。故， 橫向擴散金氧半導體元件10可具有高崩潰電壓與低接通電阻，使得橫 向擴散金氧半導體元件10具有良好的元件特性。 請參照圖1，在本實施例中是以三個摻雜層112a、112b、112c為 例’但本發明不限於此，深井區102中也可以配置有其他個數的推雜 φ 層。且，在本實施例十，是以摻雜層U2a、112b、112c的第一邊緣ρι 逐漸遠離通道區110且第二邊緣P2可彼此對齊為例，但本發明不限於 此’舉例來說，圖1中的摻雜層ll2a、112b、Ilk的位置可以彼此互 換(未繪示）’如此一來，鄰近汲極區106之深井區1〇2的空乏程度仍較 深井區102的其他部分的空乏程度來的高。也就是說，只要橫向擴散 金氧半導體元件之摻雜層的配置方式能夠使得鄰近汲極區之深井區相 較於深井區的其他部分具有較高的空乏程度即符合本發明之精神上 述實施例僅是多種摻雜層配置方式的一種，而非用以限制本發明。 0 【第二實施例】 圖2為依照本發明第二實施例之橫向擴散金氧半導體元件的剖面 構造示意圖。在本實施例中，橫向擴散金氧半導體元件1〇a的結構與 第一實施例中所述的橫向擴散金氧半導體元件1〇的結構相似，以下僅 針對其主要不同處進行說明。 請參照圖2，在本實施例中，摻雜層U2a、U2b、n2c包括多個 摻雜區塊124a、124b、124c ’摻雜區塊124a、124b、124c的摻質濃度 例如是相同。且，摻雜區塊124a、124b、124c的尺寸例如是相同，因 此摻雜層112a、U2b、112c所包括的摻雜區塊的數目例如是隨著摻雜 9 201023360 rt%vf.doc/e 層112a、112b、112c與基底100之上表面i〇〇a之間的垂直距離的增 加而減少。此外，在本實施例中’不同摻雜層112a、112b、112c的摻 雜區塊124a、124b、124c在基底100的深度方向上例如是彼此對齊。 在本實施例中，在具有第一導電型的深井區102中配置多個摻雜 層112a、112b、112c，且掺雜層112a、112b、112c分別由具有第二導 電型的多個摻雜區塊124a、124b、U4c所構成，如此一來，深井區ι〇2 中可形成多個空乏區域，以提高深井區102之空乏程度，且鄰近没極 區106之深井區1〇2相較於深井區1〇2的其他部份具有較多的空乏區 ® 域，換言之，可具有較高的空乏程度。此外，在本實施例中，深井區 102的空乏程度由鄰近汲極區1〇6的部分至鄰近通道區11〇的部分例 如是逐漸下降。如此一來，鄰近汲極區106之深井區1〇2的高電場能 大幅下降且能使鄰近通道區110之深井區102具有較低的接通電阻。 特別一提的是，摻雜區塊124a、124b、124c使得摻雜層U2a、mb、 112c與深井區ι〇2的接觸面積大幅增加，故可使汲極區ι〇6與通道區 110之間的電場均勻地且迅速地下降。故，橫向擴散金氧半導體元件 l〇a具有高崩潰電壓與低接通電阻，使得橫向擴散金氧半導體元件⑺& 〇 具有良好的元件特性。 當然，在另一實施例中，如圖3所示，橫向擴散金氧半導體元件 1〇b可具有—整層的摻雜層112c與由摻雜區塊124a、124b構成的捧雜 層112a、112b，如此一來，鄰近汲極區106之深井區1〇2相較於深井 區102的其他部分具有較高的空乏程度。換言之，本發明未限制橫向 擴散金氧半導體元件之摻雜層或摻雜區塊的尺寸、數目以及排列方 式，只要摻雜層的配置方式能夠使得鄰近汲極區之深井區相較於深井 區的其他部分具有較高的空乏程度即可，上述實施例僅是多種摻雜層 201023360 ..jwf.doc/e 配置方式的一種’而非用以限制本發明。 【第三實施例】 圖4為依照本發明之第三實施例所繪示的橫向擴散金氧半導體元 件的剖面構造示意圖》 請參照圖4,橫向雙擴散金氧半導體元件1〇c包括基底1〇〇、具有 第一導電型之深井區1〇2、具有第二導電型之井區1〇4、具有第一導電 型之汲極區106、具有第一導電型之源極區1〇8、通道區11〇、具有第 二導電型之摻雜層II2以及閘極113。在本實施例中，基底1〇〇例如是 Φ 具有第二導電型的基底。且，橫向雙擴散金氧半導體元件1〇c更包括 隔離結構116、具有第二導電型之接觸區118以及間隙壁122。其中， 基底100、深井區102、井區1〇4、汲極區106、源極區1〇8、通道區 110、閘極113、隔離結構116、接觸區118以及間隙壁122可以參照 第一實施例中所述者，於此不贅述。其中，第一導電型可為卩型或^^ 盤，當第一導電型為P型時，第二導電型為N型。當第一導電型為n 犁時，第二導電型為p型。在本實施例中，以N型來表示第一導電型， 以P型來表示第二導電型。 ® 在本實施例中，橫向雙擴散金氧半導體元件l〇c包括具有第二導 電型之摻雜層112’摻雜層112位於通道區11〇與沒極區1〇6之間的深 丼區102中，使形成空乏區域，以提高深井區1〇2之空乏程度。且， 鄰近汲極區106之摻雜層112具有較高的摻質濃度，使鄰近汲極區1〇6 之深井區102相較於深井區1〇2的其他部份(諸如鄰近通道區之深 井區102)具有較高的空乏程度。前述摻雜層112的摻質濃度由鄰近汲 椏區106之深井區往鄰近通道區110之深井區1〇2遞減更具體而言， 巧"為呈梯度(gradient)遞減。措此，深井區的空乏程度可由鄰近褒極區 11 201023360 ,fd〇c/e i〇6至鄰近通道區n〇里梯度下降。如此一來，鄰近沒極區⑽之深 井區1〇2的高電場能述下降且缺鄰近通道區 110之深井區102具 有較低的接通電阻。故，橫向擴散金氧半導體元件i〇c具有高崩潰電 壓與低接通電阻，使得橫向擴散金氧半導體元件咖具有良好的元件 特性。 在圖4中是以深井區102中僅配置一層摻雜層ιΐ2為例，當然， 但在另-實施例中’如圖5所示，橫向雙擴散金氧半導體元件i〇d的 深井區102中可以配置有多個具有帛二導電型之捧雜層112&、112卜 ❼112c。其中，鄰近没極區1〇6之摻雜層112a、112b、112c的摻質濃度 例如是皆咼於其他部分(諸如鄰近通道區11〇)之摻雜層112a、112b、n2c 的摻質濃度。或者是，多個摻雜層112a、112b、112c中至少有一掺雜 層112a、112b、112c之鄰近汲極區1〇6部份具有較高的掺質濃度，舉 例來說，摻雜層112a、112b中整層的摻質濃度皆相同，而摻雜層U2c 之鄰近没極區106部份相較於摻雜層112c之其他部分具有較高的摻質 濃度。再者，摻雜層112a、112b、112c的摻質濃度也可以是由鄰近汲 極區106的部分至鄰近通道區11〇的部分例如是呈梯度(gradient)下 © 降’使得深井區102的空乏程度亦由鄰近没極區106至鄰近通道區110 呈梯度下降。如此一來，鄰近汲極區106之深井區1〇2的高電場能大 幅下降且能使鄰近通道區110之深井區102具有較低的接通電阻。故， 橫向擴散金氧半導體元件10d具有高崩溃電壓與低接通電阻，使得橫 向擴散金氧半導體元件10d具有良好的元件特性。 【第四實施例】 圖6為依照本發明之第四實施例所繪示的橫向擴散金氧半導體 元件的剖面構造示意圖。在本實施例中’橫向擴散金氧半導體元件10e 12 201023360 ..wf.doc/e 的結構與圖5所述的橫向擴散金氧半導體元件觀的結構相似，以下 僅針對其主要不同處進行說明。 在本實施例中，每-換雜層U2a、112b、U2e包括多個摻雜區塊 124a、124b、124c，且每一摻雜層U2a、n2b、mc之鄰近汲極區ι〇6 的摻雜區塊124a、124b、124e具有較高的摻度，使鄰近錄區ι〇6 之冰井區102相較於深井1 102的其他部份具有較高的空乏程度。也 就疋4 ’在同一摻雜層U2a、i12b、U2c中，鄰近汲極區1〇6的摻雜 區塊l24a、lMb、12如的摻質濃度例如是皆高於丼他摻雜區塊12乜、 ❼ mb、124c (諸如鄰近通道區110)的摻質濃度。再者，在一實施例中， 至少一摻雜層112a、112b、112c中的摻雜區塊i24a、124b、124c的摻 質濃度例如是由鄰近汲極區l〇6的部分至鄰近通道區11〇的部分呈梯 度(gradient)下降，使得深井區1〇2的空乏程度由鄰近汲極區1〇6至鄰 近通道區11〇呈梯度下降。如此一來，鄰近汲極區1〇6之深井區1〇2 的高電場能大幅下降且能使鄰近通道區11〇之深井區1〇2具有較低的 接通電阻。故，橫向擴散金氧半導體元件1〇e具有高崩潰電壓與低接 通電阻，使得橫向擴散金氧半導體元件l〇e具有良好的元件特性。 Ο 【第五實施例】 圖7為依照本發明之第五實施例所緣示的橫向擴散金氧半導體元 件的剖面構造示意圖。在本實施例中，橫向擴散金氧半導體元件i〇f 的結構與第一實施例中所述的橫向擴散金氧半導體元件10的結構相 似’以下僅針對其主要不同處進行說明。 在本實施例中，摻雜層112a、112b、112c位於通道區110與汲極 區106之間的N型深井區1〇2中，摻雜層U2a、112b、112C包括多個 彼此分離且為P型的摻雜區塊124a、124b、124c，以於深井區1〇2中 13 201023360 ..iwf.doc/e 形成多個空乏區域。在本實施例中，掺雜層112a、112b、112c例如是 彼此分離且與基底100之上表面100a之間的垂直距離不同。且，同— 摻雜層112a、lUb、lHc的摻雜區塊124a、124b、124c的摻質濃度例 如是相同。 在本實施例中’在具有第一導電型的深井區1〇2中配置多個摻雜 層112a、112b、112c，摻雜層li2a、112b、112c由具有第二導電型的 多個掺雜區塊l24a、l24b、l24c所構成’使得深井區1〇2與每—個摻 雜區塊124a、124b、124c的接面產生空乏區。摻雜區塊124a、12扑、A according to another embodiment of the present invention, a laterally diffused MOS device is provided, comprising: a substrate, a deep well region having a first conductivity type, a well region having a second conductivity type, a source region having a first conductivity type, A drain region having a first conductivity type, a channel region, at least one doped layer having a second conductivity type, and a gate. The deep well area and the well area are located in the basement. The source area is located in the well area. The bungee area is located in the deep well area. The channel zone is located in a portion of the well zone between the source zone and the bungee zone. The doped layer is located in the deep well region between the channel region and the drain region, so that a depletion region is formed to increase the degree of depletion in the deep well region, and the doping layer adjacent to the bungee region has a higher dopant concentration. The deep well area in the polar zone has a higher degree of depletion than the other parts of the deep well zone. The gate is located on the substrate between the drain region and the source region and covers the channel region. According to still another embodiment of the present invention, a laterally diffused MOS device includes a substrate, a deep well region having a first conductivity type, a well region having a second conductivity type, a source region having a first conductivity type, and A drain region of the first conductivity type, a channel region, a plurality of doped layers having a second conductivity type, and a gate. The deep well area and the well area are located in the basement. The source area is located in the well area. The bungee area is located in the deep well area. The channel zone is located in a portion of the well zone between the source zone and the bungee zone. The doped layer is located in the deep well region between the channel region and the drain region, and each doping 201023360 twfdoc/e gate is located in the unlayered layer including a plurality of doped pure blocks separated from each other to form a plurality of depleted region polar regions and sources The polar region is on the substrate and covers the channel region. Pressure and/or on-resistance The lateral ship-type gold conductor component of the above-mentioned embodiment of the present invention can adjust the collapse of the laterally diffused MOS device by disposing a doped layer in the deep=region. [First Embodiment] ® 1 is a schematic cross-sectional structural view of a lateral diffusion money semiconductor device according to a first embodiment of the present invention. Referring to FIG. 1, the lateral double-diffused MOS device 10 includes a substrate 1 , a deep well region 102 having a first conductivity type, a well region 1 〇 4 having a second conductivity type, and a gate region 106 having a first conductivity type. The source region 1〇8 of the first conductivity type, the channel region ιι, the plurality of doping layers ma, mb, and the impurity (1) having the first conductivity type. In the present embodiment, the substrate 1GG may be, for example, a substrate having a second conductivity type. Moreover, the lateral double-diffused MOS device ίο may further include an isolation structure 116, a contact region ι8 having a second conductivity type, and a spacer 122. The first conductivity type may be a p-type or an N-type. When the first conductivity type is a p-type, the second conductivity type is an N-type, and when the first conductivity type is an N-type, the second conductivity type is a p-type. In the present embodiment, the first conductivity type is represented by an N type, and the second conductivity type is represented by a p type. In the present embodiment, the substrate 1 is, for example, a p-type substrate, which may be a germanium base epitaxial layer or other semiconductor substrate. The deep well zone 102 is, for example, an N-type deep well zone located in the basement 1〇〇. The well region 104 is, for example, a P-type well region located in the substrate 100. The isolation structure 116 can be located between the gate 113 and the drain region 106, such as a field oxide layer (F〇x) structure or a shallow trench isolation 7 201023360, iwfdDC/e (STI) structure. The bungee region 106 is, for example, N-type and is located in the deep well area 1〇2. The source region 1〇8 is, for example, an N-type, located in the well region 1〇4. The channel region 11 is located in a portion of the well region 104 between the drain region 1〇6 and the source region 1〇8. The contact zone 118 is, for example, a P-type contact zone located in the well zone 1〇4 as a signal pickup for the well zone 104. The gate 113 is located on the substrate 1〇〇 between the drain region 1〇6 and the source region 108, and covers the channel region 11〇. Gate 113 includes gate conductive layer 114 and gate dielectric layer 120. In the present embodiment, the material of the gate conductive layer 114 is, for example, polysilicon. The gate dielectric layer 120 is disposed between the gate conductive layer 114 and the substrate 100, such as tantalum oxide, tantalum nitride or other suitable dielectric material. Further, the sidewall of the gate 113 is provided with a spacer 122, and the material of the spacer 122 is, for example, hafnium oxide, tantalum nitride or other suitable dielectric material. Referring to Figure 1, the doped layers 112a, 112b, 112c are, for example, P-type, located in the N-type deep well region 1〇2 between the channel region 110 and the drain region 106. In the present embodiment, the dopant concentrations of the doped layers 112a, 112b, 112c are, for example, the same. The doped layers 112a, 112b, U2c are separated from each other and have a different vertical distance from the upper surface 100a of the substrate 100. In detail, the horizontal distance between the first edge P1 of the doped layers 112a, mb, 112c and the channel region 11〇 may be along with the doping layers 112a, 112b, 112c and the upper surface of the substrate 100. The vertical distance between them increases. Moreover, the second edge P2 of the doped layers 112a, n2b, ll2c may be substantially aligned in the depth direction of the substrate 100. In this embodiment, the doping layers 112a, 112b, and 112c of the second conductivity type may form a plurality of depletion regions in the deep well region 102 having the first conductivity type to increase the degree of depletion of the deep well region 102. And the deep well area i〇2 adjacent to the bungee area ι〇6 has a higher degree of depletion than the other parts of the deep well area 102 (such as the deep well area 1〇2 adjacent to the channel area 11〇). More specifically, the number of depleted regions in the deep well region 102 is decreased from the deep well region 102 adjacent to the bungee region 201023360, iWfdoc/e 106 to the deep well region 102 adjacent to the tunnel region 110, thereby causing the depletion level of the deep well region 102. The portion from the portion adjacent to the drain region 106 to the adjacent channel region 11A is, for example, gradually lowered. Therefore, the high electric field energy of the deep well region 1〇2 adjacent to the bungee region 106 can be greatly reduced and the deep well region 102 of the adjacent channel region 110 can have a lower on-resistance. Therefore, the laterally diffused MOS device 10 can have a high breakdown voltage and a low on-resistance, so that the laterally diffused MOS device 10 has good element characteristics. Referring to Fig. 1, in the present embodiment, three doped layers 112a, 112b, and 112c are taken as an example. However, the present invention is not limited thereto, and other numbers of Φ layers may be disposed in the deep well region 102. Moreover, in the tenth embodiment, the first edge ρι of the doped layers U2a, 112b, 112c is gradually away from the channel region 110 and the second edge P2 may be aligned with each other, but the invention is not limited thereto, for example, The positions of the doped layers ll2a, 112b, Ilk in FIG. 1 may be interchanged with each other (not shown). Thus, the degree of depletion of the deep well region 1〇2 adjacent to the bungee region 106 is still higher than that of other portions of the deep well region 102. The degree of vacancies is high. That is, as long as the doped layer of the laterally diffused MOS device is disposed in such a manner that the deep well region adjacent to the drain region has a higher degree of depletion than other portions of the deep well region, which is in accordance with the spirit of the present invention. It is only one of a plurality of doping layer configurations, and is not intended to limit the present invention. [Second Embodiment] Fig. 2 is a cross-sectional structural view showing a laterally diffused MOS device according to a second embodiment of the present invention. In the present embodiment, the structure of the laterally diffused MOS device 1a is similar to that of the laterally diffused MOS device 1A described in the first embodiment, and only the main differences will be described below. Referring to FIG. 2, in the present embodiment, the dopant concentrations of the doped layers U2a, U2b, n2c including the plurality of doped blocks 124a, 124b, 124c' doped blocks 124a, 124b, 124c are, for example, the same. Moreover, the sizes of the doped blocks 124a, 124b, 124c are, for example, the same, and thus the number of doped blocks included in the doped layers 112a, U2b, 112c is, for example, with doping 9 201023360 rt%vf.doc/e The increase in the vertical distance between the layers 112a, 112b, 112c and the upper surface i〇〇a of the substrate 100 is reduced. Further, the doped blocks 124a, 124b, 124c of the different doped layers 112a, 112b, 112c in the present embodiment are, for example, aligned with each other in the depth direction of the substrate 100. In the present embodiment, a plurality of doping layers 112a, 112b, 112c are disposed in the deep well region 102 having the first conductivity type, and the doping layers 112a, 112b, 112c are respectively doped by a plurality of dopings having the second conductivity type. Blocks 124a, 124b, and U4c are formed. As a result, a plurality of depletion regions can be formed in the deep well area ι〇2 to increase the degree of depletion in the deep well area 102, and the depth of the deep well area adjacent to the non-polar area 106 is compared with 1〇2. The other part of the 1深2 area in Sham Tseng has more Depleted Areas®, in other words, can have a higher degree of depletion. Further, in the present embodiment, the degree of depletion of the deep well region 102 is gradually decreased from the portion adjacent to the drain region 1〇6 to the portion adjacent to the channel region 11〇. As a result, the high electric field of the deep well region 1〇2 adjacent to the bungee region 106 can be greatly reduced and the deep well region 102 of the adjacent channel region 110 can have a lower on-resistance. In particular, the doping blocks 124a, 124b, and 124c greatly increase the contact area between the doping layers U2a, mb, and 112c and the deep well region ι 2, so that the drain region ι 6 and the channel region 110 can be The electric field between them drops uniformly and rapidly. Therefore, the laterally diffused MOS device l〇a has a high breakdown voltage and a low on-resistance, so that the laterally diffused MOS devices (7) & 〇 have good device characteristics. Of course, in another embodiment, as shown in FIG. 3, the laterally diffused MOS device 1b may have a full-layer doped layer 112c and a doped layer 112a composed of doped blocks 124a, 124b, 112b, as such, the deep well zone 1〇2 adjacent to the bungee zone 106 has a higher degree of depletion than the other sections of the deep well zone 102. In other words, the present invention does not limit the size, number, and arrangement of the doped layers or doped blocks of the laterally diffused MOS device, as long as the doping layer is configured in such a manner that the deep well region adjacent to the drain region is compared to the deep well region. The other portions may have a higher degree of depletion. The above embodiment is merely one of a plurality of doping layers 201023360 ..jwf.doc/e configuration, and is not intended to limit the present invention. [THIRD EMBODIMENT] FIG. 4 is a cross-sectional structural view of a laterally diffused MOS device according to a third embodiment of the present invention. Referring to FIG. 4, the lateral double-diffused MOS device 1c includes a substrate 1. 〇〇, a deep well region having a first conductivity type, a well region 1〇4 having a second conductivity type, a drain region 106 having a first conductivity type, and a source region 1〇8 having a first conductivity type The channel region 11A, the doped layer II2 of the second conductivity type, and the gate 113. In the present embodiment, the substrate 1 is, for example, Φ having a substrate of a second conductivity type. Further, the lateral double-diffused MOS device 1〇c further includes an isolation structure 116, a contact region 118 having a second conductivity type, and a spacer 122. The substrate 100, the deep well region 102, the well region 1〇4, the drain region 106, the source region 1〇8, the channel region 110, the gate 113, the isolation structure 116, the contact region 118, and the spacer 122 may refer to the first The description in the embodiments is not described herein. The first conductivity type may be a 卩 type or a ^^ disk, and when the first conductivity type is a P type, the second conductivity type is an N type. When the first conductivity type is n plow, the second conductivity type is p-type. In the present embodiment, the first conductivity type is represented by an N type, and the second conductivity type is represented by a P type. In the present embodiment, the lateral double-diffused MOS device 10c includes a doped layer 112' having a second conductivity type, and the doped layer 112 is located between the channel region 11〇 and the non-polar region 1〇6. In the zone 102, a depletion zone is formed to increase the degree of depletion in the deep well zone 1〇2. Moreover, the doped layer 112 adjacent to the drain region 106 has a higher dopant concentration, such that the deep well region 102 adjacent to the drain region 1〇6 is compared to other portions of the deep well region 1〇2 (such as adjacent channel regions) The deep well area 102) has a high degree of depletion. The doping concentration of the doped layer 112 is decreased from the deep well region adjacent to the crucible region 106 to the deep well region 1〇2 adjacent to the channel region 110. More specifically, it is a gradient. Therefore, the degree of depletion in the deep well area can be reduced by the gradient between the adjacent bungee area 11 201023360, fd〇c/e i〇6 to the adjacent channel area. As a result, the high electric field of the deep well region 1 adjacent to the non-polar region (10) can be lowered and the deep well region 102 lacking the adjacent channel region 110 has a lower on-resistance. Therefore, the laterally diffused MOS element i〇c has a high breakdown voltage and a low on-resistance, so that the laterally diffused MOS device has good element characteristics. In FIG. 4, for example, a layer of doping layer ι 2 is disposed in the deep well region 102. Of course, in another embodiment, as shown in FIG. 5, the deep well region 102 of the lateral double-diffused MOS device i〇d is shown in FIG. A plurality of doping layers 112 & 112 and 112 cc having a second conductivity type may be disposed. The doping concentration of the doped layers 112a, 112b, 112c adjacent to the non-polar region 1〇6 is, for example, the doping concentration of the doped layers 112a, 112b, n2c which are in other portions (such as adjacent channel regions 11A). . Alternatively, a portion of the plurality of doped layers 112a, 112b, 112c adjacent to the drain region 1 〇 6 of the doped layers 112a, 112b, 112c has a higher dopant concentration, for example, the doped layer 112a The doping concentration of the entire layer in 112b is the same, and the adjacent non-polar region 106 portion of the doped layer U2c has a higher dopant concentration than the other portions of the doped layer 112c. Furthermore, the doping concentration of the doped layers 112a, 112b, 112c may also be from a portion adjacent to the drain region 106 to a portion adjacent to the channel region 11〇, for example, a gradient [lower down] to make the deep well region 102 The degree of depletion also falls from the adjacent non-polar region 106 to the adjacent channel region 110. As a result, the high electric field of the deep well region 1〇2 adjacent to the bungee region 106 can be greatly reduced and the deep well region 102 of the adjacent channel region 110 can have a lower on-resistance. Therefore, the laterally diffused MOS element 10d has a high breakdown voltage and a low on-resistance, so that the laterally diffused MOS element 10d has good element characteristics. [Fourth Embodiment] Fig. 6 is a cross-sectional structural view showing a laterally diffused MOS device according to a fourth embodiment of the present invention. In the present embodiment, the structure of the laterally diffused MOS device 10e 12 201023360 ..wf.doc/e is similar to that of the laterally diffused MOS device described in FIG. 5, and only the main differences will be described below. . In this embodiment, each of the impurity-doped layers U2a, 112b, and U2e includes a plurality of doped blocks 124a, 124b, and 124c, and the doping of each of the doped layers U2a, n2b, and mc adjacent to the drain region ι6 The miscellaneous blocks 124a, 124b, 124e have a higher degree of mixing, so that the ice well zone 102 adjacent to the recording zone ι 6 has a higher degree of depletion than the other sections of the deep well 1 102. In other words, in the same doped layer U2a, i12b, U2c, the dopant concentration of the doped blocks l24a, lMb, 12 adjacent to the drain region 1〇6 is, for example, higher than that of the doped block. The dopant concentration of 12乜, ❼ mb, 124c (such as adjacent channel region 110). Furthermore, in an embodiment, the doping concentration of the doped blocks i24a, 124b, 124c in the at least one doped layer 112a, 112b, 112c is, for example, from a portion adjacent to the drain region 16 to the adjacent channel region. The portion of the 11〇 gradient decreases, causing the degree of depletion of the 1井2 in the deep well region to decrease gradually from the adjacent bungee region 1〇6 to the adjacent channel region 11〇. As a result, the high electric field of the deep well area 1〇2 adjacent to the bungee zone 1〇6 can be greatly reduced and the deep well area 1〇2 of the adjacent channel area 11〇 can have a lower on-resistance. Therefore, the laterally diffused MOS device 1〇e has a high breakdown voltage and a low on-resistance, so that the laterally diffused MOS device 10e has good element characteristics. [Fifth Embodiment] Fig. 7 is a cross-sectional structural view showing a laterally diffused MOS device according to a fifth embodiment of the present invention. In the present embodiment, the structure of the laterally diffused MOS device i 〇 f is similar to that of the laterally diffused MOS device 10 described in the first embodiment. Hereinafter, only the main differences will be described. In the present embodiment, the doped layers 112a, 112b, 112c are located in the N-type deep well region 1〇2 between the channel region 110 and the drain region 106, and the doped layers U2a, 112b, 112C comprise a plurality of separate and The P-type doped blocks 124a, 124b, 124c form a plurality of depletion regions in the deep well region 1〇2 13 201023360 .. iwf.doc/e. In the present embodiment, the doping layers 112a, 112b, 112c are, for example, separated from each other and different from the vertical distance between the upper surface 100a of the substrate 100. Further, the doping concentrations of the doped blocks 124a, 124b, and 124c of the doped layers 112a, 1Ub, and 1Hc are, for example, the same. In the present embodiment, 'a plurality of doping layers 112a, 112b, 112c are disposed in the deep well region 1A2 having the first conductivity type, and the doping layers li2a, 112b, 112c are doped by a plurality of dopings having the second conductivity type The blocks l24a, l24b, and l24c constitute 'the gap between the deep well region 1〇2 and each of the doped blocks 124a, 124b, and 124c. Doped blocks 124a, 12,

124c可大幅增加摻雜層112a、i12b、112c與深井區ι〇·2的接觸面積， 故汲極區106與通道區11〇之間的電場能均勻地且迅速地下降。因此， 橫向擴散金氧半導體元件10f具有高崩潰電壓，使得橫向擴散金氧半 導體元件10f具有良好的元件特性。 綜上所述，本發明實施例所述之橫向擴散金氧半導體元件中，具 有第一導電型的深井區與具有第二導電型的摻雜層的介面會產生空2 區，而摻雜層的配置方式可使得橫向擴散金氧半導體元件具有高2潰 電壓與低接通電阻。故，本發明實施例所述之橫向擴散金氧半導體二 件具有良好的元件特性。此外，藉由改變摻雜層或摻雜塊的換質2 度，配置位置、尺相及數目等參數’可調紐向擴散金氧半導體= 件的朋潰電壓或接通電阻，使橫向擴散金氧半導體元件 告 元件特性。 §的 雖然本發明已以實補聽如上，並非心限定本發明 何熟習此技藝者，在不脫離本發明之精神和範圍内，當可作 =潤飾，因此本發明之保護範圍當視後附之中請專利範_界= 201023360 ,.wf.doc/e 圖式簡單說明】 圖 件的麻第—實施賴示的橫向擴散金氧半導體元 氧半導體元 圖2為依照本發明之第二實施例所繪示的横向擴散金 件的剖面構造示意圖。 ❸The 124c can greatly increase the contact area between the doped layers 112a, i12b, 112c and the deep well region ι 2, so that the electric field energy between the drain region 106 and the channel region 11 均匀 can be uniformly and rapidly decreased. Therefore, the laterally diffused MOS element 10f has a high breakdown voltage, so that the laterally diffused oxynitride semiconductor element 10f has good element characteristics. In summary, in the laterally diffused MOS device according to the embodiment of the present invention, the interface between the deep well region having the first conductivity type and the doping layer having the second conductivity type may generate a void region 2, and the doping layer The configuration can be such that the laterally diffused MOS device has a high 2 breakdown voltage and a low on resistance. Therefore, the laterally diffused MOS device according to the embodiment of the present invention has good component characteristics. In addition, by changing the degree of substitution of the doped layer or the doping block by 2 degrees, the position, the phase and the number of parameters are adjusted, and the parameters of the adjustable diffusion metal oxide semiconductor are used to make the lateral diffusion. The MOS device features component characteristics. The present invention has been described as a sequel to the above, and it is not intended to limit the invention to those skilled in the art, and the scope of protection of the present invention is attached thereto without departing from the spirit and scope of the present invention. Please refer to the patent paradigm = 201023360, .wf.doc/e for a brief description of the diagram] The schematic of the diagram - the lateral diffusion of the MOS semiconductor oligo semiconductor element Figure 2 is the second implementation in accordance with the present invention. A schematic cross-sectional view of a laterally diffused gold piece is illustrated. ❸

圖3為依照本發明之-實施例所繪示的橫向擴散 的剖面構造示意圖。 干等體兀仵 圖4為依照本發明之第三實施例所緣示的橫向換散金氧半導體元 件的剖面構造示意圖。 圖5為依照本發明之一實施例所繪示的橫向擴散金氧半導體元件 的剖面構造示意圖。 圖6為依照本發明之第四實施例所繪示的橫向擴散金氧半導體元 件的剖面構造示意圖。 圖7為依照本發明之第五實施例所繪示的橫向擴散金氧半導體元 件的剖面構造示意圖》 【主要元件符號說明】 113 :閘極 114 :閘導電層 116 :隔離結構 118 :接觸區 120 :閘介電層 122 :間隙壁 124a、124b、124c :摻雜區 10、10a、l〇b、10c、l〇d、10e、 l〇f:橫向擴散金氧半導體元件 100 :基底 100a :表面 102 :深井區 104 :井區 106 :汲極區 15 201023360twf.d〇c/e 108 :源極區 塊 110 :通道區 PI、P2 :邊緣 112、112a、112b、112c :摻雜層Figure 3 is a schematic cross-sectional view of lateral diffusion in accordance with an embodiment of the present invention. Dry Etc. Figure 4 is a cross-sectional view showing the laterally-transferred MOS device according to the third embodiment of the present invention. FIG. 5 is a cross-sectional view of a laterally diffused MOS device according to an embodiment of the invention. Fig. 6 is a cross-sectional structural view showing a laterally diffused MOS device according to a fourth embodiment of the present invention. FIG. 7 is a cross-sectional structural diagram of a laterally diffused MOS device according to a fifth embodiment of the present invention. [Main component symbol description] 113: Gate 114: Gate conductive layer 116: Isolation structure 118: Contact region 120 Gate dielectric layer 122: spacers 124a, 124b, 124c: doped regions 10, 10a, 10b, 10c, 10d, 10e, l〇f: laterally diffused MOS device 100: substrate 100a: surface 102: deep well area 104: well area 106: bungee area 15 201023360twf.d〇c/e 108: source block 110: channel area PI, P2: edge 112, 112a, 112b, 112c: doped layer

1616

Claims (1)

201023360 ^vf.doc/e 十、申請專利範圍： 1. 一種橫向擴散金氧半導體元件，包括： 一基底， 具有一第一導電型之一深井區，位於該基底中； 具有一第二導電型之—井區，位於該基底中； 具有該第一導電型之一源極區，位於該井區中； 具有該第一導電型之一没極區，位於該深井區中； 一通道區’位於該源極區與該汲極區之間的部分該井區中； * · 具有該第二導電型之多個摻雜層，位於該通道區與該汲極區之間 的該溧井區中’使形成多個空乏區域，以提高該深井區之空乏程度， 真鄰近該汲極區之該深井區相較於該深井區的其他部份具有較高的空 乏择度；以及 -閘極，位於該汲極區以及該源極區之間的該基底上並且覆蓋該201023360 ^vf.doc/e X. Patent Application Range: 1. A laterally diffused MOS device comprising: a substrate having a deep well region of a first conductivity type, located in the substrate; having a second conductivity type a well region located in the substrate; having a source region of the first conductivity type, located in the well region; having one of the first conductivity type, a pole region located in the deep well region; a channel region a portion of the well region between the source region and the drain region; * a plurality of doped layers having the second conductivity type, the well region between the channel region and the drain region Medium's formation of a plurality of depleted areas to increase the degree of depletion in the deep well area, the deep well area adjacent to the bungee area has a higher degree of vacancy than the other parts of the deep well area; and - the gate Located on the substrate between the drain region and the source region and covering the substrate 2. 如申請專利範圍第1項所述之橫向擴散金氧半導體元件， 其中该深井區中的空乏區域的數目由鄰近該汲極區之該深井區往鄰近 ^ 该通道區之該深井區遞減。 3. 如申請專利範圍第1項所述之橫向擴散金氧半導體元件， 其中#一該些摻雜層與該基底之上表面之間的垂直距離不同。 4·如申請專利範圍第1項所述之橫向擴散金氧半導體元件， 其中該些摻雜層的摻質濃度相同。 5- 如申請專利範圍第1項所述之橫向擴散金氧半導體元件， 其中I一該摻雜層包括多個摻雜區塊。 6- 如申睛專利範圍第5項所述之橫向擴散金氡半導體元件， 17 201023360 wf.doc/e 其中該些摻雜區塊的摻質濃度相同。 7. 如申請專利範圍第Μ所述之橫向擴散金氧半導體元件， 其中該基底為具有該第二導電型之基底。 8. 如申請專利範圍第！項所述之橫向擴散金氧半導體元件， 其中該第一導電型為Ρ型，該第二導電型為Ν型。 9. 如申請專利範圍第i項所述之橫向擴散金氧半導體元件， 其中該第一導電型為N型，該第二導電型為ρ型。 10. 一種橫向擴散金氧半導體元件，包括：2. The laterally diffused MOS device according to claim 1, wherein the number of depleted regions in the deep well region is decreased from the deep well region adjacent to the bungee region to the deep well region adjacent to the channel region . 3. The laterally diffused MOS device according to claim 1, wherein #1 the doping layer has a different vertical distance from the upper surface of the substrate. 4. The laterally diffused MOS device according to claim 1, wherein the dopant layers have the same dopant concentration. 5. The laterally diffused MOS device of claim 1, wherein the one doped layer comprises a plurality of doped blocks. 6- The laterally diffused gold-germanium semiconductor component according to item 5 of the scope of the patent application, 17 201023360 wf.doc/e wherein the dopant concentrations of the doped blocks are the same. 7. The laterally diffused MOS device according to claim </RTI> wherein the substrate is a substrate having the second conductivity type. 8. If you apply for a patent scope! The laterally diffused MOS device according to the invention, wherein the first conductivity type is a Ρ type, and the second conductivity type is a Ν type. 9. The laterally diffused MOS device of claim i, wherein the first conductivity type is an N type and the second conductivity type is a p type. 10. A laterally diffused MOS device comprising: 一基底； 具有一第一導電型之一深井區，位於該基底中； 具有一第二導電型之一井區，位於該基底中； 具有該第一導電型之一源極區，位於該井區中； 具有該第一導電型之一汲極區，位於該深井區中； 一通道區’位於該源極區與該汲極區之間的部分該井區中； 具有該第二導電型之至少一摻雜層’位於該通道區與該汲極區之 間的該深井區中’使形成至少一空乏區域，以提高該深井區之空乏程 度，且鄰近該汲極區之該至少一摻雜層具有較高的摻質濃度，使鄰近 该淚極區之該深井區相較於該深井區的其他部份具有較高的空乏程 度；以及 一閘極’位於該没極區以及該源極區之間的該基底上並且覆蓋該 通道區。 11.如申請專利範圍第10項所述之橫向擴散金氧半導體元件， 其中該至少一摻雜層的摻質濃度由鄰近該没極區之該深井區往鄰近該 通道區之該深井區遞減。 201023360 twf.doc/e α如t料鄕圍第1G顧述讀向錢半導體元 件，其中該至少一摻雜層包括多個摻雜區塊。 I3·如申請專利範圍第I2項所述之橫向擴散金氧半導體元件， 其中該些摻雜區塊的摻質濃度隨著其所在位置接近該通道區而下降。 M.如申請專利範圍第10項所述之橫向擴散金氧半導體元件， 其中該基底為具有該第二導電型之基底。 15. 如申凊專利範圍第1〇項所述之橫向擴散金氧半導體元件， 其中該第一導電型為P型，該第二導電型為N型。 16. 如申請專利範圍第10項所述之橫向擴散金氧半導體元件， 其中該第一導電型為N型，該第二導電型為p型。 17. —種橫向擴散金氧半導體元件，包括： 一基底； 具有一第一導電型之一深井區，位於該基底中； 具有一第二導電型之一井區，位於該基底中； 具有該第一導電型之一源極區，位於該井區中； 具有該第—導電型之一汲極區，位於該深井區中； 一通道區’位於該源極區與該汲極區之間的部分該井區中； 具有該第二導電型之多個掺雜層，位於該通道區與該没極區之間 的该深井區中，各該摻雜層包括多個彼此分離的摻雜區塊，使形成多 摘变乏區域；以及 一閘極’位於該汲極區以及該源極區之間的該基底上並且覆蓋該 通遘區。 18. 如申請專利範圍第17項所述之橫向擴散金氧半導體元件， 其中每一該些摻雜層與該基底之上表面之間的垂直距離不同。 19 201023360— 19. 如申請專利範圍第17項所述之橫向擴散金氧半導體元件， 其中同一摻雜層中的該些摻雜區塊的摻質濃度相同。 20. 如申請專利範圍第17項所述之橫向擴散金氧半導體元件， 其中該基底為具有該第二導電型之基底。 21. 如申請專利範圍第17項所述之橫向擴散金氧半導體元件， 其中該第一導電型為P型，該第二導電型為N型。 22. 如申請專利範圍第17項所述之橫向擴散金氧半導體元件， 其中該第一導電型為N型，該第二導電型為P型。a substrate; a deep well region having a first conductivity type, located in the substrate; having a well region of a second conductivity type, located in the substrate; having a source region of the first conductivity type, located in the well a region having one of the first conductivity types, located in the deep well region; a channel region being located in a portion of the well region between the source region and the drain region; having the second conductivity type At least one doping layer 'in the deep well region between the channel region and the drain region' causes at least one depletion region to be formed to increase the degree of depletion of the deep well region, and the at least one adjacent to the bungee region The doped layer has a higher dopant concentration such that the deep well region adjacent to the tear region has a higher degree of depletion than the other portions of the deep well region; and a gate is located in the non-polar region and The substrate between the source regions covers the channel region. 11. The laterally diffused MOS device of claim 10, wherein a dopant concentration of the at least one doped layer is decreased from the deep well region adjacent to the non-polar region to the deep well region adjacent to the channel region . 201023360 twf.doc/e α, as described in the first section, the first semiconductor component, wherein the at least one doped layer comprises a plurality of doped blocks. I3. The laterally diffused MOS device of claim 1, wherein the doping concentration of the doped regions decreases as the location thereof approaches the channel region. The laterally diffused MOS device according to claim 10, wherein the substrate is a substrate having the second conductivity type. 15. The laterally diffused MOS device of claim 1, wherein the first conductivity type is a P type and the second conductivity type is an N type. 16. The laterally diffused MOS device of claim 10, wherein the first conductivity type is an N type and the second conductivity type is a p type. 17. A laterally diffused MOS device, comprising: a substrate; a deep well region having a first conductivity type, located in the substrate; having a well region of a second conductivity type, located in the substrate; a source region of the first conductivity type, located in the well region; having one of the first conductivity type drain regions located in the deep well region; a channel region 'between the source region and the drain region a portion of the well region; a plurality of doped layers having the second conductivity type, located in the deep well region between the channel region and the non-polar region, each doped layer comprising a plurality of doped layers separated from each other The block is configured to form a plurality of stripped regions; and a gate is located on the substrate between the drain region and the source region and covers the overnight region. 18. The laterally diffused MOS device of claim 17, wherein a vertical distance between each of the doped layers and an upper surface of the substrate is different. 19. The laterally diffused MOS device of claim 17, wherein the doped regions of the same doped layer have the same dopant concentration. 20. The laterally diffused MOS device of claim 17, wherein the substrate is a substrate having the second conductivity type. 21. The laterally diffused MOS device of claim 17, wherein the first conductivity type is a P type and the second conductivity type is an N type. 22. The laterally diffused MOS device of claim 17, wherein the first conductivity type is an N type and the second conductivity type is a P type. 2020
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8592901B1 (en) 2012-08-31 2013-11-26 Nuvoton Technology Corporation Metal oxide semiconductor field transistor and method of fabricating the same
TWI557904B (en) * 2015-03-17 2016-11-11 世界先進積體電路股份有限公司 Semiconductor device and method for fabricating the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8592901B1 (en) 2012-08-31 2013-11-26 Nuvoton Technology Corporation Metal oxide semiconductor field transistor and method of fabricating the same
TWI557904B (en) * 2015-03-17 2016-11-11 世界先進積體電路股份有限公司 Semiconductor device and method for fabricating the same

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