CN115632062A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN115632062A CN115632062A CN202211644878.XA CN202211644878A CN115632062A CN 115632062 A CN115632062 A CN 115632062A CN 202211644878 A CN202211644878 A CN 202211644878A CN 115632062 A CN115632062 A CN 115632062A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/404—Multiple field plate structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7823—Lateral DMOS transistors, i.e. LDMOS transistors with an edge termination structure
Abstract
The application discloses a semiconductor device and a manufacturing method thereof. The substrate is internally provided with a channel region, a source region, a drain region, a drift region and a first shallow trench isolation structure, wherein the source region is positioned in the channel region, the drain region is positioned in the drift region, and the drift region is positioned between the channel region and the first shallow trench isolation structure; the grid structure covers part of the channel region and part of the drift region; the dielectric layer covers the substrate and the grid structure, a first contact hole, a second contact hole and a third contact hole are formed in the dielectric layer, the first contact hole is connected with the drain region, the second contact hole is connected with the grid structure, and the third contact hole penetrates through the source region and is connected with the channel region. The scheme can reduce the on-resistance of the semiconductor device on the premise of keeping the breakdown voltage of the semiconductor device.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a semiconductor device and a method for manufacturing the same.
Background
A power device with better performance generally requires higher breakdown voltage and lower characteristic on-resistance at the same time, but in the actual device optimization process, it is found that two parameters cannot be optimized at the same time, because in a Lateral Double-diffusion Metal Oxide Semiconductor (LDMOS), the doping concentration of a drift region is increased, the on-resistance can be effectively reduced, but the breakdown voltage is also reduced; increasing the length of the drift region can effectively increase the breakdown voltage, but can increase the on-resistance and increase the size of a single device.
Disclosure of Invention
The application provides a semiconductor device and a manufacturing method thereof, which can reduce the on-resistance of the semiconductor device on the premise of keeping the breakdown voltage of the semiconductor device.
In a first aspect, the present application provides a semiconductor device comprising:
the transistor comprises a substrate, wherein a channel region, a source region, a drain region, a drift region and a first shallow trench isolation structure are arranged in the substrate, the source region is positioned in the channel region, the drain region is positioned in the drift region, and the drift region is positioned between the channel region and the first shallow trench isolation structure;
the gate structure covers part of the channel region and part of the drift region;
the dielectric layer covers the substrate and the grid structure, a first contact hole, a second contact hole and a third contact hole are formed in the dielectric layer, the first contact hole is connected with the drain region, the second contact hole is connected with the grid structure, and the third contact hole penetrates through the source region and is connected with the channel region.
In the semiconductor device provided by the present application, further comprising:
a field plate located on one side of the gate structure and on the drift region;
and the second shallow trench isolation structure is positioned in the drift region and is connected with the field plate and the grid structure.
In the semiconductor device provided by the application, the material of the gate structure is the same as that of the field plate.
In the semiconductor device provided by the application, the field plate comprises a plurality of sub-field plates which are arranged at equal intervals.
In the semiconductor device provided by the present application, further comprising:
the first metal layer is connected with the drain region through the first contact hole, the second metal layer is connected with the grid structure through the second contact hole, and the third metal layer is respectively connected with the source region and the channel region through the third contact hole.
In the semiconductor device provided by the application, the base is a semiconductor substrate, and the channel region, the source region, the drain region, the drift region and the first shallow trench isolation structure are all arranged in the semiconductor substrate.
In the semiconductor device provided by the application, the base comprises a semiconductor substrate, a buried layer and an epitaxial layer which are sequentially stacked from bottom to top, and the channel region, the source region, the drain region, the drift region and the first shallow slot isolation structure are all arranged in the epitaxial layer.
In the semiconductor device provided by the present application, the buried layer has a first conductivity type, and the epitaxial layer has a second conductivity type.
In the semiconductor device provided by the present application, the first conductivity type is a P type, and the second conductivity type is an N type; or the first conduction type is N type, and the second conduction type is P type.
In a second aspect, the present application provides a method of manufacturing a semiconductor device, with which any one of the above-described semiconductor devices is manufactured, the method comprising:
providing a substrate, wherein a channel region, a source region, a drain region, a drift region and a first shallow trench isolation structure are arranged in the substrate, the source region is positioned in the channel region, the drain region is positioned in the drift region, and the drift region is positioned between the channel region and the first shallow trench isolation structure;
forming a gate structure covering a part of the channel region and a part of the drift region;
and forming a dielectric layer covering the substrate and the grid structure, wherein the dielectric layer is provided with a first contact hole, a second contact hole and a third contact hole, the first contact hole is connected with the drain region, the second contact hole is connected with the grid structure, and the third contact hole penetrates through the source region and is connected with the channel region.
In summary, the semiconductor device provided by the present application includes a substrate, a gate structure and a dielectric layer. The substrate is internally provided with a channel region, a source region, a drain region, a drift region and a first shallow trench isolation structure, wherein the source region is positioned in the channel region, the drain region is positioned in the drift region, and the drift region is positioned between the channel region and the first shallow trench isolation structure; the gate structure covers part of the channel region and part of the drift region; the dielectric layer covers the substrate and the grid structure, a first contact hole, a second contact hole and a third contact hole are formed in the dielectric layer, the first contact hole is connected with the drain region, the second contact hole is connected with the grid structure, and the third contact hole penetrates through the source region and is connected with the channel region. According to the scheme, the third contact hole penetrates through the source region and is connected with the channel region, so that the transverse size of the semiconductor device is reduced, and the on-resistance of the semiconductor device can be reduced on the premise of keeping the breakdown voltage of the semiconductor device.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a conventional LDMOS device.
Fig. 2 is a schematic structural diagram of a semiconductor device provided in an embodiment of the present application.
Fig. 3 is another schematic structural diagram of a semiconductor device provided in an embodiment of the present application.
Fig. 4 is a schematic view of another structure of a semiconductor device provided in an embodiment of the present application.
Fig. 5 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present application.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings in which the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the recitation of a claim "comprising a" 8230a "\8230means" does not exclude the presence of additional identical elements in the process, method, article or apparatus in which the element is incorporated, and further, similarly named components, features, elements in different embodiments of the application may have the same meaning or may have different meanings, the specific meaning of which should be determined by its interpretation in the specific embodiment or by further combination with the context of the specific embodiment.
It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
In the following description, suffixes such as "module", "component", or "unit" used to denote elements are used only for the convenience of description of the present application, and have no specific meaning in themselves. Thus, "module", "component" or "unit" may be used mixedly.
In the description of the present application, it should be noted that the terms "upper", "lower", "left", "right", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
A power device with better performance generally requires higher breakdown voltage and lower characteristic on-resistance at the same time, but in the actual device optimization process, it is found that two parameters cannot be optimized at the same time, because in the LDMOS, the concentration of doping in a drift region is increased, the on-resistance can be effectively reduced, but the breakdown voltage is also reduced; increasing the length of the drift region can effectively increase the breakdown voltage, but can increase the on-resistance and increase the size of a single device.
Based on this, embodiments of the present application provide a semiconductor device and a method for manufacturing the same, and the technical solutions shown in the present application will be described in detail through specific embodiments below. It should be noted that the description sequence of the following embodiments is not intended to limit the priority sequence of the embodiments.
In the conventional LDMOS, as shown in fig. 1, a channel region 110, a source region 120, a drain region 130, a drift region 140, and a shallow trench isolation structure 150 are disposed in a substrate 100, the source region 120 is located in the channel region 110, the drain region 130 is located in the drift region 140, and the drift region 140 is located between the channel region 110 and the first shallow trench isolation structure 150; the gate structure 200 covers a part of the channel region 110 and a part of the drift region 140; the dielectric layer 300 covers the substrate 100 and the gate structure 200, the dielectric layer 300 has a first contact hole 410, a second contact hole 420 and a third contact hole 430, the first contact hole 410 is connected with the drain region 130, the second contact hole 420 is connected with the gate structure 200, the third contact hole 430 includes two first sub-contact holes 431 and one second sub-contact hole 432, the two first sub-contact holes 431 are connected with the channel region 110, and the second sub-contact hole 432 is connected with the source region 120.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a semiconductor device according to an embodiment of the present disclosure. The semiconductor device may include a substrate 10, a gate structure 20, and a dielectric layer 30. The substrate 10 is internally provided with a channel region 11, a source region 12, a drain region 13, a drift region 14 and a first shallow trench isolation structure 15, wherein the source region 12 is positioned in the channel region 11, the drain region 13 is positioned in the drift region 14, and the drift region 14 is positioned between the channel region 11 and the first shallow trench isolation structure 15; the gate structure 20 covers part of the channel region 11 and part of the drift region 14; the dielectric layer 30 covers the substrate 10 and the gate structure 20, the dielectric layer 30 is provided with a first contact hole 41, a second contact hole 42 and a third contact hole 43, the first contact hole 41 is connected with the drain region 13, the second contact hole 42 is connected with the gate structure 20, and the third contact hole 43 penetrates through the source region 12 and is connected with the channel region 11.
Thus, the present embodiment can reduce the lateral size of the semiconductor device by providing the third contact hole 43 to connect with the channel region 11 through the source region 12.
Because the length of the drift region of the device is one of the key factors determining the size of the on-resistance (Ron), the on-resistance is generally inversely proportional to the area of the chip, the larger the chip size is, although the on-resistance can be made very small, the area is increased, the manufacturing cost of the process is increased, and therefore, the on-characteristic of the device cannot be completely represented by the single Ron. In recent years, a concept of a characteristic on-resistance (Ron, sp) has been proposed, which comprehensively considers two factors of resistance and area, and is generally defined as:
where Vd is the breakdown voltage, idlin is the drain current, W is the active area width, L pitch Is the step size of the device.
Therefore, the third contact hole 43 is arranged to penetrate through the source region 12 to be connected with the channel region 11, so that the lateral size of the semiconductor device can be reduced, the step size of the semiconductor device can also be reduced, and the characteristic on-resistance of the semiconductor device is reduced. That is, the embodiment of the present application provides a semiconductor device that can reduce the on-resistance of the semiconductor device while maintaining the breakdown voltage of the semiconductor device.
In some embodiments, as shown in fig. 3, the semiconductor device may further include a field plate 50 and a second shallow trench isolation structure 16. Wherein the field plate 50 is located on one side of the gate structure 20 and on the drift region 14; a second shallow trench isolation structure 16 is located in the drift region 14, the second shallow trench isolation structure 16 connecting the field plate 50 and the gate structure 20.
It should be noted that the field plate 50 includes several sub-field plates 51 arranged at equal intervals. The gate structure 20 is made of the same material as the field plate 50 and is polysilicon, so that the gate structure 20 can be coupled to the field plate 50 through the second shallow trench isolation structure 16. Several sub-field plates 51 may also be coupled to each other by the second shallow trench isolation structure 16.
When the semiconductor device works, in the process that electrons flow from the source region 12 to the drain region 13, an electric field peak value is formed in a region corresponding to the field plate 50 of the drift region 14, so that the electric field peak value of the drain region 13 is reduced, and the breakdown voltage of the semiconductor device is improved. In the embodiment of the present invention, in order to further reduce the electric field peak of the drain region 13, the plurality of sub-field plates 51 are disposed on the first shallow trench isolation structure 15 and are distributed at equal intervals, so that a plurality of electric field peaks are formed in the drift region 14 when the semiconductor device is in operation, and further, the electric field peak of the drain region 13 is further reduced, and the breakdown voltage of the semiconductor device is improved.
It is understood that, in the case where the lengths of the drift region 14 and the first shallow trench isolation structure 15 are fixed, the larger the number of electric field peaks in the drift region 14 is, the smaller the electric field peak in the drain region 13 is, that is, the number of electric field peaks in the drift region 14 is related to the breakdown voltage of the semiconductor device. The larger the number of sub-field plates 51, the larger the number of electric field peaks. And the smaller the width and pitch of the sub-field panels 51, the larger the number of sub-field panels 51 that can be provided. Therefore, in some embodiments, the breakdown voltage of the semiconductor device can be adjusted by adjusting the number of sub-field plates 51, the spacing between adjacent sub-field plates 51, and the width of the sub-field plates 51. Experiments prove that the maximum voltage withstanding value of about 30% can be increased on the basis of keeping the length of the drift region 14 of the original traditional structure.
The length refers to a dimension of the source region 12 in a direction toward the drain region 13.
In some embodiments, the base 10 is a semiconductor substrate. At this time, the channel region 11, the source region 12, the drain region 13, the drift region 14, the first shallow trench isolation structure 15, and the second shallow trench isolation structure 16 are all located in the semiconductor substrate.
In another embodiment, the base 10 may include a semiconductor substrate, a buried layer, and an epitaxial layer. The buried layer and the epitaxial layer are sequentially stacked on the semiconductor substrate from bottom to top. At this time, the channel region 11, the source region 12, the drain region 13, the drift region 14, the first shallow trench isolation structure 15, and the second shallow trench isolation structure 16 are all located within the epitaxial layer.
In the embodiment of the present application, the channel region 11 may be a first conductivity type channel region 11, the drift region 14 may be a second conductivity type drift region 14, the source region 12 may be a second conductivity type source region, the drain region may be a second conductivity type drain region, the buried layer may be a first conductivity type buried layer, and the epitaxial layer may be a second conductivity type epitaxial layer. It should be noted that the first conductivity type is P-type, and the second conductivity type is N-type; or the first conductive type is N type, and the second conductive type is P type.
In a specific implementation, the buried layer may be formed by ion implantation of the first conductivity type into the upper surface layer of the semiconductor substrate. For example, sb ion implantation may be performed on the upper surface of the semiconductor substrate to obtain a buried layer. The epitaxial layer may be formed by a variety of methods, such as physical vapor deposition, chemical vapor deposition, or other suitable methods. The channel region 11, the source region 12, the drain region 13 and the drift region 14 can be formed by ion implantation, and are not described in detail herein.
The material of the semiconductor substrate may be single crystal silicon, silicon carbide, gallium arsenide, indium phosphide, silicon germanium or the like, the material of the semiconductor substrate may be silicon germanium, a group iii-v element compound, silicon carbide, a stacked structure thereof, a silicon-on-insulator structure, a diamond substrate, or another semiconductor material substrate known to those skilled in the art, for example, a semiconductor substrate in which P atoms are implanted into single crystal silicon to form N-type conductivity, or a semiconductor substrate in which B atoms are implanted into single crystal silicon to form P-type conductivity. In the embodiment of the present application, the semiconductor substrate is a silicon substrate.
In some embodiments, as shown in fig. 4, the semiconductor device may further include a first metal layer 61, a second metal layer 62 and a third metal layer 63 disposed on the dielectric layer 30, the first metal layer 61 is connected to the drain region 13 through a first contact hole 41, the second metal layer 62 is connected to the gate structure 20 through a second contact hole 42, and the third metal layer 63 is connected to the source region 12 and the channel region 11 through a third contact hole 43, respectively.
In the embodiment of the present application, the material filled in the first contact hole 41, the second contact hole 42, and the third contact hole 43 may include at least one of Ti, tiN, ag, au, cu, al, W, ni, zn, and Pt, and may be other suitable conductive materials.
In summary, the semiconductor device provided in the present application includes a substrate 10, a gate structure 20, and a dielectric layer 30. The substrate 10 is internally provided with a channel region 11, a source region 12, a drain region 13, a drift region 14 and a first shallow trench isolation structure 15, wherein the source region 12 is positioned in the channel region 11, the drain region 13 is positioned in the drift region 14, and the drift region 14 is positioned between the channel region 11 and the first shallow trench isolation structure 15; the gate structure 20 covers part of the channel region 11 and part of the drift region 14; the dielectric layer 30 covers the substrate 10 and the gate structure 20, the dielectric layer 30 is provided with a first contact hole 41, a second contact hole 42 and a third contact hole 43, the first contact hole 41 is connected with the drain region 13, the second contact hole 42 is connected with the gate structure 20, and the third contact hole 43 penetrates through the source region 12 and is connected with the channel region 11. According to the scheme, the third contact hole 43 penetrates through the source region 12 to be connected with the channel region 11, so that the transverse size of the semiconductor device is reduced, and the on-resistance of the semiconductor device can be reduced on the premise of keeping the breakdown voltage of the semiconductor device.
Referring to fig. 5, fig. 5 is a schematic flow chart illustrating a method for manufacturing a semiconductor device according to the present application. The manufacturing method of the semiconductor device may specifically be as follows:
101. providing a substrate, wherein a channel region 11, a source region 12, a drain region 13, a drift region 14 and a first shallow trench isolation structure 15 are arranged in the substrate 10, the source region 12 is positioned in the channel region 11, the drain region 13 is positioned in the drift region 14, and the drift region 14 is positioned between the channel region 11 and the first shallow trench isolation structure 15;
102. forming a gate structure 20 covering part of the channel region 11 and part of the drift region 14;
103. and forming a dielectric layer 30 covering the substrate 10 and the gate structure 20, wherein the dielectric layer 30 is provided with a first contact hole 41, a second contact hole 42 and a third contact hole 43, the first contact hole 41 is connected with the drain region 13, the second contact hole 42 is connected with the gate structure 20, and the third contact hole 43 penetrates through the source region 12 to be connected with the channel region 11.
According to the embodiment of the application, the third contact hole 43 is arranged to penetrate through the source region 12 to be connected with the channel region 11, so that the lateral size of the semiconductor device can be reduced, the step size of the semiconductor device is also reduced, and the characteristic on-resistance of the semiconductor device is reduced. That is, the embodiment of the present application provides a semiconductor device that can reduce the on-resistance of the semiconductor device while maintaining the breakdown voltage of the semiconductor device.
Note that the noun in this embodiment has the same meaning as that in the above-described semiconductor device embodiment, and specific implementation details can be referred to the description in the above-described semiconductor device embodiment.
The semiconductor device and the manufacturing method thereof provided by the present application are described in detail above, and the principles and embodiments of the present application are explained herein by applying specific examples, which are only used to help understand the core idea of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. A semiconductor device, comprising:
the transistor comprises a substrate, wherein a channel region, a source region, a drain region, a drift region and a first shallow trench isolation structure are arranged in the substrate, the source region is positioned in the channel region, the drain region is positioned in the drift region, and the drift region is positioned between the channel region and the first shallow trench isolation structure;
the gate structure covers part of the channel region and part of the drift region;
the dielectric layer covers the substrate and the grid structure, a first contact hole, a second contact hole and a third contact hole are formed in the dielectric layer, the first contact hole is connected with the drain region, the second contact hole is connected with the grid structure, and the third contact hole penetrates through the source region and is connected with the channel region.
2. The semiconductor device according to claim 1, further comprising:
a field plate located on one side of the gate structure and on the drift region;
and the second shallow trench isolation structure is positioned in the drift region and is connected with the field plate and the grid structure.
3. The semiconductor device of claim 2, in which a material of the gate structure is the same as a material of the field plate.
4. The semiconductor device of claim 2, wherein the field plate comprises a plurality of equally spaced sub-field plates.
5. The semiconductor device according to claim 1, further comprising:
the first metal layer is connected with the drain region through the first contact hole, the second metal layer is connected with the grid structure through the second contact hole, and the third metal layer is respectively connected with the source region and the channel region through the third contact hole.
6. The semiconductor device of claim 1, wherein the base is a semiconductor substrate, and the channel region, the source region, the drain region, the drift region, and the first shallow trench isolation structure are all disposed within the semiconductor substrate.
7. The semiconductor device according to claim 1, wherein the base includes a semiconductor substrate, a buried layer, and an epitaxial layer stacked in this order from bottom to top, and the channel region, the source region, the drain region, the drift region, and the first shallow trench isolation structure are all disposed in the epitaxial layer.
8. The semiconductor device of claim 7, wherein the buried layer has a first conductivity type and the epitaxial layer has a second conductivity type.
9. The semiconductor device according to claim 8, wherein the first conductivity type is a P-type, and the second conductivity type is an N-type; or the first conduction type is N type, and the second conduction type is P type.
10. A method for manufacturing a semiconductor device, characterized in that the semiconductor device according to any one of claims 1 to 9 is manufactured by the method for manufacturing a semiconductor device, comprising:
providing a substrate, wherein a channel region, a source region, a drain region, a drift region and a first shallow trench isolation structure are arranged in the substrate, the source region is positioned in the channel region, the drain region is positioned in the drift region, and the drift region is positioned between the channel region and the first shallow trench isolation structure;
forming a gate structure covering a part of the channel region and a part of the drift region;
and forming a dielectric layer covering the substrate and the grid structure, wherein the dielectric layer is provided with a first contact hole, a second contact hole and a third contact hole, the first contact hole is connected with the drain region, the second contact hole is connected with the grid structure, and the third contact hole penetrates through the source region and is connected with the channel region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211644878.XA CN115632062A (en) | 2022-12-21 | 2022-12-21 | Semiconductor device and method for manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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