TW201023359A - Semiconductor structure and method of fabricating the same - Google Patents

Abstract

A semiconductor structure including a substrate, a gate dielectric layer, a gate, a source region and a drain region is provided. The gate dielectric layer is disposed on the substrate. At least one recess is disposed in the substrate. The gate is disposed on the gate dielectric layer and in the recess. The source and drain regions are respectively disposed in the substrate beside the gate.

Description

124 29322 twf.doc/n 201023359 IX. Description of the Invention: [Technical Field] The present invention relates to an integrated circuit and a method of fabricating the same, and more particularly to a semiconductor structure and a method of fabricating the same. [Prior Art] As the degree of integration of semiconductor elements increases, the size of semiconductor elements also shrinks. Therefore, the size of each member such as a current divider in the semiconductor element must also be correspondingly reduced. The conventional shunt is to achieve the purpose of shunting by using a polysilicon layer and a metal layer in a serpentine configuration. However, the polycrystalline layer and the metal layer of this method occupy a considerable area, and therefore, the size of the semiconductor element cannot be reduced. In addition, the process of forming the shunt is often not integrated with the existing process, thereby increasing the complexity of the process and the manufacturing cost is also high. . Therefore, how to disregard a shunt that is small in size and compatible with existing processes has become one of the topics that the industry attaches great importance to. [Summary of the Invention]

The invention provides a shunt for a semiconductor junction size of a semiconductor structure as a shunt, which is also low in cost and excellent in reliability. ‘It includes the substrate, gate dielectric 201023359 —^38-0124 29322twf.doc/n layer, gate, source region and bungee region. The gate dielectric layer is disposed on the substrate. At least one recess is disposed in the substrate. The gate is disposed on the gate dielectric layer and in the recess. The source region and the drain region are respectively disposed in the substrate on both sides of the gate. According to an embodiment of the invention, in an operation, an inversion layer or an accumulation layer is formed between the gate dielectric layer and the substrate, so that the gate current is divided into the source region along the inversion layer or the accumulation layer. The source current and the 汲·pole current flowing to the drain region. According to an embodiment of the invention, when the shortest distance between the at least one quad and the source region is L1, and the shortest distance between at least one of the recess and the drain region is L2, the source current is proportional to L2/ (L1+L2), the drain current is proportional to L1/(L1+L2). According to an embodiment of the invention, the semiconductor structure further includes a dielectric layer disposed on a surface of the recess. According to an embodiment of the invention, the dielectric layer is not disposed on the surface of the recess. The semiconductor structure described above further includes a well region disposed in the substrate in accordance with an embodiment of the present invention. According to an embodiment of the invention, the material of the substrate comprises a material according to an embodiment of the invention, wherein the material of the gate dielectric layer is in accordance with the embodiment of the invention, and the gate is Materials include 曰 曰, polycrystalline bismuth metal, metal bismuth or metal. The present invention further provides a method of forming a semiconductor structure. First, a gate dielectric layer is formed on the substrate of 201023359~08-0124 29322twf.doc/n. Then, at least one depression is formed in the substrate. Next, a gate is formed on the gate dielectric layer and in the recess. Thereafter, a source region and a drain region are formed in the substrates on both sides of the gate. According to an embodiment of the invention, in an operation, an inversion layer or an accumulation layer is formed between the gate dielectric layer and the substrate, so that the gate current is divided into the source region along the inversion layer or the accumulation layer. The source current and the immersion current flowing to the drain region. According to an embodiment of the invention, 'when the shortest distance between at least one recess and the source region is L1, and the shortest distance between at least one recess and the drain region is L2, the source current is proportional to L2/( L1+L2), the drain current is proportional to L1/(L1+L2). According to an embodiment of the invention, the step of forming the gate dielectric layer is preceded by the step of forming at least one recess. According to an embodiment of the invention, the step of forming the gate dielectric layer is performed after the step of forming at least one recess. According to an embodiment of the invention, the method of forming the gate dielectric layer includes performing a slitting or chemical vapor deposition process. In accordance with an embodiment of the present invention, the method includes performing a residual process. According to an embodiment of the invention, Shi Xi. According to an embodiment of the invention, including oxidized stone. According to the embodiment of the present invention, the material for forming the at least one recessed substrate comprises the material of the gate dielectric layer, and the material of the gate includes 201023359 ^xv^-.v〇8- 〇l24 29322twf.doc/n polycrystalline stone ^, polycrystalline Wei metal, gold chemical or metal. In summary, the semiconductor in the present invention is formed, which is recessed on the substrate towel and is not on the surface of the depression. Configuring the dielectric layer ^ == current shunting as the source current and the immersion current 2 and the existing process integration, reducing the complexity of the process: ❹ In addition, in the semiconductor structure of the present invention, the use of the towel == trap The surface of the recess is provided with a dielectric layer 'which can be used as a single burn: can be owed == there is no unexpected phenomenon of burnout points: In order to make the above features and advantages of the present invention more obvious, the following is preferred.实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 > Partial top view. Eight please refer to Figure 1 and Figure 2, semiconductor The structure just includes the substrate 1, 2, the "electric layer 104, the gate 106, the source region 108 and the drain region 11". The substrate ι〇2 4 J is a ruthenium-based or p-type substrate, or a substrate having a conductivity different from that of the substrate (not shown). The material of the substrate 1〇2 includes germanium, for example, germanium single crystal germanium, epitaxial germanium, polycrystalline germanium, germanium germanium or tantalum carbide, and the like. Substrate 102 has an active region 101. The gate dielectric layer 1〇4 is disposed on the substrate 102 of the active region. The material of the gate dielectric layer 1〇4 is, for example, hafnium oxide. In addition, to 201023359 i_»iviv^u-z.\/\)8-0124 29322twf.doc/n Less than one Π2 is placed in the substrate 1〇2.

The gate 106 is disposed on the gate dielectric layer ι 4 and in the recess 112. The material of the gate 106 is, for example, polycrystalline germanium, polycrystalline germanium, metal silicide or metal. In an embodiment, the spacers 116 may also be selectively disposed on the sidewalls of the gates 1〇6. The source regions ι 8 and / and the polar regions 110 are respectively disposed in the substrate 1 〇 2 on both sides of the gate. The source region 108 includes a lightly doped region ι 7 and a heavily doped region m, and the source region n 包括 includes a lightly doped region 109 and a heavily doped region 113. The source region 1 〇 8 and the drain region 110 are, for example, N-type doped regions or p-type doped regions. Under an operation 'e.g., when the voltage applied to the gate 1 〇 6 is higher than the voltage applied to the substrate 102, the source region 1 〇 8 and the drain region no, the electron-rich inversion layer 114 Formed between the gate dielectric layer 1〇4 and the substrate 102, such that the gate current 1(} is divided along the inversion layer 114 into the source current is flowing to the source region 108 and the drain flowing to the drain region u〇 Current

Id. The magnitude of the source current Is and the infinite current iD conform to the following formula:

Is ~IgxL2/(L1+L2) (1)

Id ~ IgxL1/(L1 + L2) (2) wherein the shortest distance between the recess 112 and the source region 1 〇 8 is Lb The shortest distance between the recess 112 and the drain region 11 为 is L2. It can be seen from the formula (〇 and equation (2) that the source current is proportional to L2/(L1+L2), and the infinite current ID is proportional to L1/(L1+L2). Therefore, in the semiconductor structure With the recess 112 disposed in the substrate 1〇2, under appropriate operating conditions, the current path can be divided into two, and the gate current Ig is shunted to the source 9 201023359 ^Ανι^-ώυ08-0124 29322twf .doc/n current Is and the purpose of immersing current. That is, the semiconductor structure 1 of the present invention can be used as a shunt, and the inversion layer 114 can be used as a resistor to adjust the width and position of the recess 112 and The voltage applied to the interpole 1〇6, the substrate 1〇2, the source region 108 and the drain region 11〇 can change the magnitude of the source current secret current ID. In particular, the 'invention of the present invention is used. The semiconductor structure of the shunt/the known structure of the metal oxide semiconductor (Mos) is so close that the manufacturing method 髻I is integrated with the existing process to reduce the complexity of the process and greatly reduce the composition. On the other hand, the present invention only needs to be At least one recess can be arranged in the substrate to achieve the purpose of splitting, without the need for layout The polycrystalline stone and the metal layer having a serpentine size are thus the rule of the semiconductor structure used as the shunt of the present invention, which can reduce the degree of integration and performance of the 'lifting element. In the above embodiment, it is a The recess U2 is disposed on the substrate 1〇2: as an example, but the invention is not limited. In other words, the present invention does not limit the number of recesses. For example, as shown in FIG. 3 and FIG. 4, 鬌When the recesses 112a, 112b, U2c are disposed in the substrate 1〇2, the shortest distance between the recesses 112a, 112b, 112c and the source region 1〇8 is u, and between the pits 1Ua and the source regions 1〇8 The distance between the recesses (10), llh and 'and the pole region 11〇 is L2, that is, the distance between the recess fc and the pole region 11〇. The semiconductor structure of FIGS. 3 and 4 is also turned over by the formula. (1) and formula (7), by adjusting the width and position of the recesses 2a 112b, 112c and the voltages applied to the gate 1〇6, the source region 108 and the drain region 110, thereby changing the source current Is and 汲The magnitude of the pole current iD. 201023359 «...—J8-0124 29322twf.doc/n In addition, in Figures 1 to 4 In the embodiment, the shape of the recess is a strip shape and the width thereof is the same as the width of the active region 101, which is W, but the invention is not limited thereto. In another embodiment, the shape of the recess may be Any shape 'and the width of the recess may be smaller than the width of the active region 1〇1, as shown by the elliptical recess U2d of Fig. 5. In addition, in the above embodiment, the voltage applied to the gate 1〇6 is higher than The voltage applied to the substrate 102, thus the electron-rich inversion layer 114, is formed between the gate dielectric layer 104 and the substrate 1〇2, but the invention is not limited thereto. In another embodiment, when a voltage applied to the substrate 102 is higher than a voltage applied to the gate 106, a 'hole-rich accumulation layer (not shown) is formed in the gate dielectric layer. Between 1〇4 and substrate1〇2, this accumulation layer can also be used as a resistor to achieve the purpose of shunting the gate current along the accumulation layer to source current 15 and drain current 1]〇. Next, a plurality of embodiments will be exemplified to explain a method of manufacturing the semiconductor structure of the present invention. Differential JT Example ❹ Figs. 6A to 6B are cross-sectional views showing a manufacturing method of a half structure according to a first embodiment of the present invention. Referring to FIG. 6A, first, a gate dielectric layer 1〇4 is formed on the substrate 1〇2. 1〇2 is, for example, an N-type substrate or a p-type substrate, or a substrate having a well region (not shown) different from the substrate. The material of the substrate 1 〇 2 = 'for example, a single crystal, a multi-turn, a erroneous or a ruthenium carbide - the material of the electric layer 104 includes oxidized stone eve, and its formation method is exemplified by an oxidation method or a chemical vapor deposition process. . Then, a method of forming -U8-0124 29322twfdoc/n 201023359 Γ Γ / 12 / forming the recess 112 in the substrate 1 例如 2 is, for example, performing a side process. The steps of step::= can be isolated from the formation of shallow trenches (10). The steps in Fig. 6Α can also be interchanged. For example, at least the depressions 112 are formed in the upper substrate 102, and then the substrate 102 102 and the second: 1()4, therefore, the gate dielectric layer 1G4 is simultaneously formed on the substrate ❹11. Then, a process is performed to remove the gate dielectric layer 104 on the surface of the recess 。. (4) Please refer to FIG. The material of the gate 106 is f*厪. The material of the gate 106 is, for example, polycrystalline germanium, polycrystalline gold (:): metal or metal. The method of forming the gate 106 includes chemical gas i. The interpole 106 is a mask "using (4) dopant or by an ion implantation process to open the interfering regions 1〇7 and 1〇9 on the substrate 102 on both sides of the closed pole 106. Next, at the gate 106 A spacer 116 is formed on the sidewall of the spacer. The material of the spacer 116 is, for example, oxygen dicing, and is formed by, for example, chemical vapor deposition on the substrate 102 by forming - θ, a layer of spacer material (not shown), and then The part of the wall material is removed by an anisotropic surne. Then, the spacer is used as a mask, and the type I or p type is used. (4) Performing an ion implantation process to form concentrated doped regions 111 and 113 on both sides of the ιΐ6: bottom: 02. The lightly doped region 107 and the heavily doped region ill form a source positively 1〇8, and the lightly doped The impurity region 1〇9 and the thick swap region 113 form a non-polar region. Second Embodiment. FIGS. 7A to 7C are semiconductors 12 according to a second embodiment of the present invention. 201023359 ^^08-0124 29322twf.doc/n The second embodiment is similar to the first embodiment, and will be described below in different places, and the same portions will not be described again. Referring to FIG. 7A, at least one recess 112 is formed in the substrate 1〇2, The gate dielectric layer 1〇4 is formed on the substrate 102, so that the gate dielectric layer 1〇4 is simultaneously formed on the surface of the substrate 102 and the recess 112.

Next, referring to Fig. 7B, a gate 106 is formed on the gate dielectric layer 1〇4 and in the recess 112. Thereafter, the ion implantation process is performed with the gate 106 as a mask. The doped regions 1〇7 and 1〇9 are formed in the substrate 102 on both sides of the gate 106. Next, a spacer 116 is formed on the sidewall of the gate 106. Next, an ion implantation process is performed with the gap wall 116 as a mask to form concentrated doped regions (1) and U3 in the substrate H) 2 on both sides of the spacer μ. The light-doped region ι〇7 /, the doped region 111 is opened to form a source region 1〇8, and the lightly doped region and the densely doped region 113 form a non-polar region 11〇. ~^ is called 爹 peptide circle, using the tip discharge (point discharg £ = method to burn the gate dielectric layer ι〇T, T4] located at the bottom corner of the depression 112 (ie point A) IT" ll6 ^ layer i Wo, day Not) communicated and achieved the purpose of diversion. The structure of the bottom 17B can be used as a shunt for the single-burning = 2rTTTing; OTP), except that it can be used as a shunt after burning the recess 1 , the gate of the bottom corner, and the electrical layer 1 () 4 . For example, in Fig. 7f, the inversion layer or the accumulation layer formed on both sides thereof is not i-coded. "When the coding of the piece needs to be repaired, the profit is broken: please close the corner of the concave _ (such as 13 201023359 uuviv^j^-ζ, υ J8-0124 29322twf.doc/n ..., both sides of the The inversion layer or the cumulative layer has a larger degree of silkness (ie, point A)

曰 = ' Therefore, the method of fine tip discharge is burned _ place (ie A.. dip) 疋 is available. That is, Figure 7B

The ^ tree axis example (four) t factor = the degree of crime will also be greatly improved. J

In summary, in the present invention, the semiconductor structure is disposed at least one in the substrate and the dielectric layer is not disposed on the surface of the recess as a source device and the current is shunted as a source current and a secret current. The semiconductor structure used as a shunt is the same as the conventional gold-oxygen semiconducting t-structure. Therefore, its manufacturing method can be integrated with existing processes, and the complexity of the t-process is greatly reduced. In addition, since the semiconductor structure of the present invention is not required to have a large-sized snake-like multi-layer and gold > 1 layer, the size of the material is greatly increased. efficacy.

The gate in the trap 112 is turned on, so it is coded as 1. In addition, in the semiconductor structure of the present invention, at least one recess is used in the substrate, and a dielectric layer is disposed on the surface of the recess, which can be used as a single-burning, t-oxygen semiconductor structure to repair the component. . * The semiconductor structure of the present invention does not have an unpredictable phenomenon of burnout points, and its reliability is greatly improved. In addition, the semiconductor structure can be used as a shunt after the gate dielectric layer of the bottom corner of the recess is blown, and the above-mentioned area is not integrated with the existing process material. Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and it is not intended to limit the scope of the present invention. The scope of protection of the present invention is defined by the scope of the appended claims. ",, [Simplified illustration] semiconductor structure

1 is a cross-sectional view of one of the embodiments of the present invention. FIG. 1 is a cross-sectional view of one of the embodiments of the present invention. A schematic cross-sectional view of the structure shown. Etc., FIG. 4 is a partial top view of the semiconductor structure of FIG. 2. Figure 5 is a partial top plan view of one configuration of another embodiment of the present invention. Figure 6A to Figure 6 are cross-sectional views showing a method of fabricating a semiconductor structure in accordance with a first embodiment of the present invention. 7A through 7C are cross-sectional views showing a method of fabricating a structure in accordance with a second embodiment of the present invention. [Description of main component symbols] 100, 200: semiconductor structure 101: active region 102: substrate 104: gate dielectric layer 15 201023359w δ-0124 29322twf.doc/a 106: gate 107, 109: lightly doped region 10 8 * Source region 110 ·> and polar regions 111, 113: densely doped regions 112, 112a, 112b, 112c, 112d: recesses 114 · inversion layer 116: spacers LI, L2: distance

16

Claims (1)

201023359 '0124 29322twf.doc/n X. Patent Application Range: 1. A semiconductor structure comprising: a gate electrode layer disposed on a substrate, wherein at least one recess is disposed in the substrate; a gate is disposed in the And on the gate dielectric layer and the recess; and a source region and a drain region are respectively disposed in the substrate on both sides of the gate. 2. The semiconductor structure of claim 1, wherein, in an operation, an inversion layer or a buildup layer is formed between the gate dielectric layer and the substrate such that a gate current is along the The inversion layer or the accumulation layer is divided into a source current flowing to the source region and a infinite current flowing to the gate region. 3. The semiconductor structure of claim 2, wherein a shortest distance between the recess and the source region is L1, and a shortest distance between the at least one recess and the drain region is L2 When the source current is proportional to L2/(L1+L2)', the drain current is proportional to L1/(L1+L2). 4. The semiconductor structure of claim 1, further comprising a dielectric layer disposed on a surface of the recess. 5. The semiconductor structure of claim 1, wherein a dielectric layer is not disposed on a surface of the recess. 6. The semiconductor structure of claim i wherein the semiconductor structure further comprises a well region disposed in the substrate. 7. The semiconductor structure of claim 1, wherein the material of the substrate comprises ruthenium. The semiconductor structure of claim i, wherein the material of the gate dielectric layer comprises hafnium oxide. 9. The semiconductor structure of claim 1, wherein the material of the gate comprises polysilicon, polycrystalline metal, metal halide or metal. 10. A method of fabricating a semiconductor structure, comprising: forming a closed dielectric layer on a substrate, forming at least one recess in the substrate; forming a dielectric layer on the gate dielectric layer and the gate electrode The source region and the drain region are formed in the substrate. 11. For example, the manufacturing method of the semi-conducting structure of the first fiber of the first fiber, the 'in the operation', the inversion layer H is formed between the closed dielectric substrates, so that a gate current is along the opposite The transfer layer or the accumulation layer/knife is the source current flowing to the drain region and flowing toward the drain current. W Method π The manufacturing method of the semiconductor structure according to Item 11, wherein the at least one recess and the source L1, the shortest distance between the at least one trap and the secret area is! Γί == 广正...2/(L1+L2), the immersed current is proportional to 13. The semiconductor described in the patent application scope 〇 = = before the step of forming the gate dielectric layer is formed at least - The method of claim 1, wherein the step of forming the gate dielectric layer is performed after forming the guide 18 201023359_4 29322twf.doc/n. 15. The semiconductor junction method of claim 10, wherein the method of forming the gate dielectric layer comprises performing a thermal oxidation vapor deposition process. For example, the method of manufacturing the semi-conductive hard structure of the patent, the method of forming the at least one recess includes performing a surface engraving process. The method of manufacturing a semiconductor structure as described in claim 1, wherein the material of the substrate comprises ruthenium. 18. The method of fabricating a semiconductor structure according to claim 1, wherein the material of the dielectric layer comprises oxidized stone. 19. The method of fabricating a semiconductor structure as described in claim 1 wherein the material of the gate comprises a polycrystalline stone, a poly (tetra) metal, a metal telluride or a metal. 19