201023344 六、發明說明： 【發明所屬之技術領域】 本發明有關一種電熔絲結構，特別是有關一種半導體裝置用 之接觸插塞電熔絲結構及接觸插塞電炫絲裝置與唯讀記憶體之製 法。 【先前技術】 ® 隨著半導體製程的微小化以及複雜度的提高，半導體元件也 變得更容易受各式缺陷或雜質所影響，而單一金屬連線、二極體 或電晶體等的失效往往即構成整個晶片的缺陷。因此為了解決這 個問題’現行技術便會在積體電路中形成一些可熔斷的連接線 (fiisible links)，也就是熔絲(fiise)，以確保積體電路的可利用性。 一般而言’熔絲係連接積體電路中的冗餘電路(redundancy ❹ circuit) ’ 一旦檢測發現電路具有缺陷時，這些連接線就可用於修 復(repairing)或取代有缺陷的電路。另外，目前的熔絲設計更可以 提供程式化(programming elements)的功能，以使各種客戶可依不 同的功能設計來程式化電路。而從操作方式來說，熔絲大致分為 熱熔絲和電熔絲(eFuse)兩種。所謂熱熔絲，是藉由一雷射切割(iaser zip)的步驟來切斷；至於電熔絲則是利用電致遷移 (electro-migration)的原理使熔絲出現斷路，以達到修補的效果。 201023344 多晶石夕電·__位於多林層 開機制如第1圖所示，—雷㈣·碰 n糸的斷 €熔絲結構1的陰極與一熔斷裝置 (_η_Γ)2的電晶體的没極電連接，於電炼絲結構丄的陽極 上施加-電壓WS，於電晶體賴極施加 汲極施加-電廢Vd，電θι§#(ίΛ、Ε^ 日日體的源極接地。電流(I)由電熔絲結構1 的陽極流向電熔絲結構丨的陰極，電子邮)由·絲結構 極流向電熔絲結構1的陽耦 4 β ω 町丨W極。進仃熔斷時所使用的電流 ❹ 佳範圍，電流太低時，所 所侍的阻值太低，會使電性遷移不完整， 電流太4 t導致觀絲熱破裂。—般，對於65臟製程的 絲結構的熔斷電流為約13毫安培(mA)。 習知之多晶梦電炼絲結構可為例如第2及3圖所示。多晶石夕 電熔絲結構1G之形狀為卫字形，即具有窄頸部分，包含一陽極 12、一陰極14、及—炼絲本體16。在陽極12上，有複數個鶴插 塞18，在陰極14上，也有複數個鶴插塞20。由第3圖的戴面圖 觀之，陽極12、陰極14、及炫絲本體16是由一偷層= 於多晶讀22上的金屬魏物層24所形成。金屬魏物層μ幫 助各鶴插塞與各電極有良好的電性接觸。陰極14上需要有複數個 鶴插塞18以提供足夠量的電子流至陰極14，並流動至狹窄形狀的 熔絲本體16的多晶矽層22及金屬矽化物層24中，產生電致遷移 現象，而使熔絲本體16斷開。因為陰極需要供複數傭塞接觸， 以提供大量電子流，所以往往需要較大的尺寸。並且，因為需要 大量的電子流以足夠將熔絲本體斷開，所以也需要大的溶斷裝置 201023344 (即，MOS電晶體），以能夠提供足夠的電子流。因此，習知之多 晶矽電熔絲裝置的尺寸大，難以應用於32nm半導體製程節點中。 再者’於32nm製程中，多使用金屬閘極取代多晶矽閘極，因此， 此等習知之多晶梦電炫絲結構的製造也不能便利地與32ηπι製程 整合。 因此，仍需要一種新穎的電熔絲結構，其具有相對小的尺寸， 〇 並且可進一步便利地使用金屬閘極材料。 【發明内容】 本發明之一目的是提供一種接觸插塞電熔絲結構，其可應用 於例如電熔、置及唯讀記麵結構巾。應用於魏雜置時， 其在陰極僅需要-個接職塞，並与要的親相對較小因此 ^觸播塞電熔絲結構加上致斷裝置的整體尺寸可減小許多。再 ®播μ本發社接觸插塞電熔絲結構亦可制的制與金屬閘極一 =Γ與蝴翻時繼。朗神狀‘嶋構時， 、、，。構與製程均簡單，且燒錄方便。 再于 ^據本發明之接觸插塞電炼絲結構包括一石夕層及一接觸插 接觸插一第一端及一第二端’第-物夕層接觸。對 一空洞而_。接觸插塞細層接觸之第—端之處形成 201023344 於本發明之另_方面，依據本個之製造接觸插塞電熔絲裝 置之方法，包括提供-基底，其包括—金氧半導體(M〇_晶體區 及-電熔絲區；於基底形成位於M〇s電晶體區及電溶絲區之間之 -第-隔離結構及位於電熔絲區之—第二隔離結構；於m〇s電晶 ，區的基底上形成-閘極；於電熔絲區之第二隔離結構上形成一 陽極陰極、及—連接陽極與陰極之熔絲連結體；於閘極二侧 之基底分卿成-源極及—祕；全面沉積—介電層覆蓋基底； ❹及於介電層中形成至少一第一接觸插塞、僅一第二接觸插塞、及 -第三接_塞，其分別貫穿該介電層而與陽極、陰極、及沒極 接觸。 於本發明之又一方面，依據本發明之製造唯讀記憶體陣列結 構之方法包括下列步驟。提供一半導體基底。於半導體基底上形 成複數個閘極結構。進行一摻雜製程，以於閘極結構旁的半導體 ❹基底形成複數個摻雜區。於各摻雜區上形成一接觸插塞。在至少 一接觸插塞施加一電壓，以形成一空洞而將其斷開。 【實施方式】 凊參閱第4圖，其係如第2圖所示之習知之多晶石夕電熔絲結 構10沿著AA’線段的截面的穿透式電子顯微照片。本發明之發明 人發現在多晶矽電熔絲結構斷開(blown)時，金屬矽化物因電子流 由陰極流至陽極之故，而由陰極被掃移至陽極，使得金屬矽化物 層呈現斷空的現象。更發現’在金屬石夕化物被掃移(SWept)後，連 201023344 接陰極的鎢插塞也被掃移，而有鹤損失(tungstenl〇ss)的現象。多 晶石夕電熔絲結構斷開的過程巾，電阻(Rs)值由小到大而變化。請再 參閱第5圖，其係如第2圖所示之習知之多晶石夕電熔絲結構川沿 著BB線段的截面的穿透式電子顯微照片。由第5圖所示，發明 人更發現在陰極上的三鹏減巾，财巾_鎢插塞有鎢損失 •的現象。基於此等現象，發明人提出___賴穎雜臟塞電熔絲 結構、製造接觸插塞電熔絲裝置之方法、及製造唯讀記憶體陣列 ❹ 結構之方法，詳述於後。 請參閱第6圖，接觸插塞電熔絲裝置3〇包括一陽極32、一陰 極34、及一熔絲連結體36。熔絲連結體36連接陽極32與陰極34。 陽極32上連接有至少一個接觸插塞38，但個數並無特別限制，個 數較多，相對可使阻值較小，並且可有導熱或散熱的功能，避免 陽極的溫度過熱。圖中顯示有六個接觸插塞38。陰極34上則僅連 ^ 接一個接觸插塞4〇,尺寸相對的小，並且因為僅有一個接觸插塞， 所以來自致斷裝置(blowing device)之電晶體汲極的電子流可集中 流入此接觸插塞中，達成有效率的'斷開，也因此致斷裝置供應的 電流相對上不需太大，致斷裝置的尺寸也因此不需太大，相對上 可較習知技術使用的致斷裝置小許多。接觸插塞電熔絲裝置3 〇的 形狀並無特別限定，可以是窄頸的形狀，但不限於此，其陰極34 的大小可略大於接觸插塞40的底面積即可。接觸插塞的尺寸可依 設計所需及製程極限而定。接觸插塞的形狀'不限於圓筒狀或柱 •狀’並可為平截頭體狀(frustum)。陽極尺寸亦為可足供所有其上排 201023344 置的接觸插塞的接觸所需即可。 1¼極32、陰極34、及熔絲連結體36的材料可包括導電材料， 例如多晶矽、金屬、或此二者之組合，可彼此相同或不相同，但 為了製程上的便利，較佳與電晶體之間極所使用的材料相同，並 .且同時進行閘極及電熔絲結構的製造。例如，當使用多晶矽做為 ，閘極的材料時，亦使用此多晶矽做為陽極32、陰極34、及熔絲連 ❹結體％之材料，並將陽極32、陰極34、及熔絲連結體36同時圖 案化而一體以形成。其他之閘極材料尚可為金屬或一層多晶矽層 與層金屬層的上下結合的複合體。金屬可為例如Ta、TaN、Ti、 Τι>ί、A1、Cu等。接觸插塞的材質可為導電材料，例如鎢金屬、 Ta、TaN、Ti、TiN、AbCu等，可與半導體裝置的製程整合。 第7圖顯示第6圖的接觸插塞電熔絲裝置30沿著cc，線段之201023344 6. Technical Field of the Invention: The present invention relates to an electrical fuse structure, and more particularly to a contact plug electrical fuse structure for a semiconductor device and a contact plug electric glare device and a read-only memory The method of production. [Prior Art] ® With the miniaturization and complexity of semiconductor processes, semiconductor components are also more susceptible to various types of defects or impurities, and single metal wires, diodes, or transistors are often ineffective. That is, it constitutes a defect of the entire wafer. Therefore, in order to solve this problem, the current technology forms fisible links, that is, fuses, in the integrated circuit to ensure the availability of the integrated circuit. In general, a fuse is connected to a redundancy circuit in the integrated circuit. Once the circuit is found to have defects, the wires can be used to repair or replace the defective circuit. In addition, the current fuse design can provide programming elements to enable various customers to program circuits in different functional designs. In terms of operation mode, fuses are roughly classified into two types: thermal fuses and electric fuses (eFuse). The so-called thermal fuse is cut by a laser iaser zip; as for the electric fuse, the fuse is broken by the principle of electro-migration to achieve the repair effect. . 201023344 Polycrystalline stone ‧ electric _ _ located in the multi-forest layer opening mechanism as shown in Figure 1, - Lei (four) · touch n糸 broken cathode fuse structure 1 cathode and a fuse device (_η_Γ) 2 of the crystal Without a pole connection, a voltage WS is applied to the anode of the electroformed wire structure, and a drain is applied to the anode of the transistor. The electric waste Vd is electrically θι§# (Λ, Ε^ The source of the Japanese body is grounded. The current (I) flows from the anode of the electric fuse structure 1 to the cathode of the electric fuse structure ,, and the electrons flow from the filament structure to the male coupling 4 β ω 丨 W pole of the electric fuse structure 1 . The current used in the fuse is 佳 good range. When the current is too low, the resistance value is too low, which will make the electrical migration incomplete. The current is too long, causing the wire to break. Typically, the fuse current for a 65 gauge process is about 13 milliamps (mA). The conventional polycrystalline montage wire structure can be, for example, shown in Figures 2 and 3. The polycrystalline stone electric fuse structure 1G has a shape of a Wei shape, i.e., has a narrow neck portion, and includes an anode 12, a cathode 14, and a wire body 16. On the anode 12, there are a plurality of crane plugs 18, and on the cathode 14, there are also a plurality of crane plugs 20. Viewed from the worn view of Fig. 3, the anode 12, the cathode 14, and the glare body 16 are formed by a layer of metal that is on the polymorph read 22. The metal-property layer helps the crane plugs to have good electrical contact with the electrodes. A plurality of crane plugs 18 are required on the cathode 14 to provide a sufficient amount of electrons to the cathode 14 and flow to the polysilicon layer 22 and the metal halide layer 24 of the narrow-shaped fuse body 16 to cause electromigration. The fuse body 16 is disconnected. Since the cathode needs to be contacted by a plurality of plugs to provide a large amount of electron flow, a larger size is often required. Also, because a large amount of electron flow is required to break the fuse body sufficiently, a large dissolution device 201023344 (i.e., MOS transistor) is also required to be able to provide sufficient electron flow. Therefore, the conventional polysilicon electric fuse device has a large size and is difficult to apply to a 32 nm semiconductor process node. Furthermore, in the 32 nm process, a metal gate is often used in place of the polysilicon gate. Therefore, the fabrication of such a conventional polycrystalline montage wire structure cannot be conveniently integrated with the 32ηπι process. Accordingly, there is still a need for a novel electrical fuse structure that has a relatively small size, and that further facilitates the use of metal gate materials. SUMMARY OF THE INVENTION One object of the present invention is to provide a contact plug electrical fuse structure that can be applied, for example, to electrofusion, and read-only surface structure towels. When applied to Wei miscellaneous, it only needs a pick-up plug at the cathode, and is relatively small compared with the desired pro- um. Therefore, the overall size of the touch plug electric fuse structure plus the breaking device can be reduced much. Then, the manufacturer can also make the system and the metal gate with a plug-in electrical fuse structure. The shape of the sacred ‘ 嶋 嶋 , , , ,. The structure and process are simple and easy to burn. Further, the contact plug electroformed wire structure according to the present invention comprises a glazing layer and a contact plug contact with a first end and a second end. For a hole and _. Contacting the first end of the fine layer contact of the plug to form 201023344. According to another aspect of the present invention, a method for manufacturing a contact plug electric fuse device according to the present invention includes providing a substrate including a metal oxide semiconductor (M 〇 _ crystal region and - electric fuse region; the base is formed between the M 〇s transistor region and the electrolysis filament region - the first isolation structure and the second isolation structure located in the electric fuse region; s electro-crystal, forming a gate on the base of the region; forming an anode cathode on the second isolation structure of the electric fuse region, and a fuse link connecting the anode and the cathode; and a base on the two sides of the gate a source-source and a secret; a comprehensive deposition-dielectric layer covering the substrate; and forming at least a first contact plug, only a second contact plug, and a third connection plug in the dielectric layer The anode, the cathode, and the immersion contact are respectively penetrated through the dielectric layer. In still another aspect of the invention, a method of fabricating a read-only memory array structure according to the present invention includes the following steps: providing a semiconductor substrate. Forming a plurality of gate structures thereon. Performing a doping system A plurality of doped regions are formed on the semiconductor germanium substrate adjacent to the gate structure. A contact plug is formed on each doped region, and a voltage is applied to at least one of the contact plugs to form a cavity to break it. [Embodiment] Referring to Fig. 4, it is a transmission electron micrograph of a section of a conventional polycrystalline litter structure 10 as shown in Fig. 2 along the line AA'. The invention of the present invention It has been found that when the polycrystalline germanium electric fuse structure is blown, the metal telluride is flown from the cathode to the anode due to the flow of electrons, and the cathode is swept to the anode, so that the metal telluride layer is broken. It was found that after the metal ruthenium compound was swept (SWept), the tungsten plug connected to the cathode of 201023344 was also swept away, and there was a phenomenon of crane loss (tungstenl〇ss). The polycrystalline stone electric fuse structure was broken. The process towel, the resistance (Rs) value changes from small to large. Please refer to Figure 5, which is a cross section of the conventional polycrystalline lithobus fuse structure shown in Figure 2 along the BB line. Transmitted electron micrograph. As shown in Figure 5, the inventors found more on the cathode. The phenomenon of the Sanpeng towel, the turban, the tungsten plug has a tungsten loss. Based on these phenomena, the inventor proposed ___Lai Ying's dirty plug fuse structure and method for manufacturing the contact plug electric fuse device. And a method of fabricating a read-only memory array structure, which is described in detail below. Referring to FIG. 6, the contact plug electrical fuse device 3 includes an anode 32, a cathode 34, and a fuse link 36. The fuse link body 36 is connected to the anode 32 and the cathode 34. At least one contact plug 38 is connected to the anode 32, but the number is not particularly limited, the number is relatively large, the relative resistance is small, and heat conduction or The function of heat dissipation avoids overheating of the anode. The figure shows six contact plugs 38. On the cathode 34, only one contact plug 4〇 is connected, the size is relatively small, and because there is only one contact plug, Therefore, the electron flow from the transistor bungee of the blowing device can be concentrated into the contact plug, achieving an efficient 'disconnection, and therefore the current supplied by the breaking device is relatively small, so The size of the breaking device is therefore not too large, relatively The breaking device used in the prior art is much smaller. The shape of the contact plug electric fuse device 3 is not particularly limited and may be a narrow neck shape. However, the shape of the cathode 34 may be slightly larger than the bottom area of the contact plug 40. The size of the contact plug can vary depending on the design requirements and process limits. The shape of the contact plug 'is not limited to a cylindrical shape or a column shape' and may be a frustum. The anode size is also sufficient for all of the contact plugs placed on the upper row of 201023344. The material of the 11⁄4 pole 32, the cathode 34, and the fuse link 36 may include a conductive material such as polysilicon, metal, or a combination of the two, which may be the same or different from each other, but is preferably electrically used for process convenience. The materials used for the poles between the crystals are the same, and the gate and electrical fuse structures are fabricated at the same time. For example, when polycrystalline germanium is used as the material of the gate, the polycrystalline germanium is also used as the material of the anode 32, the cathode 34, and the fuse junction, and the anode 32, the cathode 34, and the fuse link are used. 36 is simultaneously patterned and integrated to form. Other gate materials may be a composite of metal or a layer of polycrystalline germanium and a layer of metal. The metal may be, for example, Ta, TaN, Ti, &ι> ί, A1, Cu, or the like. The material of the contact plug can be a conductive material, such as tungsten metal, Ta, TaN, Ti, TiN, AbCu, etc., which can be integrated with the process of the semiconductor device. Figure 7 shows the contact plug electrical fuse device 30 of Figure 6 along the line cc,
截面不意圖’於此具體實施例中，陽極32、陰極34、及熔絲連結 體 36 I 一起形成而為一電熔絲圖案層4 2，而電熔絲結構達成斷開功 效後之斷開處係在接觸插塞4〇的地方。如圖所示，接觸插塞4〇 的斷開處係以形成空洞41的態樣呈現。 於本發明中，當電熔絲裝置冬陽極、陰極、及熔絲連結體的 表面為多晶矽材質時，即，如第8圖所示的截面圖，陽極32、陰 極34、及熔絲連結體36形成一體的電熔絲圖案層，而為一多晶矽 材質或具有一多晶矽層44於表面時，彳進一步於陰極34表面上 9 201023344 形成一金屬矽化阻擋層(salicideblock，SAB)46，覆蓋陰極34的 整個表面’將未被SAB層覆蓋的地方進一步形成金屬石夕化物層 48，未被SAB層覆蓋的地方例如為陽極32及熔絲連結體％，其 一部分或全部表面形成金屬矽化物層。SAB層可為例如氮化矽、 氮氧化石夕、或其他適合的材料。陽極32上的接觸插塞38係與金 •屬矽化物層48接觸，陰極34上的接觸插塞4〇係貫穿3八6層46 以與多晶㈣44接觸。如此’阻值在多晶㈣44處會較大生 ❹熱較多，溫度提高’可有利於接觸插塞4〇的鶴金屬電致遷移以造 成斷開’而在金射化物層48有較低的阻值，可避免壓降過大； 並且生熱較小，可避免電熔絲過熱爆裂。 接觸插塞電熔絲裝置可位於半導體基板之絕緣結構(例如淺溝 渠)上，陰極以接觸插塞經由金屬内連線及致斷裝置之電晶體的沒 極上的接觸插塞以與此祕做電性連接。請參閱第9及ig圖，顯 ❿示本發明之製造接觸插塞電熔絲裝置之方法，其係將致斷裝置一 起整合製造。首先’請參閱第9圖，提供一基底5〇，其可為例如 料體基底。其包括-金氧半導體(⑽)電晶⑽及一電溶絲 區〇4接著’進行一隔離製程作㈣⑽卿㈣，於電晶體 ^及電熔絲區HM之間的基底5〇中形成—隔離結構，例如淺 ，離結構52 ’做為致斷裝置與電熔絲裝置之間的隔離。並可同 =於^絲區104的基底5〇形成一隔離結構，例如淺溝隔離結構 結構52及54可填人例如氧化物。接著，全面 一薄介電層，例如氧化物層，例如氧切、氧她、氧化給 201023344 化鑭等’於基底上’再全面形成一閘極材料層，例如金屬層、多 曰日矽層、或是多晶矽層與金屬層上下堆疊的複合層，但不限於此， 再進行微影與侧製程’定義出問極56及其下方的閉極介電層 58使其位於MOS電晶體區1〇2的基底上，及同時定義出涵括電 炼絲裝置的陽極區塊、陰極區塊及料連結翻形的電熔絲圖案 層60 ’電熔絲圖案層6〇是位於電溶絲區1〇4的淺溝隔離結構％ 的表面上。於閘極56二側的基底5〇中經由摻雜製程分別形成一 β祕62及-祕64。_可進—步於_ %嫩上形成一側壁 子66。 ,然後’請參閱第10圖，可視情況進一步進行自對準石夕化金屬 製程使沒極62及源極64表面形成一金屬石夕化物層關〇金屬矽化 物可為例如錦化石夕或銘化石夕，但不限於此。當問極％與電炼絲圖 案層60的表面是金屬時，並不會形成金屬石夕化物層。接著，可藉 ❹由例純學氣她财法，-介 7G錢絲5〇。將 介電層70侧形賴口峨為接卿，可進—步形雜障 IV·層)於開口的底部及·，然後填人插塞材料，例如鶴 可利用例如化學氣相沉積法進行__，再進行_。 接觸插塞72、-接觸插塞74、及一接觸插塞％，其分別貫 層70而分別與陽極、陰極、及汲極上的金屬石夕化物層肋接觸 另外也形成接觸插塞78及接觸插塞⑽’其分财穿介 。 分別與閘極56、及源極64上的金屬石夕化物層68接觸。接^ 介電層70的表面上進行金屬内連線的製作’例如形成一金屬内連 201023344 線82連接陰極上的接觸插塞 屬内㈣S4胳心 驗極上的接觸播塞76，及一金 屬内連線84㈣極上的接觸插塞72與周邊的邏輯電路連接。 曰當間極的材料是多晶料_表面是多砂 疋否對電熔絲圖案層6〇進行自 熔轉圖*展Μ、心a 卻化金屬製程。若不考慮對電 Γ對料化金屬製程，則可將電料區_ ❹ ^電日0體區⑽進行源極、閘極、與祕的自對準石夕 熔絲圖索Ϊ，以於其表面形成金屬石夕化物層。若考慮進一步將電 …圖案層60的陽極區塊與熔絲連結體進行自對準石夕化金屬製 程，則可參閱第η _製程，即，先於基底5Q上全面形成一湖 層86，並定義圖形，以露出⑽電晶體區ι〇2的源極、間極、 與汲極表面及電熔絲區1G4的陽極區塊與輯連結體表面，但陰 極區塊仍覆蓋著SAB層86。錢如第12圖所示，全面沉積一介 電層7〇覆蓋基底5〇。於介電層7〇中形成接觸窗，可進一步形成 阻障層(例如Ti/TiN層)關口的底部及_，織填人插塞材料， 例如鶴金屬，以形成-接觸插塞72、一接觸插塞74、及一接觸插 塞76，其分別貫穿介電層70而分別與陽極、陰極、及汲極上的金 屬矽化物層68接觸。另外也形成接觸插塞78及接觸插塞80，其 分別貫穿介電層70而分別與閘極56、及汲極64上的金屬矽化物 層68接觸。於介電層70的表面上進行金屬内連線的製作，例如 形成一金屬内連線82連接接觸插塞74與接觸插塞76，及一金屬 内連線84將接觸插塞72與周邊的邏輯電路連接。 12 201023344 與習知之電熔絲裝置比較之，包含依據本發明之接觸插塞電 熔絲結構之接觸插塞絲裝置尺寸可相對較小，斷開時所需要 的電流量也相對較小，例如與習知之多晶絲裝置比較之， 可降低、約30〇/〇以上。並且可便利的依據閘極使用的材料製作，例 如與金屬閘極或多晶石夕閘極的製程是相容的。並且具有下列優 點：電熔絲單元可採用多_電熔絲單_形狀，可在高電流下 斷開或保持原樣；可與-般邏輯製程相容，並不需要額外的光罩 ❹或製程步驟’故不增加成本；尺寸大小有，可與將來的半導 體世代相容；可做封裝級或現場級⑽復；在電熔絲結構上方可 允許多層的金屬佈線，例如五層或甚至五層以上的金屬佈線，可 具有改良的佈局佈線；其於晶片情開所㈣時間少於雷射型炫 絲結構熔斷所需的_，節省_ ;可廣泛使祕冗餘電路的修 復(redundancy repairing)、類比電路的修整(trimming〇fanai〇gThe cross-section is not intended to be 'in this embodiment, the anode 32, the cathode 34, and the fuse link 36 I are formed together to form an electric fuse pattern layer 42, and the electric fuse structure is broken after the disconnection effect is achieved. It is in contact with the plug 4〇. As shown, the break of the contact plug 4 is presented in the form of a cavity 41. In the present invention, when the surface of the winter fuse, the cathode, and the fuse link of the electric fuse device is a polycrystalline material, that is, a cross-sectional view as shown in FIG. 8, the anode 32, the cathode 34, and the fuse link. 36. Forming an integrated electric fuse pattern layer, and being a polysilicon material or having a polysilicon layer 44 on the surface, further forming a metal salicide block (SAB) 46 on the surface of the cathode 34 9 201023344, covering the cathode 34 The entire surface 'to be further covered by the SAB layer further forms the metallization layer 48, and the portion not covered by the SAB layer is, for example, the anode 32 and the fuse link %, and a part or all of the surface thereof forms a metal telluride layer. The SAB layer can be, for example, tantalum nitride, nitrous oxide, or other suitable materials. The contact plug 38 on the anode 32 is in contact with the gold telluride layer 48, and the contact plug 4 on the cathode 34 is passed through the 3-8 layer 46 to contact the polysilicon 44. Thus, the 'resistance value will be higher in the polycrystalline (four) 44, and the temperature increase will be beneficial to the electromigration of the crane metal contacting the plug 4 to cause disconnection and lower in the gold emitter layer 48. The resistance value can avoid excessive pressure drop; and the heat generation is small, which can avoid overheating and bursting of the electric fuse. The contact plug electric fuse device may be located on an insulating structure of the semiconductor substrate (for example, a shallow trench), and the cathode is in contact with the plug via the metal interconnect and the contact plug on the pole of the transistor of the breaking device. Electrical connection. Referring to Figures 9 and ig, there is shown a method of manufacturing a contact plug electrical fuse device of the present invention which is integrally fabricated with a breaking device. First, please refer to Fig. 9, which provides a substrate 5, which may be, for example, a substrate. The method comprises: a gold-oxygen semiconductor ((10)) electro-crystal (10) and an electro-dissolving filament region 〇4 followed by an isolation process (4) (10) (4), formed in the substrate 5〇 between the transistor ^ and the electric fuse region HM - The isolation structure, such as shallow, from the structure 52' acts as an isolation between the breaking device and the electrical fuse device. An isolation structure may be formed with the substrate 5 of the wire region 104. For example, the shallow trench isolation structures 52 and 54 may be filled with, for example, an oxide. Then, a thin dielectric layer, such as an oxide layer, such as oxygen cut, oxygen, oxidation, 201023344, etc., is formed on the substrate to form a gate material layer, such as a metal layer and a multi-layered tantalum layer. Or a composite layer in which the polysilicon layer and the metal layer are stacked on top of each other, but is not limited thereto, and the lithography and side processes are defined to define the gate 56 and the closed dielectric layer 58 below it so as to be located in the MOS transistor region 1 The base of the crucible 2, and at the same time, define an anode block, a cathode block and a material-connected flip-shaped electric fuse pattern layer 60, which are located in the electrolysis wire region. 1〇4 of the shallow trench isolation structure on the surface of %. A β secret 62 and a secret 64 are respectively formed in the substrate 5 二 on both sides of the gate 56 via a doping process. _ can proceed - step on the _% tender to form a side wall 66. Then, please refer to Figure 10, and further self-aligning the metallization process can be used to form a metal-lithium layer on the surface of the electrode 62 and the source 64. The metal telluride can be, for example, Jinhua Shixi or Ming. Fossil eve, but not limited to this. When the extreme % and the surface of the electroformed pattern layer 60 are made of metal, the metal lithium layer is not formed. Then, by virtue of the example, she is purely eager to learn her wealth, and she will be able to introduce 7G money. The dielectric layer 70 is formed on the side of the dielectric layer 70, and the stepped barrier IV layer is applied to the bottom of the opening and then filled with a plug material, such as a crane, for example, by chemical vapor deposition. __, then _. The contact plug 72, the contact plug 74, and a contact plug % are respectively connected to the anode, the cathode, and the metal lithium layer rib on the drain, and also form the contact plug 78 and contact. The plug (10)'s its wealth. Contact with the metal-lithium layer 68 on the gate 56 and the source 64, respectively. Fabricating the metal interconnect on the surface of the dielectric layer 70, for example, forming a metal interconnect 201023344 line 82 connecting the contact plug on the cathode (4) the contact plug 76 on the S4 core, and a metal interior The contact plug 72 on the wire 84 (four) pole is connected to the peripheral logic circuit. The material of the 曰 间 是 多 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ If the process of metallizing the metal is not considered, the source region, the gate electrode, and the secret self-aligned stone fuse can be used for the electric material region _ ❹ ^ electric day 0 body region (10). A metal ruthenium layer is formed on the surface. If it is considered to further self-align the anode block and the fuse link of the electric pattern layer 60 with the fuse link, the η _ process can be referred to, that is, a lake layer 86 is formed on the substrate 5Q. And defining a pattern to expose (10) the source, interpole, and drain surfaces of the transistor region ι〇2 and the anode block and the interconnect surface of the electrical fuse region 1G4, but the cathode block still covers the SAB layer 86. . As shown in Fig. 12, the entire layer of dielectric layer 7 is deposited to cover the substrate 5〇. Forming a contact window in the dielectric layer 7〇, further forming a bottom layer of the barrier layer (for example, Ti/TiN layer) and _, filling a plug material, such as a crane metal, to form a contact plug 72, The contact plug 74 and a contact plug 76 are respectively in contact with the metal telluride layer 68 on the anode, the cathode, and the drain, respectively, through the dielectric layer 70. Contact plugs 78 and contact plugs 80 are also formed which are respectively in contact with the metal halide layer 68 on the gate 56 and the drain 64 via the dielectric layer 70. Fabricating the metal interconnects on the surface of the dielectric layer 70, for example, forming a metal interconnect 82 connecting the contact plug 74 and the contact plug 76, and a metal interconnect 84 contacting the plug 72 and the periphery Logic circuit connection. 12 201023344 The contact plug wire device comprising the contact plug electrical fuse structure according to the invention can be relatively small in size compared to conventional electrical fuse devices, and the amount of current required to disconnect is relatively small, for example Compared with the conventional multi-wire device, it can be reduced by about 30 〇/〇. It can also be conveniently fabricated from materials used in the gate, such as those compatible with metal gates or polysilicon gates. And has the following advantages: the electric fuse unit can adopt a multi-electric fuse single-shape, can be disconnected or kept at the high current; can be compatible with the general logic process, and does not require an additional mask or process The step 'has not increased the cost; the size is different, and can be compatible with future semiconductor generations; can be package level or field level (10) complex; can allow multiple layers of metal wiring above the electric fuse structure, such as five or even five layers The above metal wiring can have improved layout and wiring; it is less than the time required for the laser type structure to be blown in the wafer situation (4), saving _; can be widely used for redundancy repairing (redundancy repairing), Trimming of analog circuits (trimming〇fanai〇g
Circuit)、晶片鑑別碼及密碼(chip-ID and password strings)。 ❹ 如上述第7及8圖所示，在對接觸插塞4〇的上端施加一電壓 (大於或等於啟始電壓(啟始電壓是恰可使接觸插塞電炼絲結構斷 開的電壓值)後’接觸插塞40在與陰極34接觸的下端處會形成一 空洞。此空洞可能是因為接觸插塞4〇的金屬例如鶴金屬發生電致 遷移所產生。空洞之處是不通電的狀態。接觸插塞4〇與其下端接 觸的石夕層(例如陰極3俩織的結構，即是本發明之接觸插塞電 熔絲結構。此接觸插塞電熔絲結構除了應用於上述之電熔絲裝置 中’亦可應躲唯讀記㈣結射’做為該唯讀記賴結構燒錄 201023344 時之燒斷結構。 接觸插塞可進-步由一金屬插塞及—阻障層包覆該金屬插塞 而形成如此接觸插塞與石夕層接觸之面係阻障層。在施加電壓斷 開時’可觀察到的現象是接觸面的阻障層的原子及金屬插塞的一 端的原子遷空，但在金屬插塞壁上的阻障層可能留下，形成空洞， 使得電路斷開，或是電阻改變。 ❹ 姓 凊參閱第13圖，其顯示一包含依據本發明之接觸插塞電熔絲 結構之唯讀記憶體結構示意圖。唯讀記憶體88係形成於一基底9〇 上，例如p型半導體基底，且在基底9〇上設有複數個n型摻雜區 2- 1、2-2、2-3、2-4、2-5、2_6、複數個絕緣薄膜(insuiating fllm) 3]、 3- 2、3-3、3-4、3-5以及複數個分別設於此等絕緣薄膜上之多晶矽 薄膜(polysilicon film) 4-卜 4-2、4-3、4-4、4-5。藉由此等多晶矽 薄膜、設於多晶矽薄膜下方之絕緣薄膜以及設於薄膜兩側之n型 ❿摻雜區，在基底90上定義出複數個NM〇s電晶體。各多晶矽薄 膜係為各NMOS電晶體之閘極，並分別電連接相對應之字元線 (word line)，而η型摻雜區即為此NMOS電晶體之源極/汲極。唯 讀s己憶體88可另包含一第一金屬導線層(first metal wiring layer) 5-1、5-2、5-3、5-4、5-5、5-6 以及一第二金屬導線層(second metal wiring layer) 6-l·、6·2、6-3、6-4、6-5、6-6 ’ 第一金屬導線層以及 第二金屬導線層間由介層插塞(via plUg) 1〇_1、10-2、10-5、10-6 . 連接’且第一金屬導電層5-1、5-2、5-3、5-4、5-5、5-6與各η型 201023344 摻雜區2]、2·2、2_3、2_4、2·5、2·6間分別由接觸插塞7]〜、 =^5、、及Μ連接。但是有—部分的η型摻雜區(例如。 "2·2、2-5、2·6)上設置有金屬魏物層92，因此， 有-部分的接觸插塞是與摻雜區上的金屬魏物層接觸，例如接 觸插塞7 1、7.2、7·5、及7·6 ;而另-部分的接觸插塞是直接與 摻雜區接觸’例如接觸插塞7_3及7_4，此等即利用依據本發明之 接觸插塞電熔絲結構。 第一金屬層6-2、6-3、6-4、6-5係為該唯讀記憶體之位元線(bit line)BL〇、BLi、BL2、BL3，且該等位元線與字元線的交界處即為 儲存= 貝料的記憶胞(memory cell)。其中位元線BL〇、BL!、BL2、 BL3係藉由介層插塞1〇_2、1〇 3、1〇_4、1〇_5及接觸插塞7 2、7 3、 7-4、7-5與下方之^型掺雜區2_2、2-3、2-4、2-5電連接。當燒錄 唯讀記憶體時’經由位元線對接觸插塞施加電壓，接觸插塞7_3、 7-4在接觸η型摻雜區2_3、2_4處，發生斷開的現象，於接觸插塞 © 的端點產生空洞91，阻斷電路。施加電壓後，接觸插塞產生空洞 與否’便決定該等記憶胞所儲存的訊息資料為「0」或「1」，進而 構成該唯讀記憶體的程式編碼。因此，可依據程式編碼，於對應 的記憶胞設置接觸插塞電熔絲結構。 應用本發明之接觸插塞電熔絲结構於唯讀記憶體中的另一態 樣是不於η型摻雜區表面設置金屬矽化物層，故亦毋需於η型摻 雜區表面設置SAB層，而直接於每一 η型摻雜區上形成接觸插 15 201023344 塞。再依據程式編碼，以定址方式對該位置之記憶胞的接觸插塞 施加一大於或等於啟始電壓值的電壓，將該接觸插塞接觸n型摻 雜區的一端斷開’以此方式記錄此等記憶胞所儲存的訊息資料為 「〇」或「1」。 第14圖顯示依據本發明之製造唯讀記憶體陣列結構之方法之 一具體實施例之剖面示意圖。首先，提供一半導體基底90。於半 ❹導體基底90上形成複數個閘極結構，其可包括絕緣薄膜、 3 3 3 4、3-5及多晶石夕層4-1、4-2、4-3、4-4、4-5。然後，進行 一雜製程，以㈣極結構旁的半導體基底9G形成複數個n型摻 雜區 2-1、2-2、2-3、2-4、。 接著，若是要形成金屬矽化物層的情形，可進一步先形成SAB 層94於。卩分摻雜區上，及曝露一部分摻雜區。進行一自對準金屬 石夕化反應’形成一金屬石夕化物層92於裸露的換雜區表面。然後， 可進=例如鑲嵌或雙鑲嵌製程，於摻雜區上形成接觸插塞，並使 於覆盍有SAB層的摻顏上卿成的細減貫穿_層而與 其下層摻雜區接觸’及於覆蓋有金屬石夕化物層的摻雜區上所形成 的接觸敏與該金屬魏物層之上表面接觸。及_形成金屬内 連線結構或介層插塞結構。可得如第13圖所示之具體實施例。 右疋利用定址方式燒錄的唯讀記憶體，而不必形成金屬矽化 • 物層的㈣，則在摻雜區形錢，可直接進行接糖塞的製作， 201023344 =:==:_成接觸插塞，直接接 同樣的，亦可將斷開機制設置於閘極結構，即，閘極結構上 層為多晶❸層時，此多晶何做為接觸插塞電熔絲結構^要的 石夕層’而於閘滅構上設置_插塞。如此，亦具有如上述於摻 雜區上形成接觸插塞之多種變化的情形。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範 圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖顯示電熔絲裝置之斷開機制。 第2圖顯示一習知之多晶矽電熔絲結構之頂示圖。 第3圖顯示第2圖之多晶矽電熔絲結構沿著AA，線段之截面 ❹示意圖。 第4圖顯示第2圖之多晶妙電炫絲結構斷開時沿著aa，線段 之戴面之穿透式電子顯微照片。 第5圖顯示第2圖之多晶矽電熔絲結構斷開時沿著bb，線段 之截面之穿透式電子顯微照片。 第6圖顯示依據本發明之接觸插塞電熔絲結構應用於電溶絲 裴置之一具體實施例之頂示圖。 第7圖顯示第6圖中沿著CC’線段之截面示意圖。 17 201023344 第8圖顯示依據本發明之接觸插塞電熔絲結構應用於電熔絲 裝置之另一具體實施例之截面示意圖。 第9及10圖顯示依據本發明之製造接觸插塞電熔絲裝置之方 法之一具體實施例之戴面示意圖。 第11及12圖顯示依據本發明之製造接觸插塞電熔絲裝置之 方法之另一具體實施例之截面示意圖。 第13圖顯示依據本發明之接觸插塞電熔絲結構應用於唯讀記 ❹憶體之-具體實施例之截面示意圖。 —第14圖顯示依據本發明之製造唯讀記憶體陣列結構之方法之 具體實施例之截面示意圖。Circuit), chip-ID and password strings. ❹ As shown in the above 7 and 8 diagrams, a voltage is applied to the upper end of the contact plug 4〇 (greater than or equal to the starting voltage (the starting voltage is the voltage value at which the contact plug electroforming wire structure is disconnected) The rear contact plug 40 forms a void at the lower end in contact with the cathode 34. This void may be caused by electromigration of a metal such as a crane metal contacting the plug 4, and the void is not energized. The structure in which the contact plug 4 is in contact with the lower end thereof (for example, the structure of the cathode 3) is the contact plug electric fuse structure of the present invention. The contact plug electric fuse structure is applied to the above-mentioned electrofusion. In the wire device, 'can also be read only (4) Ejection' as the read-only structure of the burnt structure when burning 201023344. The contact plug can be stepped by a metal plug and a barrier layer package The metal plug is covered to form a surface barrier layer which is in contact with the plug and the contact layer. The observable phenomenon when the applied voltage is broken is the atom of the barrier layer of the contact surface and one end of the metal plug. The atom is vacant, but the barrier layer on the metal plug wall may Underneath, a void is formed, causing the circuit to be broken, or the resistance to change. 凊 Surname 凊 Refer to Figure 13, which shows a schematic diagram of a read-only memory structure including the contact plug electrical fuse structure according to the present invention. 88 is formed on a substrate 9〇, such as a p-type semiconductor substrate, and a plurality of n-type doped regions 2-1, 2-2, 2-3, 2-4, 2-5 are disposed on the substrate 9〇. 2_6, a plurality of insulating films (insuiating fllm) 3], 3-2, 3-3, 3-4, 3-5 and a plurality of polysilicon films respectively disposed on the insulating films. 4-2, 4-3, 4-4, 4-5. The polycrystalline germanium film, the insulating film disposed under the polysilicon film, and the n-type germanium doped region disposed on both sides of the film are defined on the substrate 90. A plurality of NM〇s transistors are formed. Each polysilicon film is a gate of each NMOS transistor and electrically connected to a corresponding word line, and the n-type doping region is the NMOS transistor. Source/drain. The read-only suffix 88 may further comprise a first metal wiring layer 5-1, 5-2, 5-3, 5-4, 5-5, 5- 6 and one Second metal wiring layer 6-l·, 6·2, 6-3, 6-4, 6-5, 6-6 'between the first metal wiring layer and the second metal wiring layer (via plUg) 1〇_1, 10-2, 10-5, 10-6 . Connection 'and the first metal conductive layer 5-1, 5-2, 5-3, 5-4, 5-5, 5 -6 and each of the n-type 201023344 doped regions 2], 2·2, 2_3, 2_4, 2·5, and 2. 6 are connected by contact plugs 7]~, =^5, and Μ, respectively. However, a part of the n-type doping region (for example, "2·2, 2-5, 2.6) is provided with a metal-derived material layer 92, and therefore, the part-part contact plug is doped region The upper metal layer contact, for example, the contact plugs 7 1 , 7.2, 7·5, and 7·6; and the other part of the contact plug is directly in contact with the doped region, such as contact plugs 7_3 and 7_4, These utilize the contact plug electrical fuse structure in accordance with the present invention. The first metal layers 6-2, 6-3, 6-4, and 6-5 are bit lines BL〇, BLi, BL2, and BL3 of the read-only memory, and the bit lines and The intersection of the word lines is the memory cell that stores the material. The bit lines BL〇, BL!, BL2, BL3 are through the dielectric plugs 1〇_2, 1〇3, 1〇_4, 1〇_5 and the contact plugs 7 2, 7 3, 7-4. 7-5 is electrically connected to the underlying doped regions 2_2, 2-3, 2-4, 2-5. When the read-only memory is burned, 'the voltage is applied to the contact plug via the bit line, and the contact plugs 7_3, 7-4 are in contact with the n-type doped regions 2_3, 2_4, and the disconnection occurs. The endpoint of © generates a hole 91 that blocks the circuit. After the voltage is applied, the contact plug generates a hole or not, and then the message data stored in the memory cells is determined to be "0" or "1", thereby constituting the program code of the read-only memory. Therefore, the contact plug electrical fuse structure can be set in the corresponding memory cell according to the program code. Another aspect of applying the contact plug electrical fuse structure of the present invention to a read-only memory is that a metal germanide layer is not disposed on the surface of the n-type doped region, so it is not necessary to provide SAB on the surface of the n-type doped region. The layer is formed directly on each of the n-type doped regions to form a contact plug 15 201023344 plug. According to the program code, a voltage greater than or equal to the starting voltage value is applied to the contact plug of the memory cell of the location in an address manner, and the contact plug is disconnected from the end of the n-type doped region. The message data stored in these memory cells is "〇" or "1". Figure 14 is a cross-sectional view showing a specific embodiment of a method of fabricating a read-only memory array structure in accordance with the present invention. First, a semiconductor substrate 90 is provided. Forming a plurality of gate structures on the semi-turn conductor substrate 90, which may include an insulating film, 3 3 3 4, 3-5, and polycrystalline layers 4-1, 4-2, 4-3, 4-4, 4-5. Then, a heterogeneous process is performed to form a plurality of n-type doped regions 2-1, 2-2, 2-3, 2-4, with the semiconductor substrate 9G next to the (four)-pole structure. Next, in the case where a metal telluride layer is to be formed, the SAB layer 94 may be further formed first. The doped region is doped, and a portion of the doped region is exposed. A self-aligned metal-like reaction is performed to form a metal-lithium layer 92 on the exposed surface of the exposed region. Then, a contact plug can be formed, for example, a damascene or dual damascene process, and a contact plug is formed on the doped region, and the fine-doped layer of the doped layer overlying the SAB layer is contacted with the underlying doped region. The contact sensitivity formed on the doped region covered with the metallic lithium layer is in contact with the upper surface of the metal wafer layer. And forming a metal interconnect structure or a via plug structure. A specific embodiment as shown in Fig. 13 can be obtained. On the right side, the read-only memory that is burned by the address method is used, and it is not necessary to form the metal deuteration layer (4). In the doped area, the money can be directly formed, and the sugar plug can be directly produced. 201023344 =:==:_ Contact The plug is directly connected to the same, and the disconnection mechanism can also be set in the gate structure, that is, when the upper layer of the gate structure is a polysilicon layer, the polycrystal is used as a contact plug electrical fuse structure. The eve layer is set to _ plug on the brake extinction. Thus, there are also cases where a plurality of variations of contact plugs are formed on the doped regions as described above. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should fall within the scope of the present invention. [Simple description of the diagram] Figure 1 shows the disconnection mechanism of the electric fuse device. Figure 2 shows a top view of a conventional polysilicon electrical fuse structure. Fig. 3 is a schematic cross-sectional view showing the polycrystalline silicon electric fuse structure of Fig. 2 along the line AA. Fig. 4 is a view showing a transmission electron micrograph of the wearing surface along the line aa when the polycrystalline singular structure of Fig. 2 is broken. Fig. 5 is a view showing a transmission electron micrograph of a section along the line bb of the polysilicon electric fuse structure of Fig. 2 when it is broken. Fig. 6 is a top plan view showing a specific embodiment of a contact plug electric fuse structure according to the present invention applied to an electrolysis wire. Fig. 7 is a cross-sectional view showing the line along the CC' line in Fig. 6. 17 201023344 Figure 8 shows a cross-sectional view of another embodiment of a contact plug electrical fuse structure for use in an electrical fuse device in accordance with the present invention. Figures 9 and 10 show schematic views of one embodiment of a method of fabricating a contact plug electrical fuse device in accordance with the present invention. Figures 11 and 12 show schematic cross-sectional views of another embodiment of a method of making a contact plug electrical fuse device in accordance with the present invention. Figure 13 is a cross-sectional view showing a contact plug electrical fuse structure according to the present invention applied to a readable memory. - Figure 14 is a cross-sectional view showing a specific embodiment of a method of fabricating a read-only memory array structure in accordance with the present invention.
【主要元件符號說明】 1 10 14 18、2〇 24 32 36 40 42 電熔絲結構 多晶矽電熔絲結構 陰極 鎢插塞 金屬矽化物層 陽極 炫·絲連結體 接觸插塞 電熔絲圖案層 SAB層 2 熔斷裝置 12 陽極 16 熔絲本體 22 多晶妙層 30 電熔絲結構 34 陰極 38 接觸插塞 41 空洞 44 多晶妙層 48 金屬矽化物層 18 46 201023344[Main component symbol description] 1 10 14 18, 2〇24 32 36 40 42 Electric fuse structure polycrystalline germanium electric fuse structure cathode tungsten plug metal telluride layer anode dazzle wire connector contact plug electric fuse pattern layer SAB Layer 2 Fuse device 12 Anode 16 Fuse body 22 Polycrystalline layer 30 Electrical fuse structure 34 Cathode 38 Contact plug 41 Cavity 44 Polycrystalline layer 48 Metal telluride layer 18 46 201023344
50 基底 52、54 淺溝隔離結構 56 閘極 58 閘極介電層 60 電熔絲圖案層 62 汲極 64 .源極 66 側壁子 68 金屬矽化物層 70 介電層 72、74、76、78、80 接觸插塞 82、84金屬内連線 86 SAB層 88 唯讀記憶體 90 半導體基底 91 空洞 92 金屬矽化物層 94 SAB 層 102 MOS電晶體區 104 電熔絲區 2-1、2-2、2-3、2-4、2-5、2-6 η型摻雜區 3-卜 3-2、3-3、3-4、3-5 絕緣薄膜 4-1、4-2、4-3、4-4、4-5 多晶矽薄膜 5-1、5-2、5-3、5_4、5-5、5-6 、46 第一金屬導線層 6-1、6-2、6-3、6-4、6-5、6-6 、48 第二金屬導線層 10-1 ' 10-2 ' 10-3 ' 10-4 ' 10-5 、10-6 介層插塞 BL〇 ' BLj ' BL2 > BL3 ' BL4 位元線 1950 substrate 52, 54 shallow trench isolation structure 56 gate 58 gate dielectric layer 60 electrical fuse pattern layer 62 drain 64. source 66 sidewall spacer 68 metal germanide layer 70 dielectric layer 72, 74, 76, 78 , 80 contact plugs 82, 84 metal interconnects 86 SAB layer 88 read only memory 90 semiconductor substrate 91 cavity 92 metal germanide layer 94 SAB layer 102 MOS transistor region 104 electric fuse region 2-1, 2-2 , 2-3, 2-4, 2-5, 2-6 η-type doped regions 3-Bu 3-2, 3-3, 3-4, 3-5 Insulation film 4-1, 4-2, 4 -3, 4-4, 4-5 polycrystalline germanium films 5-1, 5-2, 5-3, 5_4, 5-5, 5-6, 46 first metal wiring layers 6-1, 6-2, 6- 3, 6-4, 6-5, 6-6, 48 second metal wire layer 10-1 '10-2 ' 10-3 ' 10-4 ' 10-5, 10-6 interlayer plug BL〇' BLj ' BL2 > BL3 ' BL4 bit line 19