TW201021389A - Adaptive PWM pulse positioning for fast transient response - Google Patents

Abstract

An adaptive pulse positioning system for a voltage converter including an adjustable ramp generator, a pulse generator circuit, and a sense and adjust circuit. The adjustable ramp generator has an adjust input and provides a periodic ramp voltage having an adjustable magnitude based on an adjust signal provided to the adjust input. The pulse generator circuit receives the ramp voltage and generates a pulse signal with control pulses for controlling the output voltage of the voltage controller based on the ramp voltage. The sense and adjust circuit senses an output load transient and provides the adjust signal to the adjust input of the ramp generator to adaptively shift the pulse signal in time in response to the output load transient without adding pulses to the pulse signal.

Description

201021389 VI. Description of the Invention: [Technical Fields of the Invention] The related application is also referred to the continuation of the US Patent Application No. 1 1/383,878, which is filed on May 17, 2010. The case is currently approved on November 18th, and is granted US Patent (4) No. 7,453,246, which itself claims the right of US Patent Application No. 60/737,523, filed November 16, 2005. The U.S. Patent Application Serial No. 4,459, the entire disclosure of which is incorporated herein by reference in its entirety in its entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire disclosure [Prior Art] [Embodiment] The description provided below allows the person skilled in the art to make and use the invention within the specific application background and its necessary conditions. Various modifications of the preferred embodiment will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the intention of the present invention is not intended to limit the scope of the invention as set forth in the <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt;

The load current of modern circuits, including modern central processing units (CPUs), is extremely dynamic and will quickly change from low to high and from high to high. For example, the current transient of the central processing unit may occur within i microseconds (AS), which is less than the typical switching period of a conventional voltage regulator. 1 is a timing diagram of an operational mode of an adaptive pulse width modulation pulse localization technique in accordance with the present invention. The output load current (1) of a DC-DC power conditioner (not shown) is plotted in relation to a PWM signal and a PWM signal. At the initial time (7), the signal IL_ is at the normal level lN0R^. The clock signal generates a periodic clock pulse based on a predetermined clock frequency. During normal operation under normal load as indicated by the IN0RM level of the signal, each P W Μ pulse will begin during each clock cycle and be terminated by a pulse on the clock signal. At the subsequent time u, the output transient occurs due to the signal jumping to the new high current level indicated by IHIGH. In response to the output load transient, the next pulse 1〇1 of the PWM signal is repositioned toward the beginning of the current clock cycle as indicated by arrow 103 with its normal position indicated by the dashed line. By moving the pulse ι〇ι towards the beginning of the cycle after applying a heavy load, the blank period after the transient event is naturally shortened so that there is no additional voltage 201021389 in the initial transient response. In this case, the pulse 101 also has a longer duration of time in response to an increase in the output load. During this high load event (when the IL0AD bit is at IHIGH), the subsequent pulses of the PWM signal, 1〇5, 1〇7, and will be offset towards the start of the individual clock cycle. At the subsequent time t2, the signal IL0ad will return to the normal level. The next pulse lu of the PWM signal will be shifted back to the normal position at the end of the clock cycle as indicated by arrow 113. In the particular modulation technique shown in Figure 1, PWM pulses often occur at the end of the cycle. Under this transient event, the PWM pulse is pulled forward in response to the output drop. After this transient event, the PWM pulse will return to its normal level (for example, at the end of the clock). To avoid an extra voltage drop due to the blank period relationship, under heavy load, the PWM pulse will move towards the beginning of the cycle. Under light load, 'the PWM pulse will be at the end of the clock, and the second = load condition to move', for example, moving to the beginning of the cycle under full load conditions. The pulse is flexible and can achieve better performance. . In addition to repositioning the pulse, it is also possible to have the same second PWM pulse 'which causes the output to stabilize more quickly. However, if the "state event occurs at a high repetition rate, the same cycle should be expected to be in-or multiple consumption trends. For fast transients, it is better to use light load, let the _ The pulse is pulled forward. Nearly, there will be enough space (4) 2: Keep it at the end of the cycle and pull it forward. The pulse can be placed anywhere in the pulse under heavy load two transient events. In the case of a switching cycle, after the transient, the pulse of 201021389 will immediately end, and a blank time is required to discharge the inductor current. Therefore, under heavy load conditions, it may be desirable to have the PWM pulse out. Now the starting point of the cycle. So under light load conditions, the PWM pulse will remain at the end of the cycle' and move to the beginning of the cycle as the load increases.

❹

2 is a simplified block diagram of a trailing edge modulator circuit 200 implemented in accordance with an embodiment of the present invention. The timing source 2〇1 generates a clock signal A that is provided to the input of a delay function 203. The delay function 203 delays the signal A and provides a delayed clock signal AD to the input of a ramp generator 205 and a clock input (ck) to the pulse timing circuit 211. In an alternate embodiment, the pulse timing circuit is replaced by an SR flip-flop. The ramp generator 205 generates a ramp signal B which is provided to an input (e.g., a reverse input) of a pulse width modulation comparator 207. Error amplifier 209 provides a compensation signal C to the other input of comparator 2〇7 (e.g., 'non-inverting input'). The comparator 207 generates a signal D' which is supplied to the control (CTL) input of the pulse sequential circuit 2 11. The pulse timing circuit 211 generates a PWM signal based on the signal D for controlling the output voltage of the DC-DC power regulator, and is configured to ensure that only one cycle of each cycle of the signal AD is provided. pulse. A current sensing block 213 provides an adjustment signal ADJ to the other input of the delay function 203. The current sense block 2 13 senses the load current IL0AD flowing through an output load (as shown) and controls the signal ADJ accordingly. The figure also shows that signal C and the output voltage V OUT of the converter are provided to the delay function 203. The amount of delay (or T DELAY) between signal A and AD is

ADJ

V OUT

And C's function or 7 201021389 TDELAY=TDl + fl*ADJ + f2*C + f3*VOUT ' where TD1 is a constant; and functions Π, f2, and f3 are any appropriate functions, depending on the situation, the range is relative Simple to complex. In one embodiment, Π to f 3 are all constant. In an alternate embodiment, the current sense block 213 senses the current flowing through an output inductor of the regulator or senses the phase current of each of the one or more output phase circuits. FIG. 3 shows an operational timing diagram of the trailing edge modulator circuit 200. The graph of the relationship between the fin signals Iload, A, AD, B, C, D, and PWM versus time. The signals B and C are superimposed on each other to more clearly illustrate the function of the map composer 207. In the embodiment shown in the figures, the ramp generator 205 generates a signal B having a sawtooth waveform of the rising ramp. Therefore, when the pulse of the signal AD is at the high level, the ramp signal B will start at the low ramp level R1〇; and will rise at a constant rate when the AD pulse returns to the low level. In the embodiment shown in the figures, the ramp signal B is limited to a predetermined high level Rin. The compensation signal C is configured to have a range between rl〇 and rhi. In operation, the ramp signal B resets J Rlo at the initial edge of the clock signal AD and begins to rise at the trailing edge of the AD. When b is lower than c, the comparator 207 determines that the signal D is at a high level; otherwise, it determines that the signal D is at a low level. In addition to the start point after the signal AD becomes a low level in each cycle, the pulse sequence circuit 211 usually determines the PWM signal in a manner similar to the signal D; so that when the AD becomes a low level, the Μ becomes a quotient level. And when D becomes a low level, it will become a low level. The operation is repeated in this way, and the duration of each PWM pulse will depend in part on the level of the compensation signal C. 201021389 In a conventional trailing edge modulator circuit (not shown), the delay function 203 does not exist, so the timing is based on the clock signal a rather than the clock signal AD. The delay function 203 only causes the timing of the clock signal ad to be adjusted based on the signal ADJ from the current sensing block 2 13 . The current sensing block 2 1 3 will be signaled iL 〇 AD (or other sensed) Based on the level of the output current), the signal ADJ is selected. At time t9, the signal iL〇AD will jump from Inorm to Ihigh as described above. The current sense block 213 responds to correct the signal ADJ to reduce the delay of the signal AD relative to the clock signal A. As shown at 301, the next pulse on signal AD is offset or relocated at an earlier time in the loop. The early initial edge of the AD pulse resets the ramp signal B back to R1〇 earlier than the normal value shown at 3〇3. An early reset of the ramp signal B causes the signal D to be positioned at an earlier time in the loop as indicated at 305. This early pulse on signal D causes the pwM signal to be shifted and is determined at an earlier time in the cycle as shown at 307. After the load transient offset event, the timing of the pulses is actually the same except that they are offset relative to the normal conditions. The relative width of the pwM pulses can be adjusted to handle additional loads. In this manner, the pWM signal is relocated to an earlier time in the loop in response to the load transient event. As long as the load transient event exists, the pwM signal will remain offset; and will return to normal when the inter-load condition is removed. As shown at time (four), the signal Iload will return IN 〇 RM ' and the next AD pulse will be shifted to the later time in the loop as shown. This causes the D pulse and the PWM pulse to shift back to normal positioning. In this way, the PWM pulse's fixed 9 201021389 bit is "adjusted or adapted to provide better performance in response to the load. The delay function 203 does not increase the frequency of the clock signal, but instead only temporarily adjusts the PWM. The purpose of the positioning of the pulse. It should be noted that the delay length during the normal condition can generate a period such as signal A as needed. If the delay is approximately equal to the clock period, the PWM pulse can be almost relocated to _ Anywhere in a given loop 'in response to a non-synchronized load transient event. Figure 4 is a simplified block diagram of a dual-edge modulator circuit 400 implemented in accordance with an embodiment of the present invention. In the same manner as the modulator circuit 2, a timing source 401 generates a clock signal a which is supplied to the input of a delay function 403. The operation of the delay function is substantially the same as the delay function 203. The function 4〇3 delays the signal a and provides an input of the delayed clock signal AD to a triangular ramp generator 4〇5 and a clock (CK) to the pulse sequential circuit 411. The triangular ramp generator 405 generates a triangular ramp signal τ which is supplied to an input of a comparator 407 (for example, an inverting input). The error amplifier 4〇9 provides a compensation signal. C to the other input of the comparator 407 (for example, 'non-inverting input') and to the delay function 403. The comparator 407 generates a signal D' which is supplied to the control input of the pulse timing circuit 411. The pulse timing circuit 411 generates a PWM signal based on the signal D for controlling the output voltage and is configured to ensure that there is only one pulse per cycle. A current sensing circuit 413 receives the signal. Iload also provides an adjustment signal ADJ to another input of the delay function 403. The delay function 403 also receives the signal ν 〇υτ as shown. The 201021389 current sensing circuit 4 1 3 senses a flow through a feed. The load current of the backup load or the current flowing through an output inductor or the phase current of each of the multiple output phase circuits will be as before, +, 仏u According to the control signal ADJ, the signal VOUT is also provided to the delay function 4〇3 as shown in the figure. The delay function 403 provides a delay amount substantially the same as the delay function 2〇3, or TDELAY =TDl+fl*ADJ+f2*C + f3*VOUT. ❹

Figure 5 shows the timing diagram of the operation of the double-edge modulator circuit. The plots of the signal lL0AD, A, AD, T, C, d, and PWM plotted against time are plotted. The signals D and C are superimposed on each other to more clearly understand the function of the map decoder 407. In this case, the clock signals a and ad are 5〇% duty cycle signals. When the pulse of the signal AD is at a low level, the triangular ramp signal T will rise, and when the signal ad is at a high level, it will fall. In operation, when the signal T is smaller than the signal C, the signal D will be judged as a high level; otherwise, it will be judged as a low level. When the signal D is at a high level, the pulse timing circuit 411 determines the PWM signal. The operation is repeated in this manner, and the duration of each PWM pulse is partially dependent on the level of the compensation signal C. In a conventional dual-edge modulator circuit (not shown), the delay function 403 does not exist, so the timing is based on the clock signal a, not based on the clock signal AD. For the dual-edge modulator circuit 4〇〇, the delay function 4〇3 only causes the timing of the clock signal AD to be adjusted based on the signal ADJ from the current sensing block 4丨3, which is used to adjust the timing of the clock signal AD. 4 13 will correct the signal ADJ based on the level of the signal Iload. At time t1, signal 1load will jump from IN0RM to IHIGH as previously described. The current senser 201021389 ❹ block 413 responds to correct the signal ADJ to reduce the delay of the signal AD relative to the clock signal A. As shown at 501, the signal AD will be offset at an earlier time in the loop due to the small delay relationship. The triangular ramp signal T will drop at an earlier stage (compared to normal conditions) to intersect the signal C at an earlier time in the loop as shown at 503. The early intersection between the signal τ and the signal C causes the signal D to be offset and is determined at an earlier time in the cycle as shown at 5〇5, which thus results in the indication at 5〇7 The PWM signal is relocated to an earlier time in the loop. The adaptive positioning causes the pWM signal to be relocated to an earlier time in the loop in response to a load transient event. As long as the load transient condition exists, the PWM signal will remain offset; and normal positioning will be returned when the load condition is removed. As shown at subsequent time t12, the signal how will return IN 〇 RM, causing the signals ad, d, and PWM to shift back to their normal position. In this way, the positioning of the pWM pulses is tailored or adapted and thus flexible to achieve better performance. The double-edge modulation technique using double-slope waves has been disclosed in the U.S. Patent No. 11/318, file No. G. No. 11/23, filed on Dec. 12, 2005. Dual-edge modulation pulse width modulation controller (PWM c〇ntroller with dual.edge :-(four)", which is incorporated herein by reference for all purposes and simultaneously with the per-ring! Limit the _pulse to two: two: one: two::, every cycle "The initial response to the heavy load transient event will occur without any PWM pulse cycle. May be in the 12 201021389

造成 Extra pressure drop after transient events. In a double-wave double-edge modulation technique, the 'PWM pulse total 疋 appears at the end of the cycle. Under a transient event, the PWM pulse may be pulled forward in response to the output voltage drop. After this transient event, the PWM pulse will return to the end of the loop. To avoid the extra voltage drop caused by this blank period, the PWM pulse may be moved to the beginning of the loop under heavy load. So at light loads, the PWM pulse is at the end of the cycle and it moves according to load conditions and is at the beginning of the cycle under full load conditions. The pWM pulse positioning system is flexible and variable for better performance. Fig. 6 is a schematic view showing a double-slope double-edge pulse width modulation modulation circuit 6A according to the embodiment described in the above-referenced patent application. The down-ramp comparator CMP 1 has a non-inverting input for receiving a compensation signal vC0MP (eg, from an error amplifier, for example, 2〇9, 4〇9); a reverse input for receiving A downward ramp signal Vd〇wnramp; and an output coupled to a set input of a set-reset (SR) flip-flop 6〇1. The upward ramp comparator CMP2 has: an inverting input for receiving the signal VC0MP; a non-inverting input for receiving an up ramp signal VUP_RAMP; and an output coupled to the SR flip-flop 6重置1 reset input. The Q output of the SR flip-flop 601 determines the pWM signal to provide a PWM pulse. A timing source 6〇3 generates a clock signal CK which is supplied by k to a rake ramp generator 6 〇 5. In the embodiment shown in the figure, the edge ramp generator 605 generates a downward ramp tooth waveform synchronized with the signal CK. The figure 5 shows V ^ ^ * h. 〇wn_ramp. When the down-ramp signal drops to the level of VC0MP, the comparator CMP1 determines its output as 13 201021389 high level and sets the SR flip-flop 601, and the SR flip-flop 601 determines that the PWM signal is high. To start each PWM pulse. A trailing edge ramp generator 607 generates a trailing edge ramp signal (shown as an up ramp signal VUP_RAMP) for the purpose of terminating each PWM pulse. When the PWM signal is judged to be high, the trailing edge ramp generator 607 begins to rise the signal VUP RAMP (for example, see the operation of the signal vUP-RAMP shown in Figure 16). When Vup-RAMP arrives at vC0Mp, CMP2 will determine its output as a high level to reset the sr flip-flop 601 and pull the PWM signal to the low level to terminate each PWM pulse. When the PWM is pulled down, the trailing edge ramp generator 6〇7 will again pull the signal VUP RAMP back to the low level. The double-slope dual-edge pulse width modulation circuit 6〇〇 turns the pWM pulses on and off at any time within a switching cycle, making the transient response very fast. Under normal operation, the pWM pulse will appear at the end of the switching cycle. When a heavy load is applied at the beginning of the cycle, the PWM pulse is pulled forward to the beginning of the switching cycle in an attempt to keep the output within specifications. To limit the switching frequency, it is usually allowed in a switching cycle. There is only one PWM pulse. If the transient transient load event and the PWM pulse occur at the beginning of the cycle, then another PWM pulse will not occur after the next cycle. There may be a long period in which no PWM pulses appear, so that after the initial response, the operation sequence of the double-short-wave double-edge pulse width modulation modulation circuit 600 is shown. The system's double-slope double-edge pulse modulation technique 201021389 The long blank period (blank peri〇d) problem. The signal L 〇 AD drawn in the figure, four signals VD 〇 WN - RAMP 1 to 4 (one per phase, or D 〇 WN-RAMP1 to V 〇〇 WN_RAMP4); the voltage of the compensation signal (VC0MP); The relationship between the four PWM signals PWM, PWM2, PWM3, and PWM4 with respect to time. At approximately time t2 〇 4, a heavy load is applied to the system and the control loop will quickly initiate all phases that respond to this event, as indicated by the sync pulse on each PWM signal. At the rear ❿&quot;, time gate t21, all phases will be turned off. At the subsequent time t22, the control voltage VC0MP will return to its operating point. In the ideal case, if the right system is stable after this time, then the control voltage is expected to be as ambiguous as indicated by the dashed line 701. However, since each cycle has a pulse limit 'no other pulse before time t24. Therefore, in the ideal case, there will be a "blank" period T1 between times t21 and t24, which is approximately equal to the switching period. In the actual situation; in the brothers, the target is not ^ any PWM pulse appears in the blank period, so the output voltage before the next: the PWM pulse will continue to drop. Therefore, the actual compensation signal VC0MP will increase as shown in 703 4 in an attempt to keep the output power in specifications. Therefore, the cycle will have a PWM pulse at an earlier time (2): so that the actual blank period τ2 between times m and m will be much smaller than the switching period. Even if the blank period A is much smaller than the cut period, it will cause an additional voltage drop, and the output voltage may oscillate for several cycles as it stabilizes. Therefore, in the dual-edge technology of the four-edge technology of the towel, there may be a blank period after the initial transient response in the double-slope double-edge modulation technique, which will cause additional materials and possible vibrating problems. To prevent the blank period from being as short as possible. To solve this problem, the state is allowed to have the second formula in the same cycle. After the initial transient response, Vc〇Mp will be shown in the loop of Figure 7. TM rush, the output will be: if the transient event occurs at a high repetition rate, it will have a stable frequency, the switching frequency and heat consumption. For fast transient response, two: should be able to be pulled forward in a loop. Preferably, the PWM pulse is held at the end of the cycle, and is pulled forward. However, the pulse can be overweight: a (4) place inside the switching loop. For a load release event, the 2 pulse after the pulse width modulation will end immediately and a blank time is required to discharge the inductor current. Therefore, under heavy load conditions, it is possible to have a PWM pulse appear at the beginning of the cycle. Therefore, as further explained below, under light load conditions, the PWM pulse will remain at the end of the cycle and move to the beginning of the cycle as the load increases. Figure 8 is a block diagram of an adaptive pulse width modulated pulse positioning system in accordance with the present invention embodiment, which is applicable to a double ramp dual edge pulse width modulation modulation circuit. The same components are assumed to have the same component symbol as the device in the double-slope double-edge pulse width modulation circuit. Although the timing source 603 and the generators 6〇5 and 6〇7 are not shown in the figure; however, they are actually provided and operated in the same manner. The up-ramp comparator CMp2 will receive the signal 乂(:(^!&gt; with VUP RAMp' and its output will be coupled to the reset input of the SR flip-flop. The reverse input of the down-wave comparator CMpi will The 201021389 down ramp signal Vdow»_ramp is received and its output is lightly coupled to the set input of the SR flip-flop 601. In this case, an offset voltage V is added using a function block 8〇1 and an adder 803. To the error amplifier output signal VCOMP, the adder 803 provides an adjusted compensation signal Vci to the non-inverting input of the comparator CMP1. The output of the comparator cmpi is coupled to the set input of the SR flip-flop 601. The offset voltage v〇 is a function of the sense average current IAVG of all phases 匕(4), therefore, where Φ asterisk "*" represents multiplication. Under heavy load, the offset voltage V〇 is high, so that in the early stage of the cycle The PWM pulse is triggered. Although not shown in the figure; however, a balanced current can be used to adjust the compensation signal supplied to the up-ramp comparator CMP2, wherein the balanced current and a phase sense phase current Iphase and all phases The sense average current Lvg is related, for example, f2(IAVG, Iphase) 'where G is any suitable function. A simple example is Ibalance = k*(IAVG-Iphase), where k is a constant. A schematic diagram of a pulse width modulation pulse localization system 900 for performing an exemplary pulse width modulation pulse localization system 8〇〇_ and a double ramp dual edge pulse width modulation modulation circuit 800 The devices in the same device are assumed to have the same component symbols. Although the timing source 603 and the generators 605 and 6〇7 are not shown in the figure; however, they are actually provided and operated in the same manner. In this case The signal Vc〇Mp is supplied to one end of a resistor R1, and the other end of the resistor 1 generates a signal Vd which is supplied to the non-inverting input of the comparator CMP1. The current is injected to generate the signal VC1. Among the nodes, it will make v〇=RinAVQ and Vci-Vc〇Mp+ Ri*IavG. 17 201021389 4-phase system adaptive pulse width modulation pulse calibration map containing four downward ramp signals

The operation of the individual comparators for generating signals PWM1 to PWM4 is solved. The voltage of VC0MP is shown in dotted lines in the figure for comparison purposes. As shown in the figure, FIG. 10 is an operation timing diagram of a 4-phase appearance system 900. A load transient occurs just before time t30, which causes all signals PWM1 to PWM4 to be triggered, and then they will It becomes a low level again near time t31. At time t3 2, t3 3, and t34, additional PWM pulses appear on signals PWM2, pWM3, and PWM4, respectively. If signal Vc〇Mp is not directly supplied to comparator CMp, instead of modified compensation signal VC1, Then each one will appear earlier. In this way, the performance will be significantly improved. Figure 11 is a block diagram of an adaptive pulse width modulated pulse positioning system 1 00 in accordance with another embodiment of the present invention, which is applicable to a double ramp dual edge pulse width modulation modulation circuit. The adaptive pulse width modulation pulse positioning system 1100 is identical to the universal pulse width modulation pulse positioning system 800, wherein the same device is assumed to have the same component symbol. Although the timing source 6〇3 and the generators 605 and 607 are not shown in the figure; however, they are actually provided and operated in the same manner. Signal IAVG will be provided to function block 801 to generate an offset VO' offset voltage VO which is provided to the inverse input of adder iioi. The adder lioi will receive the signal Vdownramp at its non-inverting input. In this case, the signal VDOWNRAMP is adjusted by the offset voltage VO, 18 201021389 instead of the error amplifier output signal Vc 〇 Mp. The adder 丨1〇1 will subtract VO from VD0WN RAMP to generate an adjusted ramp signal VR, which will be supplied to the inverting input of comparator CMP1. As shown, the error amplifier output signal VC0MP will be directly Provided to the inverting input of comparator CMP2, comparator CMP2 will receive its output at its non-inverting input and its output will be coupled to the reset input of SR flip-flop 6〇1. The SR flip-flop 601 operates in a similar manner to provide the pWM signal. Figure 12 is a block diagram of an adaptive pulse width modulation ❹ pulse positioning system 1200 in accordance with another embodiment of the present invention, which is applicable to a double ramp dual edge pulse width modulation modulation circuit. The adaptive pulse width modulation pulse positioning system 12 〇〇 and the double slant wave double edge pulse width modulation modulation circuit 6 are identical, wherein the same device hypothesis has the same component symbol. Although the timing source 6〇3 and the generators 605 and 607 are not shown in the figure; however, they are actually provided and operated in the same manner. The comparator CMP1 is provided and compares the signal Vc 〇 Mp and the signal VD0WN_RAMP and provides its output to the set input of the SR flip flop 601 to provide the PWM signal at its Q output. In this case a different offset voltage V02 is generated which is related to the sense phase current iPHASE of the individual phase in a multiphase converter. Current Iphase is provided to the input of function block 1201 (which will multiply IpHASE by function f3(s) to produce V02' and then v2 will be provided to the input of an adder 12〇3. Adder 1203 adds VC0MP to V02 to generate an adjusted compensation signal VC2. This signal VC2 will be supplied to the inverting input of comparator CMP2, which will receive VupRAMp at its non-inverting input and its output will be coupled to the reset input of SR flip-flop 601. Under heavy load, this bias 19 201021389 shifts voltage V02 high and voltage Vo decreases, which causes Vc〇Mp to increase to maintain the same duty cycle' resulting in early triggering of PWM pulses for each phase. 13 is a schematic diagram of an adaptive pulse width modulated pulse positioning system 13 00 for performing an exemplary embodiment of an adaptive pulse width modulated pulse positioning system 1200. Again, the same device assumes the same component symbol. Although timing source 603 and generators 605 and 607 are not shown in the figures; however, they are actually provided and operate in the same manner. In this case, the resistor R2 is used instead of the function block 12〇1 and the adder ❹1203匕 to receive the signal VC0MP and the other end will generate the signal Vq. As shown, the signal Vo will be provided. Reverse input to comparator CMp2. The current IPHASE is pulled out from the node where the signal Vo is generated, so that Vc2 = VCOMP - R2 * lPHASE. Comparator CMP2 compares the adjusted compensation signal VC2 and signal VUP RAMp, and the output of comparator CMP2 is coupled to the reset input of SR flip-flop 601. The circuit of the comparator CMP1 is the same as that shown in FIG. Figure 14 is an operational timing diagram of an adaptive pulse width modulated pulse chirp positioning system 1300 for a 4-phase system including four down ramp signals Vd〇wn~rAMP丨 to VDOWN RAMP4 and four pWMs. Signals pwM1 to PWM4. The graph plots the signal signals Il〇ad, v_N RAMp丨 to VD〇WN_RAMP4, and PWM1 to PWM4 versus time. The signal vC0MP and the signal ▽(10) dragon^(10)丨 to Vd〇wn^mh are superimposed on each other to illustrate the operation of the individual comparators for generating the signals PWM1 to PWM4. As shown in the figure, a load transient occurs at approximately the time to cause the signal 20 201021389

Vcomp is increased, thereby causing all signals P WM 1 to P WM4 to be triggered. The signals P WM1 to P WM4 will again become low levels at the subsequent time t4 1 . Additional PWM pulses appear on signals PWM2, PWM3, and PWM4 at times t42, t43, and t44, respectively, if signal VC0MP, instead of modified compensation signal VC2, is provided directly to comparator CMP2, then each They will all appear earlier. In this way, the performance will be significantly improved. 15 is a block diagram of a ramp-down wave generator 15A that can be used to generate a signal VD0WN_RAMP of the double-slope double-edge pulse width modulation modulation circuit 600, thereby illustrating the adaptability according to another embodiment of the present invention. Pulse width modulation pulse positioning system. Therefore, the double-skew double-edge pulse width modulation modulation circuit 600 is used in the figure except that the leading edge ramp generator 605 is replaced by the downward ramp generator 1500. For the ramp-up generator 150A, a controlled current sink 1501 is coupled between ground (GND) and node 1502 for generating the signal V〇0WN_RAMP. Capacitor ci will be coupled between node 1502 and GND. The cathode of diode 15〇3 will be coupled to node 15 02' and its anode will be coupled to the positive terminal of voltage source 1505 for generating minimum ramp voltage vMIN. A switching terminal of a SPST, single_p〇le single-throw switch SW is coupled between the node 15〇2 and the positive terminal of the voltage source 1507 for generating the maximum ramp voltage VMAX, where VMAX is greater than VMIN. The negative terminals of voltage sources 1505 and 1507 are coupled to GND. The switch SW has a control terminal for receiving a clock signal (CLK) which opens and closes the SW at the frequency of the signal CLK. The current slot 1501 has a control terminal ' for receiving the signal c + k * IAVG ' where C and k are constant. In this way, the current 21 201021389 of the current sink 15〇1 is based on the measured or sensed level of the iAVG. In operation of the ramp-up generator 1500, the switch sw will be closed and the voltage source 1507 will charge the capacitor C1 to the voltage level νΜΑχ. When the switch SW is opened, the current tank 15〇1 discharges the capacitor C1 at a rate based on the signal Uvg. It determines the constant... so that the normal operating level of the two pairs of signals iAVG determines the appropriate slew rate of the signal Vd〇wn ramp. When the signal Iavg is increased due to load transition, the slew rate of the signal 乂〇0__11心1&gt; is thus increased to accelerate the discharge of the capacitor ci and thereby reposition the next PWM pulse at an earlier time in the loop ❹. As a result, the slew rate of the signal VD0WNRAMp can be adjusted based on the sensed average current. At light loads, Iavg is low and the conversion rate of the signal vdownramp is very low. Under heavy load,

Uvg will mention that the conversion rate of the signal VD〇WNRAMp will increase, causing the PWM pulse to be triggered early in the cycle. Figure 16 is an operational timing diagram of an adaptive pulse width modulated pulse positioning system employing a down ramp generator 15A. The diagram plots the relationship of signals I1〇ad, CLK Vd〇wn_ramp, VUP RAMp, vc〇Mp, and pwM with respect to time. The signal VC0MP and the signals VD0WN RAMP and Vup-RAMP are superimposed on each other to illustrate the operation of the comparators CMP 1 and CMP2. When the signal Il〇ad jumps from INORM to IHIGH, the signal vc〇Mp will temporarily increase, and the signal Iavg will also increase, resulting in early triggering of the pwM signal. Figure 17 shows a schematic diagram of a dual-edge modulator circuit 1700 implemented in accordance with another embodiment. The double-edge modulator circuit 17A includes a triangular ramp generator 1 701 and a sensing and adjusting circuit 丨7〇3. In one embodiment, 22 201021389 the dual-edge modulator circuit 1700 replaces the functional blocks 401, 403, 405, and 413 of the double-edge modulator circuit 400. The triangular ramp generator 1701 generates a periodic triangle. The ramp voltage T2, which replaces the triangular ramp signal τ supplied to the inverting input of the comparator 407, is shown. The signal c is generated by the error amplifier 4〇9 in a manner substantially identical to that previously described and is provided to the non-inverting input of the comparator 407. The comparator 407 generates a signal D that is supplied to the CTL input of the pulse timing circuit 411, and the pulse timing circuit 411 generates the Pwm signal at its output. The triangular ramp ❹ generator 1701 also generates a clock signal CLK that is supplied to the CK input of the pulse timing circuit 411. The pulse sequence circuit 4 11 generates a PWM signal based on the signal D for controlling the output voltage of the DC-DC power regulator, and is configured to ensure that each cycle of the clk signal is only One pulse. Comparator 4〇7 and pulse sequential circuit 411 together form a pulse generator circuit to generate a PWM pulse signal for controlling the output of the voltage regulator. The sensing and adjusting circuit i 7〇3 senses the signal Iload and generates a current modulation signal IADJ, which will be used to adjust or adjust the magnitude of the triangular ramp voltage T2'. The sensing and adjusting circuit 1 703 basically replaces the current sensing circuit 4 13 , wherein the nickname IADJ serves as an adjustment signal, and the operation mode is the same as the signal adj. However, the signal IADJ is provided to the triangular ramp generator 17〇. A point inside 1 to adjust the size of T2, further explained below. A voltage source VCC is provided to a switching terminal of a normally open single pole single throw (SPST) switch SW1, the other switching terminal of which is coupled to the negative terminal of current source 1702 for generating current 2ICH. . 23 201021389 The positive terminal of current source 1 702 is coupled to node 1704 for generating the triangular ramp voltage T2. Node 1704 is further coupled to one end of capacitor COSC, coupled to the negative terminal of another current source 1706 for generating current ICH, coupled to the non-inverting input of comparator COMPH, coupled to another comparator COMPL The inverting input is coupled to the inverting input of comparator 407. The positive terminal of current source 1706 and the other end of capacitor COSC are coupled to GND. The negative terminal of voltage source 1708 is coupled to GND and its positive terminal provides a voltage VTHH to one end of resistor R1. The other end of resistor R1 is coupled to node 1710 which produces a voltage © VTHHM and is coupled to the inverting input of comparator COMPH. The negative terminal of the other voltage source 1712 is coupled to GND and its positive terminal provides a voltage VTHL to the non-inverting input of the comparator COMPL. The output of the comparator COMPH is supplied to the set input of the SR flip-flop FF3, and the output of the comparator COMPL is supplied to the reset input of the SR flip-flop FF3. The non-inverting Q output of FF3 produces a signal CLK which is provided to the CK input of pulse timing circuit 411. The signal CLK toggles between the digital levels at the same frequency as the triangular ramp signal T2. The 反向 reverse Q output of FF3 (indicated by "Qbar" in the figure with a short line above the reverse "Q" output) is supplied to the control input of switch SW1. The load current Iload shown in the figure is provided through current sensor 1705, which produces a current sense voltage VCS that is proportional to I LOAD . Signal I LOAD may be the load current itself or other signal related to or affected by the load current, such as the inductor current signal. The VCS is provided to the non-inverting input 24 201021389 of the amplifier 1707; to an input of the resistor R2; and to the positive control input of the voltage controlled current source 1714, which controls the negative control input of the current source 1714 Will be coupled to GND. Current source 1714 has a negative output terminal that is coupled to node 1709 and a positive output terminal that is coupled to GND. Current source 1714 draws a proportional current IPADJ from node 1709 to GND, where current IPADJ is proportional to VCS and VCS itself is proportional to the level of Iload. The other end of R2 will be coupled to capacitor C2 and coupled to the inverting input of amplifier 1707. The other end of capacitor C2 will be coupled to GND, and the output of amplifier 1707 will generate a load transient signal LT. The LT will be provided to the non-inverting input of the comparator COMPTR+ and will be provided to the inverting input of the other comparator COMPTR-. The negative terminal of voltage source 1716 is coupled to GND and its positive terminal provides a voltage VTRTH+ to the inverting input of comparator COMPTR+. The positive terminal of another voltage source 1718 is coupled to GND, while its negative terminal provides a non-inverting input of voltage VTRTH- to comparator COMPTR-. The output of the comparator COMPTR+ is coupled to the set input of the SR flip-flop FF1, and the output of the comparator COMPTR- is coupled to the set input of the other SR flip-flop FF2. The output of the comparator C0MPH is coupled to the reset input of both FF1 and FF2. The non-inverting Q output of FF1 is provided to an input of a dual input OR gate 1 7 11 . The non-inverting Q output of FF2 will be provided to the control input of a normally open SPST switch SWL and will be provided to the other input of the OR gate 1 7 11 . The switch terminal of switch SWL (which closes when the control input is logic high) is coupled between VCC and the negative terminal of current source 1 720, and the positive terminal of current source 1720 is coupled to node 25 201021389 point 1709. Current source 1720 provides a current IPADJOFFS to node 1709 when switch SWL is closed. The output of the OR gate 1711 will be coupled to the control input of another normally open SPST switch SWH, the switching terminal of the switch SWH will be coupled between nodes 1710 and 1709, and will close when the control input is logic high. . As further explained below, the voltage of VTHHM typically has the same voltage level as VTHH. When the switch SWH is closed, the current IADJ (shown in the inflow node 1710 in the figure) adjusts the level of VTHHM to modulate the peak value or upper limit amplitude of T2. As further explained below, the SR flip-flops FF1 and FF2, the current sources 1714 and 1720, the switches SWL and SWH, and the OR gate 1711 together form an adjustment signal generating circuit that controls the signal in response to the output load transient. IADJ, used to adjust the size of T2. In response to a positive load transient that causes LT to rise above the positive threshold voltage VTRTH+, the upper threshold voltage of T2 will decrease by an amount proportional to the increase in Iload. A decrease in the upper threshold voltage of T2 causes the comparator COMPH to trigger earlier, which pulls the next PWM pulse forward to appear at an earlier time in the cycle. The triggering action of COMPH also resets FF 1 so that the threshold change is limited to one cycle. In response to a negative load transient that causes LT to fall negatively below the negative threshold voltage VTRTH-, the upper threshold voltage of T2 increases the offset value determined by IPADJOFFS and is reduced by the amount of the decrement of IL0AD. An increase in the upper threshold voltage of T2 causes the comparator COMPH to trigger later, which will push the next PWM pulse extrapolated to appear at a later time in the cycle. The triggering action of COMPH also resets FF2 so that the threshold change is limited to one cycle. 201021389 The operation of the double-edge modulator circuit 1700 will be described with reference to FIG. 18. FIG. 18 includes a first timing diagram of IL0AD with respect to time, a second timing diagram of triangular ramp voltage T2 with respect to time, and a PWM signal. A third timing diagram relative to time. The timing diagram for T2 also illustrates the voltage levels of VTHHM, C, and VTHL using dashed lines to account for the operation of the dual-edge modulator circuit 1700. For the sake of clarity, the compensation voltage C shown in the figure is at a constant level, where it should be understood that the compensation voltage C will generally vary with load conditions. At the beginning, the load current Iload is at the normal steady state level, and the triangular ramp voltage T2 rises and falls between the threshold voltage levels VTHL and VTHH. When IADJ is zero or negligible, such as during steady state load conditions, then VTHHM will be substantially equal to VTHH. When switch SW1 is open, capacitor COSC is discharged by current ICH, causing T2 to fall from VTHH toward VTHL. When T2 drops to approximately voltage level VTHL, comparator COMPL switches and resets FF3, which closes switch SW1. The current 2ICH, which is twice the level of the ICH, charges the capacitor COSC at a current level of approximately ICH (2ICH-ICH) such that T2 will rise from VTHL towards VTHH at a constant rate. When T2 reaches the voltage level of VTHH, the comparator COMPH switches and sets FF3, which opens the switch SW1. During normal steady-state load conditions or when the output load changes slowly, the operation is repeated in this manner, where T2 ramps up between the critical voltage levels VTHL and VTHH. During each cycle, when T2 falls below the voltage level of C, the PWM signal is judged to be high. When T2 rises below the voltage level of C, the PWM signal is reset back. Low level. 27 201021389 Resistor R2 and capacitor C2 together form a low pass filter such that the inverting input of amplifier 1707 is delayed relative to its non-inverting input. In this way, the level of the signal LT will change in response to a transition of VCS (which will be proportional to Iload). The voltages VTRTH+ and VTRTH- are critical voltages that define a voltage range in which the LT can be changed without affecting the normal operating voltage range. A relatively slow change in Iload can result in slight changes in LT. However, a relatively fast and relatively large change in ILOAD results in a corresponding change in VCS, causing LT to briefly jump out of the normal operating range between the threshold voltages VTRTH+ and VTRTH-. In this manner, the amplifier circuit including the amplifier 1707 and the RC filter having R2 and C2, together with the comparator circuit COMPTR+/-, constitute a load transient critical circuit' for monitoring the output load transient.

At approximately time t1, the load current Iload quickly jumps to the high current level indicated by Ihigh. In response to this output load transient, vcs will increase and amplifier 1707 will respond by asserting LT to a high level. In this case, the Iload transition is so high that LT will rise above the upper threshold voltage VTRTH+, causing the comparator COMPTR+ to toggle state and set FF1. The OR gate 1711 will assert its output to a high level in response to the high level output of FF1 and will close the switch SWH. The output current IPADJ of voltage controlled current source 1714 (which will be proportional to the higher level of ILOAD) will result in a negative IADJ current for pulling current from node 1710 via resistor R1. The IPADJ current flowing through resistor R1 will reduce the voltage level of VTHHM below the voltage level of VTHH as shown. The relative voltage variation of VTHHM will depend on the size of IPADJ, which will depend on the size of VCS 201021389 and This will depend on the size of the Iload. When T2 reaches the lowered VTHHM voltage level, the comparator COMPH switches its output to a high level and sets FF3 early to open the switch SW1 early in the current PWM cycle. In this way, Τ2 will arrive at a lower sized spike early in the loop and begin ramping down to a lower level as indicated at 801. Further, Τ2 will arrive at C earlier in the current cycle, which will cause the next PWM pulse to adaptively shift to the earlier time in the cycle shown at 1 802 in response to the increased load transient. At the office. You can use the ® standard limit technique to limit the movement of this upper threshold to stay above VTHL. The comparator COMPH also resets FF1 at time t2 so that the switch SWH will re-open, causing VTHHM to return to the voltage level of VTHH, while amplifier 1 707 will adjust according to the transient and pull LT back to VTRTH. - Inside the critical voltage range between VTRTH+. Therefore, the sense and adjustment circuit 1 703 is actually reset back to normal operation and the triangular ramp voltage T2 and the PWM signal are returned to normal operation to limit the load transient response to a single cycle. ® At approximately time t3, the load current IL0AD will quickly fall back to the normal current level. Inorm 0 In response to this negative load transient, amplifier 1 707 will determine that LT is below the negative threshold voltage VTRTH- and cause comparator COMPTR- to set FF2. It should be noted that in the embodiment shown in the figure, VTRTH- is a negative threshold below GND such that LT will fall negatively and fall below VTRTH- to trigger comparator COMPTR-. After the response, FF2 will close both switches SWL and SWH. A lower level of IL0AD will reduce VCS, which will lower the current level of the IPADJ. Since both switches SWL and SWH are closed, 29 201021389 current IPADJOFFS will be provided to node 1710 to be shifted by current IPADJ such that IADJ=IPADJOFFS-IPADJ. Current IADJ is injected into node 1710 via resistor R1 to increase the voltage of VTHHM as shown at time t3, where the voltage increase is based on the current level of IADJ and the resistance of R1. The rising ramp of the triangular ramp voltage T2 passes through the normal upper threshold of VTHH until it reaches the boosted south voltage of VTHHM at time t4. Since the T2 rises at a strange rate, it takes a long time to reach the increased voltage of the VTHHM, which causes a temporary increase in the size of T2 as shown at 1803. At time t4, when T2 reaches the voltage level of ◎ VTHHM, the comparator COMPH switches to initiate a negative ramp of T2. Τ2 will eventually drop to the voltage level of C to initiate the next PWM pulse. In this way, the increased size of Τ2 will delay the next PWM pulse as indicated at 18〇4, and the operation will return to normal until the next load transition. Also at time t4, the comparator COMPU also resets FF2 to limit the load transition response to a single loop. The double-edge modulator circuit 1700 modulates the amplitude of the ramp signal (triangle or zigzag) in a single cycle after a load transient, wherein the amplitude is lower in one cycle when Load q is increased, and When Il〇ad falls, the amplitude will be larger in one cycle. Since the compensation signal C is compared with the ramp signal to generate the PWM pulses, the adaptive amplitude change shifts the next PWM pulse. Since the load transient response is limited to one cycle, subsequent PWM pulses will also have a time offset to maintain the same pulse rate. In general, the pulse signal is adaptively offset over time without having to increase the pulse. These pulses are pulled in the positive load transient (load condition increase) 30 201021389 and will be pushed in the negative position. In this way, μ (the load condition is degraded) is extrapolated. In this way, the operating frequency is only affected in one cycle, and returns to normal after the parent-transient. In response to the positive load slip, the next: WM pulse will be offset w now at an earlier time, causing the operation to increase briefly. Similarly, in response to a negative load transient, the next MM pulse will be offset and appear at a later time, causing the operating frequency to drop briefly. Because the transient response in any-case is limited to _ loops,

Therefore, the operating frequency will be normal immediately, so that the change in the total operating rate can be ignored. The forward/outward push action is triggered by the load transient critical circuit, and if the load change is greater than the preset limit, the load transient critical circuit will initiate the critical value change of the cycle. In a tenth embodiment, the preset limit is maintained between 1 〇 and 5 〇 % of the full load condition. The relative offset of the pwM pulse in response to the load transient is adjusted based on the relative magnitude of the transient. For example, the lower the load current during a positive load transient, the lower the level of the IPADJ, which reduces the VTHHM derating in response to an increase in load, thereby reducing the relative offset of the next PWM pulse. Similarly, the higher the load current during the negative load transient, the higher the level of the IPADJ current, and thus the increase in VTHHM', thereby reducing the delay offset of the next pwM pulse. If the transient occurs during the on-time of the PWM, the dual-edge modulator circuit 1700 does not automatically lose the pulse and spread the pulse width to facilitate the load transient response β. Although the dual edge configuration is explained herein, The concept can easily be adapted for use in leading or trailing edge modulation systems. Although the load 31 201021389 current is sensed to represent the output load condition, other output signals, such as output voltage or the like, can also be sensed. Although the ramp generator 17〇1 generates a triangular ramp voltage, it can also generate alternative types of ramp signals, such as sawtooth signals, up-slope signals, down-slope signals, and the like. Although the adjustment signal explained in this document is a current signal, alternative types of signals such as voltage or timing signals and the like can be used. Although the present invention has been described in considerable detail with reference to certain preferred embodiments of the invention, the invention may be For example, the delay adjustment of the clock signal or the offset voltage added to the ramp signal and/or the compensation signal can also output operational parameters other than the load current (eg, input voltage, output current, and/or output). The differential value of the voltage (for example, transient events or similar events), etc.). The present invention can also be applied to digital modulators in which analog functions (e.g., ramp, error, compensation, etc.) are replaced by digital calculations and/or algorithms and similar digital functions. The present invention can be applied to a modulator that uses a digital controller (e.g., to adjust the delay time, adjust the clock signal, adjust the timing of the start of the PWM pulse to adjust the PWM duty cycle based on the calculation result, etc.).人士 Those skilled in the art will appreciate that they can easily use the concepts and specific embodiments disclosed herein to achieve the purpose of designing or modifying other structures to provide the same use as the present invention, but not Without departing from the spirit and scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS The advantages, features, and advantages of the present invention will become more apparent from the description and accompanying drawings in which: FIG. Timing diagram of the operation mode of the pulse width modulation pulse localization technique; FIG. 2 is not a simplified block diagram of the trailing edge modulator circuit according to the present invention; FIG. 3 is not the trailing edge modulation of FIG. FIG. 4 is a simplified block diagram of a dual-edge modulator circuit implemented in accordance with an embodiment of the present invention; FIG. 5 is not a timing sequence of the dual-edge modulator circuit of FIG. Figure 6 is a schematic diagram of a double-slope double-edge pulse width modulation modulation circuit according to the embodiment described in the prior patent application; Figure 7 is a double oblique wave double of Figure 6. Operation timing diagram of the edge-width modulation modulation circuit, which illustrates the long blank period problem in the double-slope dual-edge pulse modulation technique of the -4 phase system; FIG. 8 is not adapted according to an embodiment of the present invention. Block diagram of a pulse width modulation pulse positioning system, which can be applied To the double-slope double-edge pulse width modulation modulation circuit; FIG. 9 is a pulse width modulation pulse positioning system for performing an exemplary embodiment of the adaptive pulse width modulation pulse positioning system of FIG. Schematic diagram, FIG. 10 is an operational timing diagram of the adaptive pulse width modulated pulse positioning system of FIG. 9 for a -4 phase system; FIG. 11 is an adaptive pulse width modulation according to another embodiment of the present invention. A block diagram of a variable pulse positioning system that can be applied to a double-slope double-edge pulse width modulation modulation circuit; 33 201021389 FIG. 12 is an adaptive pulse width modulation pulse positioning system according to another embodiment of the present invention. Block diagram, which can be applied to a double ramp dual edge pulse width modulation modulation circuit; FIG. 13 is an adaptive pulse for performing an exemplary embodiment of the adaptive pulse width modulated pulse positioning system of FIG. A schematic diagram of a wide-tuning pulse positioning system; Figure 14 is an operational timing diagram of the adaptive pulse width modulation pulse positioning system of Figure 13 for a 4-phase system; Figure 15 is shown for generating Figure 6 Ramp-wave double-edge pulse width modulation A block diagram of a downward ramp generator of a signal to illustrate an adaptive pulse width modulation pulse localization system in accordance with another embodiment of the present invention; FIG. 16 is an adaptation of the downward ramp generator of FIG. FIG. 17 is a schematic diagram showing an operation of a pulse width modulation pulse positioning system; FIG. 17 is a schematic diagram of a double-edge modulator circuit according to another embodiment; and FIG. 18 is a double-edge modulator circuit shown in FIG. A timing diagram of the operation. [Main component symbol description] 101, 105, 107, 111: pulse 1〇3, 113: arrow 2〇〇: trailing edge modulator circuit 201: timing source 203: delay function 205: ramp generator 34 201021389 207: Pulse width modulation comparator 209: error amplifier 2 1 1 : pulse timing circuit 2 1 3 : current sensing block 400: double edge modulator circuit 401: timing source 403: delay function 405: triangular ramp generator Ο 407 : Pulse width modulation comparator 409 : Error amplifier 4 11 : Pulse timing circuit 4 1 3 : Current sensing circuit 6 00 : Double ramp double edge pulse width modulation modulation circuit 601 : Setting - reset (SR) positive Counter 603: Timing Source 605: Leading Edge Ramp Generator® 607: Trailing Edge Ramp Generator 701: Dotted Lines 800, 1 100, 1200, 13 00: Adaptive Pulse Width Modulation Pulse Positioning System 801: Function Block 803 : Adder 9 00 : Pulse width modulation pulse positioning system 1101 : Adder 1201 : Function block 35 201021389 1203 : Adder 1500 : Down ramp generator 1501 : Controlled current slot 1502 : Node 1503 : Diode 1505 , 1507: voltage source 1700: double-edge modulator circuit 1701: triangular ramp generator 1702, 1706, 1714, 1 720: current source 1703: sensing and adjusting circuit 1704, 1709, 1710: node 1705: current sensor 1707: amplifier 1708, 1712, 1716, 1718: voltage source 1711: dual input OR gate A, CLK: clock signal AD: Delayed pulse signal ADJ: Adjust signal B: Ramp signal C: Compensation signal CK: Clock input CMP1: Down ramp comparator CMP2: Up ramp comparator COMPH, COMPL, COMPTR+, COMPTR-: Comparator 201021389 _ C0SC, C1: Capacitor CTL: Control input D: Signal FF1-FF3: SR Positive and negative GND: Ground IADJ: Current modulation signal ICH, IPADJOFFS: Current Iavg: Average current _ I HIGH : 13⁄4 Current level

Iload : Load current Inorm : Normal level Iphase . Phase current LT : Load transient signal Rhi : South ramp level Rlo : Low ramp level Rl5R2 : Resistor ® SW, SWH, SWL, SW1 : Single pole single throw switching T, T2: Triangular ramp signal Vc〇MP: Compensation signal VCS: Current sense voltage VC1 • Adjusted/modified compensation signal VC2: Adjusted compensation signal Vd〇WN_RAMP: Down ramp signal V minj Vmax : Min/Max ramp voltage 37 201021389 V0, V02 : Offset voltage VR: Adjusted ramp signal VTHL, VTHH, VTHHM: Threshold voltage VTRTH+, VTRTH-: Voltage

VlJP RAMP: Up ramp signal

38

Claims (1)

201021389 ' VII. Patent application scope: 1. An adaptive pulse positioning system for a voltage converter, the voltage converter provides an output voltage, and the adaptive pulse positioning circuit comprises: an adjustable ramp generator, Having an adjustment input and providing a periodic ramp voltage, the magnitude of the periodic ramp voltage being adjusted based on the adjustment input; a pulse generator circuit that receives the ramp voltage and produces a complex number a pulsed pulse signal for controlling the output voltage of the voltage controller based on the ramp voltage; and a sensing and adjusting circuit for sensing the output load of the voltage converter a signal of the state, and providing an adjustment signal to the adjustment input of the adjustable ramp generator to adaptively shift the pulse signal in time in response to the output load transient, without the need for the plurality of pulses Add any pulse in it. 2. The adaptive pulse positioning system according to the application of the patent scope, wherein the adjustable ramp generator comprises a triangular ramp generator for providing a beta angle ramp voltage, and the ramp angle voltage is The lower limit threshold voltage and the upper limit threshold voltage are raised and lowered, and wherein the adjustment input adjusts the upper limit threshold voltage. An adaptive pulse positioning system according to claim 2, wherein the sensing and adjusting circuit has a turn-in coupled to the adjustable ramp generator and wherein the sensing and adjusting circuit is only in the oblique The upper limit threshold is adjusted in one cycle of the wave voltage. 4. An adaptive pulse positioning system according to the scope of the patent application, wherein 39 201021389 the pulse generator circuit comprises: a comparator that compares an error voltage and the ramp voltage and generates a one for indicating a comparison result a pulse control signal; and a pulse sequential circuit having: a first input for receiving the There is only one pulse in the loop. 5. The adaptive pulse positioning system of claim </ RTI> wherein the sensing and adjusting circuit comprises: a sensor that senses an output load signal and provides a proportional to the wheel load signal a load transient circuit; a load transient circuit having a wheel input for receiving the sense voltage and an output for providing a load transient sense voltage, the load transient sense voltage indicating Transient of the output load signal; a comparator circuit that compares the load transient sense voltage with a positive threshold voltage and a - (four) boundary voltage, if the load transient senses that the electrical house reaches the positive threshold voltage, The comparator circuit provides a first control signal, and if the load transient sensing voltage reaches the negative threshold voltage, the comparator circuit provides a second control signal; and an adjustment signal generating circuit is provided The first control signal provides the adjustment signal for reducing the magnitude of the ramp voltage, and when the second control signal is provided, the adjustment signal is provided to increase the slope The size of the wave voltage. 201021389 6. The adaptive pulse positioning system of claim 5, wherein the sensor comprises a current sensor that senses an output load current of the voltage converter. 7. The adaptive pulse positioning system of claim 5, wherein the load transient circuit comprises: a low pass filter having an input for receiving the sense voltage and having an output; An amplifier having: a first input for receiving the sense voltage; a second input 'which is coupled to the output of the low pass filter; and an output for providing the load transient sense Measure the voltage. 8. The adaptive pulse positioning system of claim 5, wherein the adjustable ramp generator comprises a triangular ramp generator for providing a triangular ramp voltage, the triangular ramp voltage being at a lower limit The voltage and the upper limit threshold voltage are raised and lowered, and when the first control signal is provided, the adjustment signal decreases the upper limit threshold voltage, and when the second control signal is provided, the adjustment signal increases the upper limit threshold Voltage. [9] The adaptive pulse positioning system of claim 8 wherein, when the first control signal is provided, the adjustment signal generating circuit determines the adjustment signal proportional to the sensing voltage. When the second control signal is ready, the adjustment signal generating circuit determines that the adjustment signal bit is at a bias=level, and the offset level is adjusted to be proportional to the sensing voltage. A method for controlling a pulse for adaptively locating an output voltage of a pulse width modulation voltage regulator, the method comprising: 41 201021389 generating a periodic ramp voltage; comparing the ramp voltage and the - error voltage for Providing a plurality of pulses in a continuous cycle of the ramp voltage; sensing a signal indicative of a load transient of the voltage regulator's wheel load; and adjusting the ramp voltage in response to the load transient In order to adaptively offset the plurality of pulses in time without adding any pulses. 11^ The method of claim Π)) wherein the sensing is used to indicate that one of the load transients of the output load of one of the voltage regulators includes the sensed output load current. 12. The method of claim 1 (), wherein the generating a ramp voltage comprises generating a ramp voltage between a first threshold voltage and a second threshold voltage and wherein adjusting the ramp voltage comprises At least one of the first threshold voltage and the second threshold voltage is adjusted in at least one cycle of the ramp voltage. ❹ 13. The method of claim 1, wherein the generating a ramp voltage comprises generating a triangular tilt that will rise and fall between a lower limit, a r丨艮 threshold voltage, and an upper limit voltage. , ^ ^ * wave voltage, and wherein the ramp voltage is adjusted to at least the ramp voltage of the ramp voltage to adjust the upper threshold voltage. The method of _month patent scope 帛13, wherein the sensing is used to indicate the voltage regulator - the rim check... one of the load transients of the output load includes the Russian test for indicating the load A positive load transient, and where the boundary voltage is adjusted. The method of claim 13, wherein the sensing is used to indicate a load transient of one of the output voltages of the voltage regulator, wherein the upper limit is reduced by at least one cycle of the ramp voltage. Included, 丨; a negative load transient indicating a reduced load, and wherein the adjusting the ramp voltage comprises increasing the upper threshold voltage in at least a cycle of the ramp voltage. 1 6. The method of claim 2, wherein the sensing one of a load transient for indicating an output load of the voltage regulator comprises: a sensing-output signal-change; a change in the output signal and a threshold value; and a load transient when the change in the output signal reaches the threshold. 17. The method of claim 10, wherein the sensing one of a load transient for indicating an output load of the voltage regulator comprises: sensing a change of an output signal; comparing the output a change in the signal and a positive threshold and a negative threshold; and a load transient when the change in the output signal reaches either of the positive threshold and the negative threshold. 18. The method of claim 1, wherein the adjusting the ramp voltage comprises adjusting the ramp voltage in only one cycle. 19. The method of claim 1, wherein the adjusting the ramp voltage comprises adjusting the ramp power based on a relative amount of the load transient. 2. The method of claim 10, wherein: generating a periodic ramp voltage comprises generating a ramp voltage between a lower threshold voltage and an upper threshold voltage; and wherein the adjusting the slope The wave voltage includes: decreasing the upper limit threshold voltage by an amount proportional to the one state; and increasing the negative load to temporarily increase the upper limit threshold voltage by an offset value subtraction and representation - load transient of the load is proportional One amount. G decline, schema. (such as the next page) 44