201021050 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種内容可定址記憶體及用於内容可定址 記憶體之資料搜尋比對電路。 【先前技術】 習知技術關於内容可定址記憶體的文獻，研究重點不外 乎是如何提高内容可定址記憶體的搜尋比對速度，並且降 低其功率消耗。由許多研究中發現，大部份都在探討内容 可定址記憶體單元架構（參考先前技術文獻[1])，和内容可 定址記憶體的搜尋比對資料的電路與方法（參考先前技術 文獻[2]及[3])，以及内容可定址記憶體在不同操作電壓下 對其效能的影響（參考先前技術文獻[4])。相關先前技術參 考美國專利編號：US7,339,810(March 4，2008)、 US7,099，170(August 29，2006)、US6,958,925(October 25, 2005)、US6,898,661(May 24，2005)、US6,845,024(January 18，2005)，其技術與上述文獻大致相同。這些先前習知技 術未能在資料搜尋比對後進行電路關閉，故無法進一步節 省電源消耗。 因此，有必要提供一種創新且具進步性的内容可定址記 憶體及用於内容可定址記憶體之資料搜尋比對電路，以解 決上述問題β 先前技術文獻： [1 ] I. Arsovski, T. Chandler, and A. Sheikholeslami, "A ternary content-addressable memory (TCAM) based on 4T static storage and including a current-race sensing scheme，" «/· 133587.doc 201021050201021050 IX. Description of the Invention: [Technical Field] The present invention relates to a content addressable memory and a data search comparison circuit for content addressable memory. [Prior Art] In the literature on content addressable memory, the research focus is not only on how to improve the search speed of content addressable memory, but also to reduce its power consumption. It has been found in many studies that most of them are exploring content-addressable memory cell architectures (refer to the prior art literature [1]), and circuits and methods for searching content comparison data for content-addressable memory (refer to the prior art literature [ 2] and [3]), and the effect of content-addressable memory on its performance at different operating voltages (refer to prior art document [4]). Related prior art references US Patent Nos.: US 7,339,810 (March 4, 2008), US 7,099,170 (August 29, 2006), US 6,958,925 (October 25, 2005), US 6,898,661 (May 24, 2005), US 6,845,024 (January 18, 2005), the technique of which is substantially the same as the above document. These prior art techniques failed to close the circuit after the data search was performed, so that power consumption could not be further saved. Therefore, it is necessary to provide an innovative and progressive content addressable memory and data search comparison circuit for content addressable memory to solve the above problem. β Prior Art Literature: [1] I. Arsovski, T. Chandler, and A. Sheikholeslami, "A ternary content-addressable memory (TCAM) based on 4T static storage and including a current-race sensing scheme," «/· 133587.doc 201021050
Circuits, vol. 38, no. 1, pp. 155-158, Jan. 2003.Circuits, vol. 38, no. 1, pp. 155-158, Jan. 2003.
[2] N. Mohan, W. Fung, D. Wright, and M. Sachdev, "Match line sense amplifiers with positive feedback for low-power content addressable memories," IEEE Custom Integrated Circuits Conf., pp. 297-300, Sept 2006.[2] N. Mohan, W. Fung, D. Wright, and M. Sachdev, "Match line sense amplifiers with positive feedback for low-power content addressable memories," IEEE Custom Integrated Circuits Conf., pp. 297- 300, Sept 2006.
[3] P. T. Huang, W. K. Chang, and W. Hwang, "Low power pre-comparision Scheme for NOR-type 10T content addressable memory," in Proc. of IEEE Conf. on Circuits and Systems, pp. 1301-1304, Dec. 2006.[3] PT Huang, WK Chang, and W. Hwang, "Low power pre-comparision Scheme for NOR-type 10T content addressable memory," in Proc. of IEEE Conf. on Circuits and Systems, pp. 1301-1304 , Dec. 2006.
[4] H. Noda, K. Inoue, M. Kuroiwa, F. Igaue, K. Yamamoto, H. J. Mattausch, T. Koide, A. Amo, A. Hachisuka, S. Soeda, I. Hayashi, F. Morishita, K. Dosaka, K. Arimoto, K. Fujishima, K. Anami, and T. Yoshihara, MA cost-efficient high-performance dynamic TCAM with hierarchical searching and shift redundancy architecture," IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 245-253, Jan. 2005. 【發明内容】 本發明提供一種内容可定址記憶體，其包括：一資料暫 存器、一資料搜尋比對電路及一位址編碼器。該資料暫存 器用以接收至少一欲搜尋之資料訊號。該資料搜尋比對電 路用以接收該欲搜尋之資料訊號，該資料搜尋比對電路包 括複數個資料搜尋比對列，每一個資料搜尋比對列包括： 複數個具有雙端比較線輸出之記憶元件及一差動輸入感測 電路，該等具有雙端比較線輸出之記憶元件用以儲存資料 訊號，並比對該欲搜尋之資料訊號及所儲存之資料訊號是 否相同，輸出雙端比較線至該差動輸入感測電路，該差動 輸入感測電路依據雙端比較線，輸出一比對訊號，並關閉 133587.doc 201021050 該差動輸入感測電路之充電路徑。該位址編碼器用以依據 該等比對訊號，輸出一位址訊號。 本發明另提供一種用於内容可定址記憶體之資料搜尋比 對電路’其包括：複數個資料搜尋比對列，用以接收至少 一欲搜尋之資料訊號，每一個資料搜尋比對列包括：複數 個具有雙端比較線輸出之記憶元件及一差動輸入感測電 路’該等具有雙端比較線輸出之記憶元件用以儲存資料訊 號，並比對該欲搜尋之資料訊號及所儲存之資料訊號是否 相同’輸出雙端比較線至該差動輸入感測電路，該差動輸 入感測電路依據雙端比較線，輸出一比對訊號，並關閉該 差動輸入感測電路之充電路徑。 本發明之該差動輸入感測電路可同時對字元線上所有記 憶元件做感測，以達到快速之搜尋比對速度，並且進行資 料搜尋比對時，不管是否搜尋比對到符合之資料，皆會自 動關閉該差動輸入感測電路之充電路徑，以節省功率消 耗。 【實施方式】 參考圖1，其顯示本發明内容可定址記憶體之示意圖。 本發明之内容可定址記憶體100包括：一資料暫存器lOi、 一資料搜尋比對電路102及一位址編碼器103。該資料暫存 器用101以接收至少一欲搜尋之資料訊號（Search_data)。該 資料暫存器101依據該欲搜尋之資料訊號（Search_data)，輸 出複數個位元線組，每一位元線組具有一第一位元線 (BL<i>)及一第二位元線（BLB<i>)。 133587.doc 201021050 該資料搜尋比對電路102用以接收該欲搜尋之資料訊 號。該資料搜尋比對電路1 02包括複數個資料搜尋比對列 112，每一個資料搜尋比對列112包括：複數個具有雙端比 較線輸出之記憶元件114及一差動輸入感測電路115，該等 具有雙端比較線輸出之記憶元件114用以儲存資料訊號， 並比對該欲搜尋之資料訊號及所儲存之資料訊號是否相 同，輸出雙端比較線（ML<i>、SML<i>)至該差動輸入感測 電路115，該差動輸入感測電路115可同時對字元線上所有 β β - 記憶元件114做感測’以達到快速之搜尋比對速度，該差 動輸入感測電路115依據雙端比較線，輸出一比對訊號， 並關閉該差動輸入感測電路115之充電路徑，以節省功率 消耗。該位址編碼器1 〇3用以依據該等比對訊號，輸出一 位址訊號（Match一address) ’將搜尋比對符合資料之所在位 址訊號輸出。 參考圖2,其顯示本發明具有雙端比較線輸出之記憶元 φ 件之示意圖。本發明具有雙端比較線輸出之記憶元件114 包括：一記憶單元201及一互斥閘型態比較電路2〇2。該記 憶單元201用以儲存一資料訊號Q，並與該第一位元線 (BLB<i>)及該第二位元線（BLB<i>)比較，輸出一第一節點 A1及一第二節點A2。在本實施例中，該記憶單元2〇丨為一 6-T靜態隨機存取記憶元件（sraM CELL)。 該互斥閘型態比較電路202包括一第一 N型電晶髏 NM201、一第二N型電晶及一第電晶體 NM203。其中’該第一 N型電晶體NM2〇l之閘極連接至該 133587.doc • 9 - 201021050 第一節點A1，其源極連接至該第一位元線（BL<i>)，其汲 極耦接至該第三N型電晶體NM203之閘極》該第二N型電 晶體NM202之閘極連接至該第二節點A2，其源極連接至該 第二位元線（BLB<i>)，其汲極耦接至該第三N型電晶體 NM203閘極。該第三N型電晶體NM203之源極及汲極分別 連接至雙端比較線（ML<i>、SML<i>)，雙端比較線包括一 第一比較線（ML<i>)及一第二比較線（SML<i>)，依據該記 憶單元201之比對結果，控制該第三N型電晶體NM203是否 導通。當第一位元線（BL<i>)之輸入訊號等於資料訊號Q 時，則該第三N型電晶體NM203關閉；反之，當第一位元 線（BL<i>)之輸入訊號不等於資料訊號Q，則該第三N型電 晶體NM203導通。 參考圖3，其顯示本發明差動輸入感測電路之示意圖》 本發明差動輸入感測電路105包括一差動輸入電路301、一 正回授電路302及一選擇邏輯電路3 03。該差動輸入電路 301包括一第一充放電控制電晶體PM301、一第二充放電 控制電晶體NM303及一差動對電路。其中該第一充放電控 制電晶體PM301連接至該差動對電路，該差動對電路連接 至該第二充放電控制電晶體NM303，該差動對電路包括複 數個電晶體PM302、PM303、NM301、NM302，用以接收 該第一比較線（ML<i>)及該第二比較線（SML<i>)，輸出一 第三節點（KP)。 該正回授電路302包括一第三P型電晶體PM304、一第五 N型電晶體NM304、第六N型電晶體NM305及一反相電路 133587.doc -10· 201021050 304 »該第三P型電晶體PM304之源極連接至一電壓源，其 閘極耦接至一搜尋訊號（SEARCH)，其汲極耦接至該第三 節點（KP)。該第五N型電晶體NM3042汲極耦接至該第三 節點（KP)，其閘極耦接至該搜尋訊號（SEARCH)，其源極 耦接至該第六N型電晶體NM305之汲極。該第六N型電晶 體NM305閘極耦接至該反相電路304之一輸出端 (MATCHB)，其源極連接至一接地端。該反相電路304之輸 入端連接至該第三節點（KP)。 該選擇邏輯電路303包括一反相器307、一多工器308及 一第七N型電晶體NM306。其中該反相器307之輸入端連接 至該第六N型電晶體NM3 06之没極，其輸出端控制該多工 器307之一選擇端；該多工器307之二輸入端分別連接至一 接地端和一搜尋致能訊號（SEARCH—EN)，該多工器308之 輸出端為該搜尋訊號（SEARCH);該第七N型電晶艎NM306 之汲極耦接至該第六N型電晶體NM305之汲極，其閘極連 接至一反相搜尋致能訊號(SEARCH_EN )，其源極連接至 9 一接地端。 在本實施例中，該第一充放電控制電晶體PM301為一 P 型電晶體，其源極連接至一電壓源，其閘極耦接至該反相 電路302之輸出端（MATCHB)，其汲極耦接至該差動對電 路。該第二充放電控制電晶體NM303為一 N型電晶體，其 汲極耦接至該差動對電路，其閘極耦接至該多工器308之 輸出端（SEARCH)，其源極耦接至該第一比較線（ML<i>)。 在本實施例中，該差動對電路包括一第一P型電晶體 133587.doc 201021050 PM302、一第二P型電晶體PM303及二個N型電晶體 NM301、NM302。該第一P型電晶體PM302之源極及該第 二P型電晶體PM303之源極連接，並連接至該第一充放電 控制電晶體PM301之汲極，該第一 P型電晶體PM302之閘 極耦接至該第一比較線（ML<i>)，該第二P型電晶體PM303 之閘極耦接至該第二比較線（SML<i>)，其汲極耦接至該第 三節點（KP)。 配合參考圖2及圖3，本發明差動輸入感測電路1〇5之電 路運作方式如下說明： 1. 搜尋之前’第一比較線（ML<i>)與第二比較線 (SML<i>)在搜尋前皆會先設定成低電壓準位，搜尋致能訊 號（SEARCH_EN)為邏輯零（低電壓準位），該第七N型電晶 體NM3 06導通，使反相器307之輸入端（SP)降為低電壓準 位，使得搜尋訊號（SEARCH)為邏輯零，第三P型電晶體 PM304導通，第五N型電晶體NM304關閉，使得第三節點 (KP)為邏輯一（高電壓準位），進而使得反相電路304之輸出 端（MATCHB)為邏輯零，第一充放電控制電晶體PM301導 通。 2. 當開始搜尋時，搜尋致能訊號（SEARCH_EN)為邏輯 一，則搜尋訊號（SEARCH)為邏輯一，使第二充放電控制 電晶體NM303開啟。 (1).如果輸入之欲搜尋資料訊號和字元線上記憶單元所 存之資料相符時，亦即當第一位元線（BL<i>)之輸入訊號 等於資料訊號Q時，則圖2之該第三N型電晶體NM203不導 133587.doc -12- 201021050 通，使得第一比較線（ML<i>)持續被充電而電壓值上升， 但第二比較線（SML<i>)電壓值保持零，第三節點（κρ)則維 持在高電壓準位’導致反相器307之輸入端（sp)電壓值一 直上升’由於該選擇邏輯電路303之該反相器3〇7及該多工 器308，使得搜尋訊號（SEARCH)降為低電壓準位，將第二 充放電控制電晶體NM303關閉，反相電路3〇4輸出端 (MATCHB)保持邏輯零。參考圖4，其顯示上述運作情形之 時域圖。 (2).如果輸入之欲搜尋資料訊號和字元線上記憶元件所 存之資料不相符時，亦即當第一位元線（BL<i>)之輸入訊 號不等於資料訊號Q，則圖2之該第三N型電晶體NM203導 通，使得第一比較線（ML<i>)和第二比較線（SML<i>)持續 被充電而電壓值上升，第三節點（KP)之電壓值則持續下 降，導致該正回授電路302之該第六N型電晶體NM305被啟 動，使得第三節點（KP)降為邏輯零，進而使反相電路304 輸出端（MATCHB)為邏輯一，將第一充放電控制電晶體 PM301關閉。參考圖5，其顯示上述運作情形之時域圖。 所以，不管比對結果是否相符，由於具有該正回授電路 302和該選擇邏輯電路303，感測時間皆很短暫，以達到快 速之搜尋比對速度；並且在感測結束後，該第一充放電控 制電晶體PM301或該第二充放電控制電晶體NM303關閉， 具有自動關閉第一比較線（ML<i>)的電流充電路徑的功 能，因此可降低功率消耗。 惟上述實施例僅為說明本發明之原理及其功效，而非限 133587.doc -13· 201021050 制本發明。因此，習於此技術之人士對上述實施例進行修 改及變化仍不脫本發明之精神。本發明之權利範圍應如後 述之申請專利範圍所列。 【圖式簡單說明】 圖1顯示本發明内容可定址記憶體之示意圖； 圖2顯示本發明具有雙端比較線輸出之記憶元件之示意 1^1 · 園， ❹ 圖3顯示本發明差動輸入感測電路之示意圖； 圖4顯示本發明之内容可定址記憶體對單一字元線上記 憶元件做資料搜尋比對到符合資料之模擬時域圖；及 圖5顯示本發明之内容可定址記憶體對單一字元線上記 憶το件做資料搜尋比對不到符合資料之模擬時域圖。 【主要元件符號說明】 100 101 102 103 112 114 115 201 202 301 302 ❿ 本發明之内容可定址記憶體 資料暫存器 資料搜尋比對電路 位址編碼器 資料搜尋比對列 具有雙端比較線輸出之記憶元件 差動輸入感測電路 記憶單元 互斥閘型態比較電路 差動輸入電路 正回授電路 133587.doc -14- 201021050[4] H. Noda, K. Inoue, M. Kuroiwa, F. Igaue, K. Yamamoto, HJ Mattausch, T. Koide, A. Amo, A. Hachisuka, S. Soeda, I. Hayashi, F. Morishita, K. Dosaka, K. Arimoto, K. Fujishima, K. Anami, and T. Yoshihara, MA cost-efficient high-performance dynamic TCAM with hierarchical searching and shift redundancy architecture, " IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 245-253, Jan. 2005. SUMMARY OF THE INVENTION The present invention provides a content addressable memory, comprising: a data register, a data search comparison circuit, and address coding Device. The data register is configured to receive at least one data signal to be searched. The data search comparison circuit is configured to receive the data signal to be searched. The data search comparison circuit includes a plurality of data search alignment columns, and each of the data search comparison columns includes: a plurality of memories having double-ended comparison line outputs. The component and a differential input sensing circuit, wherein the memory component having the double-ended comparison line output is used for storing the data signal, and outputting the double-ended comparison line according to whether the data signal to be searched and the stored data signal are the same. To the differential input sensing circuit, the differential input sensing circuit outputs a comparison signal according to the double-ended comparison line, and turns off the charging path of the differential input sensing circuit by 133587.doc 201021050. The address encoder is configured to output an address signal according to the comparison signals. The present invention further provides a data search comparison circuit for a content addressable memory, which includes: a plurality of data search comparison columns for receiving at least one data signal to be searched, and each data search comparison column includes: a plurality of memory elements having a double-ended comparison line output and a differential input sensing circuit. The memory elements having double-ended comparison line outputs are used to store data signals and compare the information signals to be searched and stored. Whether the data signal is the same 'output double-ended comparison line to the differential input sensing circuit, the differential input sensing circuit outputs a comparison signal according to the double-ended comparison line, and turns off the charging path of the differential input sensing circuit . The differential input sensing circuit of the present invention can simultaneously sense all memory elements on the word line to achieve a fast search comparison speed, and when searching for data, whether or not the search is matched to the matching data, The charging path of the differential input sensing circuit is automatically turned off to save power consumption. [Embodiment] Referring to Figure 1, there is shown a schematic diagram of an addressable memory of the present invention. The content addressable memory 100 of the present invention comprises: a data register 10Oi, a data search comparison circuit 102 and an address encoder 103. The data buffer 101 is used to receive at least one data signal (Search_data) to be searched. The data register 101 outputs a plurality of bit line groups according to the data signal (Search_data) to be searched, each bit line group having a first bit line (BL<i>) and a second bit Line (BLB<i>). 133587.doc 201021050 The data search comparison circuit 102 is configured to receive the data signal to be searched. The data search comparison circuit 102 includes a plurality of data search alignment columns 112. Each of the data search alignment columns 112 includes a plurality of memory elements 114 having double-ended comparison line outputs and a differential input sensing circuit 115. The memory element 114 having the double-ended comparison line output is used for storing the data signal and outputting the double-ended comparison line (ML<i>, SML<i>) compared to whether the data signal to be searched and the stored data signal are the same. ;) to the differential input sensing circuit 115, the differential input sensing circuit 115 can simultaneously sense all of the β β -memory elements 114 on the word line to achieve a fast search comparison speed, the differential input The sensing circuit 115 outputs a comparison signal according to the double-ended comparison line, and turns off the charging path of the differential input sensing circuit 115 to save power consumption. The address encoder 1 〇3 is configured to output an address signal (Match-address) according to the comparison signals to search for the address signal of the matching data. Referring to Figure 2, there is shown a schematic diagram of a memory element of the present invention having a double-ended comparison line output. The memory component 114 having the double-ended comparison line output of the present invention comprises: a memory unit 201 and a mutual retort type comparison circuit 2〇2. The memory unit 201 is configured to store a data signal Q, and compare with the first bit line (BLB<i>) and the second bit line (BLB<i>) to output a first node A1 and a first Two nodes A2. In this embodiment, the memory unit 2 is a 6-T static random access memory element (sraM CELL). The mutual retort type comparison circuit 202 includes a first N-type transistor NMOS, a second N-type transistor, and a transistor NM203. Wherein the gate of the first N-type transistor NM2〇l is connected to the first node A1 of the 133587.doc • 9 - 201021050, the source of which is connected to the first bit line (BL<i>), and thereafter The gate of the second N-type transistor NM202 is coupled to the second node A2, and the source thereof is connected to the second bit line (BLB<i>;), the drain is coupled to the third N-type transistor NM203 gate. The source and the drain of the third N-type transistor NM203 are respectively connected to the double-ended comparison line (ML<i>, SML<i>), and the double-ended comparison line includes a first comparison line (ML<i>) and A second comparison line (SML<i>) controls whether the third N-type transistor NM203 is turned on according to the comparison result of the memory unit 201. When the input signal of the first bit line (BL<i>) is equal to the data signal Q, the third N-type transistor NM203 is turned off; otherwise, when the input signal of the first bit line (BL<i>) is not Equal to the data signal Q, the third N-type transistor NM203 is turned on. Referring to Figure 3, there is shown a schematic diagram of a differential input sensing circuit of the present invention. The differential input sensing circuit 105 of the present invention includes a differential input circuit 301, a positive feedback circuit 302, and a selection logic circuit 303. The differential input circuit 301 includes a first charge and discharge control transistor PM301, a second charge and discharge control transistor NM303, and a differential pair circuit. The first charge and discharge control transistor PM301 is connected to the differential pair circuit, and the differential pair circuit is connected to the second charge and discharge control transistor NM303. The differential pair circuit includes a plurality of transistors PM302, PM303, and NM301. The NM 302 is configured to receive the first comparison line (ML<i>) and the second comparison line (SML<i>), and output a third node (KP). The positive feedback circuit 302 includes a third P-type transistor PM304, a fifth N-type transistor NM304, a sixth N-type transistor NM305, and an inverting circuit 133587.doc -10· 201021050 304 » the third P The source of the transistor PM304 is connected to a voltage source, the gate is coupled to a search signal (SEARCH), and the drain is coupled to the third node (KP). The fifth N-type transistor NM3042 is electrically coupled to the third node (KP), the gate is coupled to the search signal (SEARCH), and the source is coupled to the sixth N-type transistor NM305. pole. The gate of the sixth N-type transistor NM305 is coupled to an output terminal (MATCHB) of the inverter circuit 304, and the source thereof is connected to a ground terminal. The input of the inverter circuit 304 is connected to the third node (KP). The selection logic circuit 303 includes an inverter 307, a multiplexer 308, and a seventh N-type transistor NM306. The input end of the inverter 307 is connected to the second pole of the sixth N-type transistor NM3 06, and the output end thereof controls one of the select ends of the multiplexer 307; the two input ends of the multiplexer 307 are respectively connected to a ground terminal and a search enable signal (SEARCH-EN), the output of the multiplexer 308 is the search signal (SEARCH); the drain of the seventh N-type transistor NMOS NM306 is coupled to the sixth N The drain of the transistor NM305 has its gate connected to an inverted search enable signal (SEARCH_EN) and its source connected to a ground terminal. In this embodiment, the first charge and discharge control transistor PM301 is a P-type transistor, the source thereof is connected to a voltage source, and the gate thereof is coupled to the output end of the inverter circuit 302 (MATCHB). The drain is coupled to the differential pair circuit. The second charge and discharge control transistor NM303 is an N-type transistor, the drain of which is coupled to the differential pair circuit, the gate of which is coupled to the output end of the multiplexer 308 (SEARCH), and the source is coupled Connected to the first comparison line (ML<i>). In this embodiment, the differential pair circuit includes a first P-type transistor 133587.doc 201021050 PM302, a second P-type transistor PM303, and two N-type transistors NM301, NM302. The source of the first P-type transistor PM302 and the source of the second P-type transistor PM303 are connected to the drain of the first charge-discharge control transistor PM301, and the first P-type transistor PM302 a gate is coupled to the first comparison line (ML<i>), a gate of the second P-type transistor PM303 is coupled to the second comparison line (SML<i>), and a drain is coupled to the gate Third node (KP). Referring to FIG. 2 and FIG. 3, the circuit operation mode of the differential input sensing circuit 1〇5 of the present invention is as follows: 1. Before searching for the 'first comparison line (ML<i>) and the second comparison line (SML<i>;) Before the search, it will be set to the low voltage level, the search enable signal (SEARCH_EN) is logic zero (low voltage level), the seventh N-type transistor NM3 06 is turned on, and the input of the inverter 307 is turned on. The terminal (SP) is lowered to a low voltage level, so that the search signal (SEARCH) is logic zero, the third P-type transistor PM304 is turned on, and the fifth N-type transistor NM304 is turned off, so that the third node (KP) is logic one ( The high voltage level) further causes the output terminal (MATCHB) of the inverter circuit 304 to be logic zero, and the first charge and discharge control transistor PM301 is turned on. 2. When the search starts, the search enable signal (SEARCH_EN) is logic one, then the search signal (SEARCH) is logic one, and the second charge and discharge control transistor NM303 is turned on. (1) If the input data to be searched matches the data stored in the memory unit on the character line, that is, when the input signal of the first bit line (BL<i>) is equal to the data signal Q, then Figure 2 The third N-type transistor NM203 does not conduct 133587.doc -12- 201021050, so that the first comparison line (ML<i>) is continuously charged and the voltage value rises, but the second comparison line (SML<i>) voltage The value remains at zero, and the third node (κρ) is maintained at the high voltage level 'causing the input (sp) voltage value of the inverter 307 to rise all the time due to the inverter 3〇7 of the selection logic circuit 303 and the The multiplexer 308 causes the search signal (SEARCH) to be lowered to a low voltage level, the second charge and discharge control transistor NM303 is turned off, and the inverting circuit 3〇4 output terminal (MATCHB) remains logic zero. Referring to Figure 4, a time domain diagram of the above operational situation is shown. (2) If the input data to be searched does not match the data stored in the memory element on the character line, that is, when the input signal of the first bit line (BL<i>) is not equal to the data signal Q, then Figure 2 The third N-type transistor NM203 is turned on, such that the first comparison line (ML<i>) and the second comparison line (SML<i>) are continuously charged and the voltage value rises, and the voltage value of the third node (KP) Then, the sixth N-type transistor NM305 of the positive feedback circuit 302 is activated, so that the third node (KP) is reduced to logic zero, and the output of the inverter circuit 304 (MATCHB) is logic one. The first charge and discharge control transistor PM301 is turned off. Referring to Figure 5, a time domain diagram of the above operational situation is shown. Therefore, regardless of whether the comparison result is consistent, since the positive feedback circuit 302 and the selection logic circuit 303 have a short sensing time to achieve a fast search comparison speed; and after the sensing ends, the first The charge/discharge control transistor PM301 or the second charge and discharge control transistor NM303 is turned off, and has a function of automatically turning off the current charging path of the first comparison line (ML<i>), thereby reducing power consumption. However, the above-described embodiments are merely illustrative of the principles and effects of the present invention, and are not limited to the 133587.doc -13. 201021050. Therefore, those skilled in the art can make modifications and changes to the above embodiments without departing from the spirit of the invention. The scope of the invention should be as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram showing the addressable memory of the present invention; FIG. 2 is a schematic diagram showing the memory element of the present invention having a double-ended comparison line output. FIG. 3 shows the differential input of the present invention. 4 is a schematic diagram of a sensing circuit in accordance with the present invention; and FIG. 5 shows an analogizable time domain map of a data search element on a single word line to a data matching; and FIG. 5 shows an addressable memory of the present invention. A data search for a memory on a single character line is less than a simulated time domain map that meets the data. [Main component symbol description] 100 101 102 103 112 114 115 201 202 301 302 ❿ The content of the present invention addressable memory data register data search comparison circuit address encoder data search alignment column has double-ended comparison line output Memory element differential input sensing circuit memory unit mutual retort type comparison circuit differential input circuit positive feedback circuit 133587.doc -14- 201021050
303 選擇邏輯電路 304 反相電路 307 反相器 308 多工器 BL<i> 第一位元線 BLB<i> 第二位元線 ML<i> 第一比較線 NM201 第一 N型電晶體 NM202 第二N型電晶體 NM203 第三N型電晶體 NM301、NM302 N型電晶體 NM303 第二充放電控制電晶體 NM304 第五N型電晶體 NM305 第六N型電晶體 NM306 第七N型電晶體 PM301 第一充放電控制電晶體 PM302 第一 P型電晶體 PM303 第二P型電晶體 PM304 第三P型電晶體 SML<i> 第二比較線 133587.doc -15-303 selection logic circuit 304 inverter circuit 307 inverter 308 multiplexer BL<i> first bit line BLB<i> second bit line ML<i> first comparison line NM201 first N-type transistor NM202 Second N-type transistor NM203 Third N-type transistor NM301, NM302 N-type transistor NM303 Second charge-discharge control transistor NM304 Fifth N-type transistor NM305 Sixth N-type transistor NM306 Seventh N-type transistor PM301 First charge and discharge control transistor PM302 First P type transistor PM303 Second P type transistor PM304 Third P type transistor SML<i> Second comparison line 133587.doc -15-