201017859 六、發明說明： 【發明所屬之技術領域】 本發明係有關一種電子構裝堆叠结構。 【先前技術】 電子元件構裝技術目前已經不斷的進步’盼藉由技術的改 進，開發出體積更輕薄短小、整合性更高、更具市場競爭力 之產品。因此於母板（mother board)需設置之元件曰益增多， 如驅動1C、控制晶片、記憶體裝置與多個被動元件。如圖1 所示，不同尺寸與功能的被動元件1、2、3、4、5、6、7、8、 9、10、11、12通常#利用表面黏著技術（surface mount technology)設置於母板100上並佔有相當之面積。於電子構 裝技術中，如何有效提高空間使用率實為一重要之課題。 【發明内容】201017859 VI. Description of the Invention: [Technical Field to Which the Invention Is Ascribed] The present invention relates to an electronic assembly stack structure. [Prior Art] Electronic component packaging technology has been continuously improved. It is hoped that through technological improvements, products that are thinner, lighter, more integrated, and more competitive in the market will be developed. Therefore, the components to be installed on the mother board have increased benefits, such as driving the 1C, controlling the wafer, the memory device, and the plurality of passive components. As shown in Figure 1, passive components of different sizes and functions 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 are usually placed on the mother using surface mount technology. The board 100 occupies a considerable area. In the electronic assembly technology, how to effectively improve the space utilization rate is an important issue. [Summary of the Invention]
+本發明目的之一係提供一種電子構裝堆疊結構，將被動元 件藉由基板堆疊達到空間有效利用。 本發明目的之—健供—種電子構裝堆#結構，被動心 藉由基板堆疊後可藉由金屬引線電性連接兩基板。An object of the present invention is to provide an electronic package stack structure that utilizes substrate stacking for space efficient use. The purpose of the present invention is to provide a structure for the electronic package. The passive core can be electrically connected to the two substrates by metal leads after the substrate is stacked.
結構為，:=上S 基板上並料—細賴元件，錢置於第 上；複數個第二被_件，# ^板’係、叠置於第—被動元 接；複數條金屬二第二基板上並與第二基板電性: 層，係設置於第二⑼^接第—基板與第二基板；以及一氣 被動元件上。 T面用以將第二基板疊置於第-基板之第. 201017859 【實施方式】 圖2Α、圖2Β與圖2C所示為根據本發明一實施例電子構裝堆 疊結構之示意圖。於本實施例中，電子構裝堆疊結構係包括： 第一基板110與一第二基板120。如圖2A所示，複數個第一 被動元件21、22、23、24'25、26、27、28被設置於第一基板11〇 上並與第一基板11〇電性連接。 ΟThe structure is::= on the S substrate, and the material is placed on the top; the money is placed on the first; the second is the _ piece, the #^ plate is attached to the first-passive element; the plurality of metal is the second The second substrate is electrically connected to the second substrate: the layer is disposed on the second (9) and the second substrate and the second substrate; and a gas passive component. The T-plane is used to stack the second substrate on the first substrate. 201017859 [Embodiment] FIG. 2A, FIG. 2A and FIG. 2C are schematic views showing an electronic structure stacking structure according to an embodiment of the present invention. In this embodiment, the electronic package stack structure includes: a first substrate 110 and a second substrate 120. As shown in Fig. 2A, a plurality of first passive components 21, 22, 23, 24'25, 26, 27, 28 are disposed on the first substrate 11A and electrically connected to the first substrate 11. Ο
接續上述說明，如圖2B所示，複數個第二被動元件29、30、 31、32被設置於第二基板12〇上並與第二基板12〇電性連接。其中， 請參照圖2C ’第二基板12〇疊置於第一被動元件21、22、23、24、 25、26、27、28上。複數條金屬引線130電性連接第一基板110與第 —基板120。 繼續參照圖3A’一黏著層140係設置於第二基板120下表面用 以將第二基板120疊置於第一基板110之第一被動元件21、22、23、 24、25、26、27、28上。此黏著層14〇之材質包括環氧樹脂或絕緣膠。 於一實施例中，第一被動元件21、22、23、24、25、26、27、28之 向度可為相同，如圖3A所示。於另一實施中，第一被動元件21、22、 23、24、25、26、27、28之高度為相異，於圖3B所示。因此’選擇 黏著層140時，需選用較柔軟之材質。 於一實施例中，於下層之第—基板u〇更可設置其他元件，如記 憶體晶片或控制晶片等，圖上未示。 综合上述，本發明將被動元件藉由基板堆疊達到空間有效 =用，被動το件藉由基板堆疊後可藉由金屬引線電性連接兩 ，板。因此，位於下層之母板可將空間用作設置更多元件並 整合更多功能。 以上所述之實施例僅係為說明本發明之技術思想及特 其目的在使熟習此項技藝之人士能夠瞭解本發明之内容 ，據以實施’當孩以之限定本發明之專利，即大凡依 ^發明所揭*之精神所作之均等變化祕飾，減涵蓋在本 發明之專利範圍内。 201017859 【圖式簡單說明】 圖1所示為習知技將被動元件設置於母板上之示意圖。 圖2A、圖2B與圖2C所示為根據本發明一實施例之示意圖。 圖3A與圖3B所示為本發明不同實施例之示意圖。 【要元件符號說明】 100 母板 φ 110第一基板 120 第二基板 130 金屬引線 140黏著層 1、2、3、4、5、6、7、8、9、10、11、12 被動元件 21、22、23、24、25、26、27、28 第一被動元件 29、30、3卜32第二被動元件Following the above description, as shown in FIG. 2B, a plurality of second passive components 29, 30, 31, 32 are disposed on the second substrate 12A and electrically connected to the second substrate 12. 2C, the second substrate 12 is stacked on the first passive components 21, 22, 23, 24, 25, 26, 27, 28. The plurality of metal leads 130 are electrically connected to the first substrate 110 and the first substrate 120. 3A', an adhesive layer 140 is disposed on the lower surface of the second substrate 120 for stacking the second substrate 120 on the first passive component 21, 22, 23, 24, 25, 26, 27 of the first substrate 110. 28 on. The material of the adhesive layer 14〇 includes epoxy resin or insulating glue. In one embodiment, the first passive elements 21, 22, 23, 24, 25, 26, 27, 28 may be the same, as shown in Figure 3A. In another implementation, the heights of the first passive components 21, 22, 23, 24, 25, 26, 27, 28 are different, as shown in Figure 3B. Therefore, when selecting the adhesive layer 140, a softer material is required. In one embodiment, other components such as a memory chip or a control wafer may be disposed on the first substrate of the lower layer, which is not shown. In summary, the present invention achieves space-efficient use of the passive components by the substrate stacking. The passive τ component can be electrically connected to the two boards by metal leads after the substrate is stacked. Therefore, the motherboard in the lower layer can use the space to set more components and integrate more functions. The embodiments described above are merely illustrative of the technical idea of the present invention and the purpose of the present invention is to enable those skilled in the art to understand the contents of the present invention, and to implement the invention as a child. The equivalent change secrets made in accordance with the spirit of the invention are included in the scope of the patent of the present invention. 201017859 [Simple Description of the Drawings] FIG. 1 is a schematic view showing a conventional method of disposing a passive component on a mother board. 2A, 2B and 2C are schematic views of an embodiment of the present invention. 3A and 3B are schematic views of different embodiments of the present invention. [Description of Element Symbols] 100 Motherboard φ 110 First Substrate 120 Second Substrate 130 Metallic Leads 140 Adhesive Layers 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 Passive Components 21 , 22, 23, 24, 25, 26, 27, 28 first passive component 29, 30, 3 32 32 passive component