TW201017529A - Computation and addressing method of a eneral sized memory-based FFT processor - Google Patents

Computation and addressing method of a eneral sized memory-based FFT processor Download PDF

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Publication number
TW201017529A
TW201017529A TW97141311A TW97141311A TW201017529A TW 201017529 A TW201017529 A TW 201017529A TW 97141311 A TW97141311 A TW 97141311A TW 97141311 A TW97141311 A TW 97141311A TW 201017529 A TW201017529 A TW 201017529A
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Taiwan
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fourier transform
memory
fast fourier
data
point
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TW97141311A
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English (en)
Chinese (zh)
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TWI375171B (cs
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Chen-Yi Lee
qing-feng Xiao
Yuan Chen
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Univ Nat Chiao Tung
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TW97141311A 2008-10-28 2008-10-28 Computation and addressing method of a eneral sized memory-based FFT processor TW201017529A (en)

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TW97141311A TW201017529A (en) 2008-10-28 2008-10-28 Computation and addressing method of a eneral sized memory-based FFT processor

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TW97141311A TW201017529A (en) 2008-10-28 2008-10-28 Computation and addressing method of a eneral sized memory-based FFT processor

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TW201017529A true TW201017529A (en) 2010-05-01
TWI375171B TWI375171B (cs) 2012-10-21

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9459812B2 (en) 2014-02-03 2016-10-04 Ceva D.S.P. Ltd. System and method for zero contention memory bank access in a reorder stage in mixed radix discrete fourier transform
CN109117454A (zh) * 2017-06-23 2019-01-01 扬智科技股份有限公司 3780点快速傅立叶转换处理器及其运作方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9459812B2 (en) 2014-02-03 2016-10-04 Ceva D.S.P. Ltd. System and method for zero contention memory bank access in a reorder stage in mixed radix discrete fourier transform
CN109117454A (zh) * 2017-06-23 2019-01-01 扬智科技股份有限公司 3780点快速傅立叶转换处理器及其运作方法
CN109117454B (zh) * 2017-06-23 2022-06-14 扬智科技股份有限公司 3780点快速傅立叶转换处理器及其运作方法

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TWI375171B (cs) 2012-10-21

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