TW201017423A - System and method of dynamically switching queue threshold - Google Patents

Abstract

A system and method of dynamically switching the threshold of a queue, such as FIFO, is disclosed. The queue has a first threshold and a second threshold, where the first threshold is greater than the second threshold. The queue is switched between the first threshold and the second threshold according to different CPU power state. The queue is then filled with data from system memory whenever the quantity of the data in the queue is less than the switched threshold.

Description

201017423 IX. Description of the Invention: [Technical Field] The present invention relates to a power management, and more particularly to a system and method for dynamically switching a FIFO threshold. [Prior Art] Intel Corporation (Intel) announced the specification of high definition audio (HDA) in 2004. The specifications of the specification can refer to the High Definition Audio Specification version 1.0 and its subsequent update version (http). ://www.intel.com/standards/hdaudio/ ). • The first diagram shows the basic architecture of the HDA. A central processing unit (CPU) 10 is coupled to the memory controller 12 via a main bus 1 for controlling access to the system memory 13. The memory controller 12 is coupled to the HDA controller (HDAC) 15 via a system bus (e.g., PCI) 14. The HDA controller 15 is connected to one or more codecs (codecs) 17 via an HDA link 16. The HDA controller 15 includes one or more direct memory access (DMA) instructions 5 201017423 engine or controller ι5〇 (hereinafter referred to as ^^8) for controlling the system memory 13 and the codec. The transfer of the data stream between 17 and the HDA link 16 provides a means for the control signals and data to be transmitted between the HDA controller 15 and the vocoder 17. Each codec 17 includes one or more converters (converter 'C) for converting digital signals into analog signals to an output device (eg, η 八), or from an input device (eg, a microphone). The analog signal is converted to a digital signal. The DMA 150 contains a queue of information, such as first in first out (FIFO) ^ ϋ ( „T ^ FIK〇), which stores enough data to maintain the data stream in the HDA link 16 so that it There will be no underrun or overrun situations. Therefore, before the data is transferred to the HDA link 16, if the amount of data in the FIFO is less than a threshold, the HDA controller 15 enters the sink. The bus master cycle is used to access data in the system memory 13. Generally, the relationship between the FIFO threshold, the burst length and the FIFO length (FIFOSIZE) has the following relationship, where h represents 16 carry value, DW stands for double word (double word, which is equivalent to 4 bytes)·· 201017423 Table 1

FIFOSIZE FIFO threshold continuous transmission length 40h DW 31h DW — lOh DW 30h DW 21h DW lOh DW 20h DW 19h DW 8h DW lOh DW dh DW 4h DW 8h DW 7h DW 2h DW 4h DW 4h DW lh DW Other values 4h DW ·— 1 —. lh The function of the DW FIFO threshold is to let the HDA controller 15 know when it is necessary to enter the bus master cycle to obtain data in the system memory 13 for playback or to store data to the system. Inside the memory 13. In this way, the underrun situation caused by the busy bustling of the system bus 14 can be avoided as a kind of tolerance. The second figure illustrates a FIFO' with a total length of 192 bytes and a critical value of 128 bytes. For example, a sampling rate of 48 kHz, two channels, and a 16-bit (or 2-byte) data format for each channel, for example, each data frame (frame) contains 4 bytes, and each data can be The box is regarded as the unit resource 7 201017423 material transmission amount. When the data in the FIFO is less than 128 bytes, the HDA controller 15 will enter the bus master cycle. The transmission time is 20.83 microseconds (//s) (=1Λ48χ103)), which can be equal to 20.83 microseconds ("considered as 'unit transmission time", so 128 bytes can hold 32 data frames (=128/ 4) Up to 666 microseconds (A s) (=32x20.83). In the HDA system of the first figure, the 'input and output device (such as woo, headset, modem or microphone) is coded by 17 The interface connected to the HDA controller 15° HDA link 16 performs data transmission by some basic control signals. For example, serial digital output (iAZS^DO) is used to transmit sequence format data to Output device 'serial digital input (AZSDI) Receiving data of the input device; the synchronization signal SYNC is driven by the HDA controller 15 for synchronization of the data frame and as an outbound tag signal; the reset signal AZRST# is used to reset the HDA chain. 6; The clock signal AZBITCLK is a 24 MHz clock source, which is obtained by dividing the 48 MHz USBPHY PLL. 8 201017423 When the HDA driver issues a request to the HDA controller 15 and sets it to execute. After the (RUN) bit, the HDA controller 15 can perform paging, recording, command outbound ring buffer (CORB) or inward response loop buffer with the codec 17 by the DMA 150. Response inbound ring buffer (RIRB) The power management unit (PMU) 18 in the first system is used to control the power-saving sleep state (Cx) of the central processing unit 10. For example, HP (AC) (Advanced Configuration and Power Interface) specifications developed by companies such as (HP) and Intel (Intel). For details of the specifications, refer to the website (http://www.acpi.info/). ). According to the ACPI specification, the C0 state represents that the CPU 10 is in a fully operational state, and Φ C1 to Cn are in various sleep states; wherein a larger value of η indicates that the CPU 10 is less idle, that is, the power is saved. When in the C2 (or below) state, the system can continue to access the system memory 14; when in the C3 or higher state, the system cannot access the system memory 14. In other words, if in the C4 state and the amount of data in the FIFO is less than the critical value, the CPU 10 must transition from C4 to the C2 state in order to request data from the system memory 14. By the same token, if the amount of data in the FIFO is less than the critical value in the C3 state and 9 201017423, the CPU 10 must change from C3 to the C2 state to request data from the system memory 14. The HDA controller 15 and codec 17 can request a bus master event or interrupt event in the sleep state Cx without software triggering. At this point, codec 17 can drive azsd to inform HDA controller 15 and request a bus master cycle or interrupt. The azsdj signal can be locked by the PMU 18 to form a power management event (PME), which causes the CPU 1 to leave the sleep state Cx.

_ ! -I The third figure shows the flow chart of the HDA system entering and leaving the sleep state. First, the PMU 18 signals that the cpu 1〇 enters the C3 or C4 (i.e., 'C3/C4) state (step 3〇). Next, in step 31, it is determined whether the RUN bit of the HDAC is active. If the RUN bit is not active, cpu ίο is in the C3/C4 state (step 32A). At this time, the HDA link 16 is in a reset state (step 33A), which causes the codec 17 to be hidden (when the HDA link 16 does not exist at this time). Next, in step 34A, if the HDA controller 15 detects the active AZSDI signal, the CPU 1〇 will leave the C3/C4 state and enter the C0/C2 state (step 35); otherwise, if the HDA controller 15 201017423 detects To the inactive AZSDI signal 'the CPU 10 is maintained in the C3/C4 state (step 32A). If the RUN bit determined in step 31 is active, the CPU is in the C3/C4 state (step 32B). At this time, the HDa link leaves the reset state (step 33B), which causes the codec 17 to be revealed (when the HDA link 16 exists). Then, in step 34, if the HDA controller 15 detects the active weeping signal, or the data in the FIFO is less than the critical value, the CPU 1〇 will leave the state and enter the C0/C2 state (step 35). 'Otherwise, cpu 1〇 is maintained in the C3/C4 state (step 32B). When the CPU 10 is in the C3/C4 state, since the device is easy to enter the bus master control cycle, there is no need to store too much data in the FIFO. • The data is used for playback or recording. Conventional HDA systems use a fixed Fif〇 threshold, whether in the C3/C4 state or the C0/C2 state, thus causing the CPU 10 to leave C3/C4 frequently to enter the c〇/C2 state. In view of the fact that the traditional power-saving sleep state transition is not efficient for power saving, it is urgent to propose a novel control mechanism to save more power, so that the portable electronic device can be used in the case of limited power supply. Longer time. 11 201017423 SUMMARY OF THE INVENTION It is an object of the present invention to provide a threshold value system and method for dynamically switching data columns (e.g., fIFQ) to make the (four) system power supply more efficient. According to an embodiment of the invention, the data queue (e.g., FIF〇) is provided with a first threshold value and a second threshold value, wherein the first threshold value is greater than the second threshold value. The first threshold or the second threshold is dynamically switched to the knowledge base according to the central processing unit (CPU) being in a different power saving state. For example, when the CPU changes from the first state to the more power-saving state, the first threshold is switched to the second threshold. When the CPU changes from the second state that is more power-saving to the first state, then the first The threshold is switched to the first threshold. When the amount of data in the data queue is less than the first threshold or the second threshold after the switch, a master record is accessed to fill the data. [Embodiment] FIG. 4A shows the inventive concept of the dynamic switching data queue threshold value of the present invention. The data queue 40A/40B (for example, FIFO) is provided with a first threshold and a second threshold, wherein the first threshold is greater than the second threshold, and the CPU (CPU) is in a different power saving state and dynamically cuts 12 201017423 The first critical value or the second critical value to the data column. As shown in FIG. 4A, when the CPU changes from the first state to the second state that is more power-saving, the data queue 40A of the first threshold is switched to the data of the second threshold 40B° when the CPU is compared. When the second state of the power saving becomes the first state, the data queue 40B of the second threshold value is switched to the data queue 40A of the first critical value. ❹ The fourth B and fourth c diagrams show the FIF 可 which can dynamically switch the threshold according to an embodiment of the present invention. This embodiment takes the HDA system as an example, so its system architecture will follow the system block diagram and its label shown in the first figure. Although the present embodiment is exemplified by the HDA, the present invention is also applicable to other sound specification systems, video specification systems, or general data input and output systems. For example: Integrated Device Electronic (IDE) system, Serial Advanced Technology φ Attachment (SATA) system or Universal Serial Bus (USB) system. In this embodiment, when the CPU l is in the C0/C2 state, the threshold value of the data queue is a larger first threshold (fourth B map); when in a more power-saving C3/C4 state, The threshold of the data queue is a smaller second threshold. The above CO, C2, C3, C4 are ACPI (Advanced 13 201017423

Power saving status in the Configuration and Power Interface specifications. The power saving state of the CPU is controlled by a power management unit (PMU) 18. The FIFs shown in the fourth and fourth C diagrams are based on a sampling rate of 48 kHz, two channels, and a 16-bit (or 2-byte) data format for each channel. ) contains 4 bytes. In the present embodiment, each frame may be regarded as one of the "unit data transmission amount" embodiments, however, it is not intended to limit the present invention. In other embodiments, for example, in a USB system, the "unit data transfer amount" can be a "transaction" (transaction) completed into the data transfer amount involved. For the fourth 6 graph FIFO, when the HDAi controller 15 After consuming 64 bytes of data (that is, when the data in the FIFO is less than the threshold of 128 bytes), the CPU 10 will leave the C3/C4 state and issue a bus master cycle (bus call mastercycle). Since the transmission time of each data frame is 2〇83 microseconds (private s) (=1Λ48χ1〇3)), you can treat 2, 83 microseconds (heart) as a "unit transmission time". , that is, the time it takes to transmit a "unit data transfer amount". Therefore, this 64-bit data allows cpu 1〇 to stay in the C3/C4 state for up to 16 data frames (=64/4), which is equivalent to 333 28 microseconds (#s) (=16x20.83). 201017423 When this is the case, the 128-bit tuple (that is, the 'first threshold value') of the FIFO material is switched to the 64-bit of the fourth c-picture. The tuple (ie, the 'second threshold'), for the same data format (ie, sampling when the HDA controller 15 consumes 128 bytes of resources) After (that is, the data in the FIFO is less than the critical value of 64 bit township time), cpui〇 will leave the C3/C4 state and issue the bus master control cycle (bus off: spring cycle). Because each data frame The transfer time is plus (10) microseconds Us) (=1Λ48χ103)) 'So this 128-bit data allows cpu 1〇 to stay in the C3/C4 state for up to 32 data frames (=128/4), ie The time it takes to transmit 32 "unit data transfers" is equivalent to 666.56 microseconds (yS) (=32x20.83). Compared to the FIFO of the fourth b-picture, the FIFO of the fourth C-picture can make the CPU 1 The time spent in the C3/C4 state is 333.28 microseconds (in s) ❹ (=666.56-333.28). It takes some time for the CPU 10 to change from the CX state (X is greater than or equal to 3) to C2. During this time, in order to avoid data underrun or overrun, there must be sufficient data in the fif. In view of this, the setting of the new threshold is sufficient to cope with the CPU 1 state transition. Time》 15 201017423 The fifth figure illustrates the waveform of the ^ from the C4 state to the C3 state until the C2 state. The CPU 1〇 enters C3 from C4. The state takes 30.14 microseconds C // , ί MJ (=12.56+17.58), and it takes 870 apricot γ β, “ w, ns) to enter the C2 state from C3. Therefore, the total time from C4 to C2 is about 32. Microseconds ("q, 〇. If 20.83 microseconds (/zs) of a data frame is used as a time unit of transportation, then the fifth Lu Xin

The Jf - μ example requires at least two units of transmission time to handle the CPU ]^Q 41: At state transition. In other words, the second threshold can be set to no, •1, one stay » >, the length of the morning pass time. Taking a data rate of 48 kHz, two channels, and 16-bit (or 2-byte) per channel as an example, the two-unit transmission time is equivalent to I g bytes, that is, two, and the unit transmits data. Usually, 'based on tolerance considerations, plus a few units of data transferred," as a safety data frame. For example, if the cpu ίο transition from C4 to C2 may exceed 41.66 microseconds (ie, one unit of transmission time), then a number of "unit rounds of data" security data frames must be added. To avoid the occurrence of an underrun or overrun situation. In the present embodiment, the second threshold value can be obtained by the following equation: 16 201017423 Two states/first state transitions V (second threshold value per unit transmission = (unit data transmission amount)*[(from the first - the time required for the status/second state)]+n* (unit data transfer amount)

The η material small (four) filament in the above formula can be controlled by a 3-bit in a register, and η is an integer of 〇~7 - the above-mentioned safety data frame means η * (The unit data transmission volume can be adjusted according to the application situation, and no person is added (η=(7) or the second critical value after adding the safety data frame is still not greater than the first critical value. In one embodiment If the result calculated by [(the second state/first state becomes the first state/second state required time unit transmission time)] is not an integer, the obtained quotient may be increased by 1' The data may be underrun or overrun. In addition, the unit of the first threshold or the second threshold may be a bit or a byte. The sixth figure shows the dynamics according to an embodiment of the present invention. Flowchart for switching the FIFO threshold. First, the PMU 18 signals that the CPU 10 enters the C3/C4 state (step 60). Next, it is determined in step 61 whether the RUN bit of the HDAC is active (if active) if the RUN bit is not To be active, the CPU 1 is in the C3/C4 state (step 62). At this point, the HDA link 16 is in reset. (reset) state (step 63), which causes the codec 17 of 17 201017423 to be hidden (the HDA link 16 does not exist at this time). Next, in step 64, if the HDA controller 15 detects the active AZSDI The signal 'cpu 1〇 will leave the C3/C4 state and enter the C0/C2 state (step 65); otherwise, if the hda controller 15 extracts the inactive AZSDI signal, the CPU X〇 remains in the C3/C4 state (step 62) If the RUN bit determined in step 61 is active, pMu will issue a PMU-C3/C4 signal by a link between HDA control!!15ΜΜυΐ8 (for example, # in the fifth figure) The DpSLp (C3) number allows the HDA to control the np system to know the current power state (step 66). Compared with the conventional system (shown in the heart diagram), the HDA control (4) 15 in this embodiment can be actively pre-measured. Knowing (4) 1〇 current power state, this is the function that is lacking in the traditional system. Next, the calculated FIF 〇 second critical value (that is, the critical value of the C3/C4 state, for example, the example of the fourth c-picture) And FIF 〇 first critical value (that is, 'C0/C2 state critical value' such as shown in the fourth b diagram) For comparison (step 67). If the FIFO second threshold is less than the FIF 〇 first threshold value, the associated FIfO threshold value in the HDA controller 15 is switched to the second threshold value (step 68A); otherwise, the FIF threshold is not made. The switching of the value 18 201017423 (step 68B). After the setting of the critical value is completed, the CPU 10 is in the C3/C4 state (step 69). At this point, the HDA key 16 leaves the reset state (step 70)' which causes the codec 17 to be revealed (when the HDA link 16 is present). Next, in step 71, if the hdA controller 15^(detects the active AZSDI signal, or the Fijr data is less than the critical value, the CPU 10 will leave the CVC4 state and enter the C0/C2 state (step 65); Otherwise, the CPU 10 maintains the C3/C4 state (step 69). According to an embodiment of the present invention, the FIFO threshold value is dynamically set according to the power state in which the power state is the C0/C1 state or the C3/C4 state. The critical value allows the cpu ίο to be in the C3/C4 state for a longer period of time, saving more power, allowing the portable electronic device to 'use longer time in the case of limited power supply. The present invention is For the "dynamic" adjustment of the same data threshold, this is not the same as the artificial adjustment made at the factory. For example, if the conventional FIFO size is 40hDw, the critical value is 3 hours. DW, after the factory may be due to customer demand, will deliberately adjust the threshold from 19 201017423 40hDW to another threshold ighDW. In contrast, the first critical value of the case is the general waste threshold (same as the conventional Pro Value), "data transmission per unit" in the first critical value, "transmission between the unit" as the value of the user at the time of use, in accordance with the usage obtained, so the second threshold value can be dynamically changes afterwards.

In the case of a hardware architecture, in one embodiment of the invention, the DMA 150 β may be integrated into the HDA controller 15; however, in other embodiments, the DMA 150 may be configured outside of the HDA controller 15. Furthermore, in an embodiment of the invention, one FIFO may be configured to correspond to one DMA 150; but in other embodiments, multiple FIFO configurations may be associated: .丨丨, 'to the same DMA 150 for _ low cost. The above is only the preferred embodiment of the present invention, and is not intended to limit the scope of the invention as claimed. Any equivalent changes or modifications made without departing from the spirit of the invention should be included in the following. Within the scope of the patent application. For example, the present invention is applicable to a general data queue that requires access to the main memory, and is not necessarily limited to the HDA system. [Simple diagram of the diagram] The first diagram shows the basic architecture of the HDA. 201017423 The second figure illustrates a FIFO with a total length of 192 bytes and a threshold of 128 bytes. The third figure shows a flow chart of the traditional HDA system entering and leaving the sleep state. The fourth A diagram shows the inventive concept of the dynamic switching data queue threshold of the present invention. The fourth B and fourth C diagrams show FIFOs that can dynamically switch thresholds in accordance with an embodiment of the present invention. ^ The fifth diagram illustrates the signal waveform from the C4 state to the C3 state up to the C2 state. The sixth diagram shows a flow chart of dynamically switching FIFO thresholds in accordance with an embodiment of the present invention. [Main component symbol description]

10 central processing unit (CPU) 11 main bus (host bus) 12 memory controller 13 system memory 14 system bus 15 HDA controller 16 HDA link (link) 17 codec (codec) 18 PMU 21 201017423 30-35 Process of entering and leaving the sleep state of the traditional HDA system Step 40A Set the data of the first threshold value 伫 40B Set the data of the second threshold value 伫 60-71 The process steps of the dynamic switching FIFO threshold value of the embodiment

150 DMA

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Claims (1)

201017423 X. The scope of application for patents: 1. A line that dynamically switches the threshold value of the queue, including: - the data column, which has a -th-threshold value and a second threshold value, according to - central processing The CPU (CPU) is in a different power saving state and dynamically switches to the first critical value or the second critical value of the data string, wherein the first critical value is greater than the second critical value; when the data column is included If the amount of data is less than the first threshold value or the second threshold value after the switching, a primary memory is accessed to fill the data string. 2. The system for dynamically switching data thresholds according to claim 1, wherein when the CPU changes from a first state to a second state, the first threshold is switched to the second threshold. When the CPU changes from the second state to the first state, the second threshold is switched to the first threshold, wherein the second state is saved compared to the first state. 3. The system for dynamically switching data thresholds as set forth in claim 2, wherein when the CPU is in the C0/C2 state, the threshold of the data queue is the first threshold; when in the C3/ In the C4 state, the threshold value of the data queue is the second threshold value, wherein the above C0, C2, C3, and C4 are power saving states in the ACPI (Advanced Configuration and Power Interface) specification. 23 201017423 4· As in the third paragraph of the patent application scope, the above secrets further include (10) a threshold value for controlling the power-saving bear of the CPU. 70 ^ρΜυ), 5· If the second threshold value of the second critical value of the patent application range is changed, the bit data is changed from the first value to the first state/second state. Required: the second position of the transmission time is fine* (time of the unit data) / (single integer. 6 is not less than 〇 6. The dynamic switching data system as described in U of the patent application scope, wherein the η value is by - One of the integers of the 3-bit value in the scratchpad. 1 2 3 4 5 is 〇~7 24 1 . As described in the patent: Item 1: Dynamic switching data 2 system 'where the resource _ column For the first out buffer (FlF〇), the system further includes at least a direct memory access engine (DMA), and the memory 4 corresponds to at least the DMA configuration 'to access the main memory by at least the DMA 5 body to fill the FIFO. 201017423 8. The system for dynamically switching data thresholds as described in claim 1 of the patent scope, wherein the system is a high resolution sound (HDA) system, integrated device circuit (Integrated Device Electronic; IDE) System, Sequence Advanced Technology Add-on (Serial Advanc Ed Technology Attachmeryt; SATA) System or Universal Serial Bus (USB) system 9. The system for dynamically switching data thresholds as described in the first paragraph of the patent application, where the system is still parsing sound (HDA) system, the data is listed as a first in first out buffer (FIFO), and the system further includes an hda controller, the HDA controller includes at least one direct memory access engine (DMA), and at least The DMA corresponds to the FIFO configuration. 10. The system for dynamically switching data thresholds as described in claim 9 further includes an HDA link for connecting the DMA to one or more Codec (codec) 11. A method for dynamically switching the threshold of a data queue (qUeue), comprising: dynamically switching according to - the central processing H (CPU) is in a different power saving state - the critical value of the data (4) to 1 - a critical value or - a second critical value 'where the first critical value is greater than the second critical value; when the data amount in the data column 25 201017423; is less than the first critical value after switching or the second Threshold value , accessing a main memory to fill the data queue. 12. A method for switching data thresholds as recited in claim 11 of the patent application, wherein the CPU changes from a - state to a second In the state, the first critical value is switched to the first: critical value; when tltcpu is changed from the second state to the first state, the second threshold is switched to the first threshold, wherein the second state ratio This first state saves power. 13. The method for dynamically switching data thresholds according to item 12 of the patent scope of Zhongqing Patent, wherein when the CPU is in the CG/C2 state, the threshold value of the data column is the threshold value; when in the C3 In the /C4 state, the threshold value of the data queue is the second threshold value, wherein the above-mentioned c〇, C2, C3, and C4 are power-saving states in the ACPI (Advanced Configuration and Power φ Interface) specification. 14. The method of dynamically switching data thresholds as described in claim 13 of the patent application, further comprising using a power management unit (PMU) for controlling the power saving state of the CPU. 26 201017423 15. For the method of patent application No. 12, in which (4) a 34 dynamic switching data column threshold value is /m, i - critical value = 丨 (single 彳 4 data transmission amount) * (by the second =: Time required to become the first state/second state: = one data transmission amount at the time of transmission); where n is not small 16·If the application is turned over, the dynamic switching of the fine column is the threshold value The method, wherein the η value is controlled by a 3-bit in a register, and η is one of integers of ～7. 17. The method for dynamically switching data thresholds as recited in claim 2, further comprising using at least one direct memory access engine (DMA), wherein the data is listed as a first in first out buffer (FIFO), And the FIFO corresponds to at least the DMA configuration to access the main memory by at least the DMA to fill the FIFO. 18. A method for dynamically switching data thresholds as described in claim 11 of the patent application, which is applicable to a high resolution sound (HDA) system, an integrated device electronic (IDE) system, and a sequence advanced technology attachment. (Serial Advanced Technology Attachment; SATA) system or Universal Serial Bus (USB) system. 27 201017423 19. If you apply for the full-scale sub-paragraph u, the method of changing the threshold value is applied to the high-resolution sound (HDA) system FIFO buffer (brain), and the system is more Control: The HDA controller includes at least one direct memory access engine (DMA), and at least the DMA corresponds to a FIF configuration. φ 2〇. The method for dynamically switching data thresholds as recited in claim 19 further includes using an HDA link to connect the DMA to one or more codecs. . ^ : j 21. If the HDA controller is not active and the system is in the C3/C4 state, as in the case of applying the patent range i, item 19, when the input device inputs data, Then the cpu is changed to c〇/C2 • State 'where the above co, C2, C3, and C4 are the power saving states in the ACPI (Advanced Configuration and Power Interface) specification. 22. The method for dynamically switching data thresholds as recited in claim 19, wherein when the HDA controller is active and the HDA controller detects that the CPU enters a C3/C4 state, the FIFO uses the Second criticality 28 201017423 Value 'The above CO, C2, C3, C4 are the power saving states in the ACPI (Advanced Configuration and Power Interface) specification. 23. The method of dynamically switching data thresholds as recited in claim 22, wherein if the second threshold is greater than the first threshold, the FIf 沿 follows the first threshold. 2 4. If the method for dynamically switching data thresholds according to item 23 of the patent application scope is applied, if there is input device input data or the FIF data is less than the second threshold value, Lin CPU#_(3) state . 25. The method for dynamically switching data thresholds as described in claim 22, wherein the MUPMU-C3/CW number is issued by the power supply management unit (pMu) to cause the HDA controller to detect the (4) Entering the C3/C4 state. 29