TW201015675A - An electronic packaging structure with enhanced design - Google Patents

An electronic packaging structure with enhanced design Download PDF

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Publication number
TW201015675A
TW201015675A TW097137919A TW97137919A TW201015675A TW 201015675 A TW201015675 A TW 201015675A TW 097137919 A TW097137919 A TW 097137919A TW 97137919 A TW97137919 A TW 97137919A TW 201015675 A TW201015675 A TW 201015675A
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TW
Taiwan
Prior art keywords
layer
electronic
package structure
telecommunication
electronic component
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TW097137919A
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Chinese (zh)
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TWI426585B (en
Inventor
Ming-Chih Yew
Tuan-Yu Hung
Kuo-Ning Chiang
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Kuo-Ning Chiang
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Priority to TW097137919A priority Critical patent/TWI426585B/en
Publication of TW201015675A publication Critical patent/TW201015675A/en
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Publication of TWI426585B publication Critical patent/TWI426585B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

This invention provides one kind of electronic packaging structure which contains the enhanced design. The enhancement design is fabricated through batch process. The purposes of the enhanced design are decreasing the thermo-mechanical stress due to the coefficient of thermal expansion (CTE) mismatch among packaging material and improving the packaging reliability. In the above packaging structure, the electric signal could be connected to the enhanced design, and thus the electric performance of the package is increased because of the provided ground plane. On the other hand, the accumulated heat from the integrated circuit could be dissipated quickly through the enhanced design. Therefore, the proposed invention is especially suit for integrated circuits with high power density.

Description

201015675 六、發明說明： 【發明所屬之技術領域】 本發明係有關一種電子封裝結構，特一 化層設計之封裝單元，該結構強化層可構強 U裝結構内電子凡件訊號之接地平面’提高封裝單元:巧 裝太而擁有傳統封裂所沒有之優點;“ t ”吊見的覆晶封裝’chip，fc)主要不同在於轉 ϊ 充填底膠__之特性；®缺少底膠‘呆 ❹ ί教;封裝、结構設計t佳時，封裝體易因晶片與基板間 二:^量^匹配所導致過高之熱應力/應變而提早破壞，造 可*度降低。由以上敘述可知，晶圓級封裝最主要的 之-是藉著適t的結構麟層配合絲幾何控制與 置(Layout)設計，達到降低層間熱應力/應變之目的，進一步 明體巾電訊連線與錫球可靠度制要求之設計絲。本發 =提出具結構強化設計之電子封裝結構，使用單或複數個結 ，強=層減緩於溫度貞載下各㈣間可能產生之熱_機械應 ，藉此降低封裝體内部金屬導線或錫球產生破壞之機會。 【先前技術】 美國專利字號6,284,563中揭露一種具有應力緩衝層設計 $電子封裝結構’請參閱圖一；此封裝結構包括：電訊接點 1 ;應力緩衝層〇〇2 ;電子元件〇〇3 ;訊號連接線⑻4以及絕 緣層005。應力緩衝層⑻2主要分布於電訊接點〇〇1與訊號連 3 201015675 ，線〇〇4 T方’藉由其較柔軟之材料特性釋放封裝體内部於田 3負載下所產生之熱·機械應力，達到提高電訊接點謝可^ 大之熱膨，練，其與電子元件_ _位置㈣材料 較不具有應力緩衝層〇〇2設計之封裝結 在多次麵載下可謝破__子元件=3力=變’ ❹ 增強接=與 刀別具有第一接觸墊022與第三接觸墊〇28，來 S 。外部 ，祕接地平面之_，可藉錢高電子元健 雷 軋特性。為增強封裝結構之散熱能力 ^ :=:往電/二r運作過程中產=能= 至:S:封装趙底部042傳送’並利用散熱物散逸 連003上方之應力緩衝層002可能使訊號 性。、亦可作為電子元件訊號之接地端，增加其電氣特 【發明内容】 晶圓級封裝技術利用在晶圓上即完成封裝的製程，擁有 4 201015675 體=、降低成本、增加產品量產速度、電性表現優 技=所描術’參考前述先前 裝結構，本發明下具結構強化設計之電子封 其目種以批量製造方式完狀電子封裝結構， ㈣置-供一種同時兼顧焊錫接點與金屬導線可靠度之 热-機械:’，、另内====== 熱膨脹一問題二 ❹: 的在於提供—種電子封裝賴，其内部 且古ϋΓΛ另一目的在於提供一種電子封裝結構，其内部 且為熱之良導體，可有效使由電子元件所產生 循賴触躲電村件外部擴 於二電件之面積；單或複數個填充區域，形成於前述電子 結構之上表面，且該電訊接點表子： ί isti電子元件上表面之面積；單或複數個電訊通i、， 形成於歧電子封裝結構電訊無能子元件細墊之 内部電路利用該電訊通道傳遞至封裝體表面；單或複數 個…構強化層，形成於前述覆蓋材料間，且與前述單或複數個 5 201015675 電訊通道相連接。 本發明之前述與其他目的、特徵、以及優點，將藉由下文中參 照圖示之較佳實施例之詳細說明得以更明確。 【實施方式】201015675 VI. Description of the Invention: [Technical Field] The present invention relates to an electronic package structure, a package unit designed with a special layer, which can form a ground plane of an electronic component signal in a U-mounted structure Improve the package unit: it is too clever to have the advantages of traditional cracking; the t-package of the flip chip package 'chip, fc) is mainly due to the characteristics of the 充 充 filling primer _ _ _ lack of primer ❹ 教 teach; when the package and structure design is good, the package is easy to be damaged due to excessive thermal stress/strain caused by the matching between the wafer and the substrate, and the degree of fabrication is reduced. It can be seen from the above description that the most important thing in wafer level packaging is to reduce the thermal stress/strain between layers by using the appropriate structure of the lining layer to match the wire geometry control and layout design. Design wire for wire and solder ball reliability requirements. The present invention proposes an electronic package structure with a structurally reinforced design, using a single or a plurality of junctions, and the strength = layer slows down the heat generated by each of the (4) temperatures under the load, thereby reducing the metal wires or tin inside the package. The ball has a chance to destroy. [Prior Art] U.S. Patent No. 6,284,563 discloses a design of a stress buffer layer $electronic package structure. Please refer to FIG. 1; the package structure includes: telecommunication contact 1; stress buffer layer 〇〇 2; electronic component 〇〇 3; Connection line (8) 4 and insulating layer 005. The stress buffer layer (8) 2 is mainly distributed in the telecommunication contact 〇〇1 and the signal connection 3 201015675, and the wire 〇〇4 T square' releases the thermal and mechanical stress generated by the inside of the package under the load of the field 3 by its soft material property. , to improve the telecommunications contact Xie Ke ^ big heat expansion, training, and electronic components _ _ position (four) material less stress buffer layer 〇〇 2 design package knot in the multiple surface load can be thanked __ child Element = 3 force = change ' 增强 Enhanced connection = and the blade has a first contact pad 022 and a third contact pad 28, to S. External, the secret ground plane _, can borrow money high electronic yuan Jian Lei rolling characteristics. In order to enhance the heat dissipation capability of the package structure ^ :=: During the operation of the electricity / two r, the production = energy = to: S: package Zhao bottom 042 transmission ' and use the heat sink to dissipate the stress buffer layer 002 above the 003 may make the signal. It can also be used as the grounding end of the electronic component signal to increase its electrical characteristics. [Inventive content] Wafer-level packaging technology utilizes the process of completing the packaging on the wafer, which has 4 201015675 body =, reduces cost, increases product mass production speed, Electrical performance superior technology = described "with reference to the aforementioned prior-packed structure, the present invention has a structurally enhanced design of the electronic sealing of the object in a batch manufacturing manner to complete the electronic packaging structure, (four) set - for a simultaneous consideration of solder joints and Thermal-mechanical reliability of metal wires: ',, and other ====== Thermal expansion is a problem. The second is to provide an electronic package. The other purpose is to provide an electronic package structure. The inside is a good conductor of heat, which can effectively expand the area of the electric component generated by the electronic component to the outside of the two electric parts; a single or a plurality of filling regions are formed on the upper surface of the electronic structure, and The telecommunication contact table: ί isti the area of the upper surface of the electronic component; single or plural telecommunication i, the internal circuit formed in the fine pad of the telecommunications incompetent sub-component of the electronic package structure The telecommunications channel with transfer to the surface of the package body; ... A single or multiple layer reinforcing structure, formed between the covering material and is connected to the single or plural 5201015675 telecommunications channel. The foregoing and other objects, features, and advantages of the invention will be more [Embodiment]

本發明揭露一種電子封裝結構。詳言之，本發明提供一 種具結構強化層設計之封裝單元，該結構強化層主要用以減低 應力緩衝層與電子元件間之熱膨脹係數不匹配問題，藉此提高 封裝體中訊號連接線之可靠度。該發明之實施例詳細說明如 下，唯所述之較佳實施例只做一說明，並非用以限定本發明。 圖二A為本發明之第一實施例，為具有結構強化層設計 之電子封裝結構剖面圖，圖三B則為對應於圖三a，本發明第 一實施例之傾斜視角示意圖。第一封裝單元體1⑻利用支撐底 板101作為結構之骨架，該電子元件支撐底板可為金屬材料、 非金屬材料、半導體材料或前述材料的組合；於支 上利用接合層Η)2與電子元件1()4接合，此電子元; ^主動電子元件、被動f子元件、_元件、測 mw組合。利用充填物103將電子= 網版_\二應力緩偏之效果，又該填充區域可利用 /ί板印刷、滚筒式塗佈、喷墨塗佈、貼合、微影技 t其他料之枝戦，且其±平秘近€奸件 面電子70件104上具有複數個接觸墊，其第一 瓣114⑽ 絕緣特性’除作為電訊通道間之 H強化層1〇7’該結構強化層w為電之 二具 材料的組合H㈣σ錢_具導電性之 八4何形狀可包含_、矩形、多邊形、或各 201015675 種不規則形狀之組合。 工-構強化層1G7具導雜，故可與封裝結構中之電 形 =路，具有接地端之特性;第二覆蓋層 =8 =以控制第—電訊通道115、第二電訊通道μ 與Λ構強化層1〇7間之訊號連通與否，如圖^ A 遽至當不且m一接觸塾105之訊號由第一電訊通道115傳 之固著結構ui與第二具電訊傳遞之固 Π專遞之固著結構120與第五具電訊傳遞之 通道Ϊΐ6錄播^自第二接觸墊113之接地訊號由第二電訊 傳遞之固匕層i07相連接’同時亦傳遞至第三具電訊 印刷、模板印著ί構與接觸整間且可利用網板 厶之方切疴式塗佈、噴墨塗佈、微影技術或其他適 ^，第二電訊通道通單元體1〇0 導r之材料的組合』電= 二道之功能;另-方面’ t ί ^種具導電性之材料的組合，其具有較硬之 電訊通道m 二電訊通道116與第三 & 步之保濩，提升封裝體整體可靠度。 子可能製造程序為：將電 方式形成充填物103喷塗或其他適合之 1〇5、第-並利用微影技術在第一接觸墊 接觸塾113與第三接觸塾m處定義開孔位置；以 7 201015675 或他種適當方式在第—覆蓋層106上 形成、、《構強化層1〇7 ’並在前述接觸塾彳置 =層⑽與沉積第—電訊通道115、第=道= 門T否3第ί覆蓋層108控制電訊通道與結構 巧匕層107間疋否為電轉通或絕緣 ，線層109提供保護，並定義具電訊傳=;= ^裝體中之分佈位置，在;t述第三覆蓋層 筒式塗佈、喷墨塗佈、微馳== 電”護層112，並在其上方擺放具電訊傳 Ο ❷ 元之目的，接續可進以 一 1' …、 刀°1】，形成獨立分離之複數個封裝單 兀。、.歪由上述之一種製造程序，可完成本發 強化設計之電子封裝結構;前述之較佳實施例程= -說明，並非狀限定本㈣。 ㈣餘，、做 圖四A為本發明之第二實施例，為 t之Ϊ子封裝結構剖面圖，圖四B則為對應於圖四A 3 Ξί i實t角示意圖。與前述第—實施例中之第一 構強化層設計，包含第-結構強化層207、第二結構Hi 208、第三結構強化層213、第四結構強化層214與第五妹構 強化層215 ;前述結構強化層可同時或分別利用塗佈、壓:、 黏合或曝光顯影等方式完成於第—覆蓋層撕上方，且 形，可包賴形、矩形、多邊形、或各種不規卿狀之組合， 又其主要分佈位置在電子元件2G4與充填物2G3交界位置上 可減緩該位置材熱膨脹魏不匹配而產生之熱-機械 應力累積’降低佈線層216發生破s之機會並提高第 元體200在使用狀態下之產品可靠度。 衣早 圖玉為本發明之第三實施例’為具有多層結構強化層設 8 201015675The invention discloses an electronic package structure. In detail, the present invention provides a package unit having a structural reinforcement layer design, which is mainly used to reduce the thermal expansion coefficient mismatch between the stress buffer layer and the electronic component, thereby improving the reliability of the signal connection line in the package. degree. The embodiments of the present invention are described in detail below, but the preferred embodiments are merely illustrative and not intended to limit the invention. 2A is a cross-sectional view of an electronic package structure having a structural reinforcement layer design, and FIG. 3B is a schematic perspective view of the first embodiment of the present invention corresponding to FIG. 3a. The first package unit body 1 (8) utilizes the support base plate 101 as a skeleton of the structure, and the electronic component support bottom plate may be a metal material, a non-metal material, a semiconductor material or a combination of the foregoing materials; the bonding layer 2 2) and the electronic component 1 are used on the support () 4 bonding, this electronic element; ^ active electronic components, passive f sub-components, _ components, measured mw combination. The filling material 103 is used to reduce the effect of the electron=screen _\ two stresses, and the filling area can be utilized by the board, the drum coating, the inkjet coating, the lamination, the lithography technique, and the other materials.戦 且 且 且 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 The combination of two materials of electricity H (four) σ money _ with conductivity of 4 4 shape may include _, rectangle, polygon, or a combination of each of the 201015675 irregular shapes. The work-structure strengthening layer 1G7 has a miscellaneous structure, so it can be combined with the electric form in the package structure, and has the characteristics of the ground end; the second cover layer = 8 = to control the first telecommunication channel 115, the second telecommunication channel μ and Λ Whether the signal between the layers 1 and 7 is connected or not, as shown in Fig. 2A, when the signal of the contact 105 is transmitted by the first telecommunication channel 115, the fixed structure ui and the second telecommunication transmission are fixed. The fixed structure 120 and the fifth telecom transmission channel 6 are recorded. The ground signal from the second contact pad 113 is connected by the second telecommunication transmission layer i07', and is also transmitted to the third telecommunication printing. The stencil is printed with a stencil coating, inkjet coating, lithography, or other suitable material for the stencil, and the second telecommunication channel is connected to the material of the unit body. Combination of electricity = two functions; another - aspect 't ί ^ a combination of conductive materials, which have a harder telecommunication channel m two telecommunication channels 116 and third & step protection, upgrade package Overall reliability. The sub-producible manufacturing procedure is: spraying the electric form forming filler 103 or other suitable one, and using lithography to define the opening position at the first contact pad contact 塾 113 and the third contact 塾m; Formed on the first cover layer 106 by 7 201015675 or other suitable means, "construction strengthening layer 1 〇 7 ' and in the aforementioned contact = = layer (10) and deposition of the first telecommunications channel 115, the = channel = gate T No 3 the ί overlay 108 controls whether the telecommunication channel and the structural layer 107 are electrically turned or insulated, the line layer 109 provides protection, and defines the distribution position in the telecom transmission =; = ^ in the package; The third overcoat tube coating, inkjet coating, micro-motor == electric "protective layer 112", and placed above it with the purpose of telecommunications transmission, the connection can be followed by a 1' ..., knife °1], forming a plurality of independent packaging packages. 歪 歪 歪 歪 歪 歪 歪 歪 歪 歪 歪 歪 歪 歪 歪 歪 歪 歪 歪 歪 歪 歪 歪 歪 歪 歪 歪 歪 歪 歪 歪 歪 歪 歪 歪 ; ; ; ; ; ; ; ; (4) (4) Yu, and Figure 4A is a second embodiment of the present invention, which is a tweezers package of t FIG. 4B is a schematic view corresponding to FIG. 4A 3 Ξί i, and the first structural strengthening layer design in the foregoing first embodiment includes a first structural strengthening layer 207 and a second structural Hi 208. The third structural strengthening layer 213, the fourth structural strengthening layer 214 and the fifth structural strengthening layer 215; the structural strengthening layer can be simultaneously or separately coated, pressed, exposed or developed to complete the first cover layer tearing The upper, and the shape may be a combination of a shape, a rectangle, a polygon, or a variety of irregular shapes, and the main distribution position at the boundary between the electronic component 2G4 and the filler 2G3 may slow down the thermal expansion of the positional material and cause mismatch. The heat-mechanical stress accumulation reduces the chance of the wiring layer 216 breaking s and improves the reliability of the product of the element body 200 in use. 衣早图玉 is a third embodiment of the invention 'is a multilayer structure strengthening layer Set 8 201015675

計之電子封裝結構剖面圖。在第三封裝單元體3⑻中，電子元 件304利用接合層302與支推底板301接合，並利用充填物 303達到元件訊號侧之平整性；與前述圖三a、圖三b中本發 明之第一實施例相比較，來自第一接觸墊3〇5、第二接觸墊3〇6 與第二接觸塾307之電子訊號藉由第一佈線層3與第二佈線 層311傳遞至第三封裝單元體3〇〇表層，第一結構強化層3〇8 與第一結構強化層309分別位於前述佈線層下方，並利用第二 覆蓋層313與第四覆蓋層315提供電訊絕緣。其中來自第二接 觸墊306之接地訊號與第二結構強化層3〇9相連通，故第二結 構強化層309可作為第三封裝單元體3〇〇中電子訊號之接地平 面；而第一接觸墊305與第二接觸墊306之訊號藉由具電訊 遞之固著結構321傳遞至封裝體外部。前述之較佳實施例结構 只做-說明’並非魏限定本發明’尤其鱗肋限定結構強 化層與佈線層在電子封裝結構中之對應位置關係。 圖六為本發明之第四實關’為具有結麵化層設計及 夕層金屬訊號層之電子封裝結構剖面圖。第四封裝單元體 中之電子元件404利用接合層402與支撐底板4〇1接合，結 強化層406位於第一佈線層411與第二佈線層412間，主^ 高層與鄰近區域之結構強度，降低封裝體内部材料因 熱膨脹係數不匹配而產生之變形；第二電訊通道4 件404之接地訊號傳遞至結構強化層4〇6，提高整體 =結構強化層406位置除可能如圖六所示介於佈線層間，= β此位於封裝體佈線層之最下或最上方；前述 構只做-說明，並_以限定本發明，尤^ 強化層與佈線層在電子封裝結構中之對應位置=乂限疋、，、。構 圖七為本發明所如之電子職結齡製錢程 ^上之可能排列情形。電子元件502利用二丰^ 體材料基板505上方，利用前述第一實施例中之J 此製造方式完成具有結構強化層設計之封裝單元體5⑴後，; 9 201015675 輩機ΐ鑽孔、雷射鑽孔、乾職 ，子封裝r構封在裝製 元體603利用前述第-實施例中之可 基板可為金屬材料、非金屬材料、半 等體材科或μ材料的組合，且可具有不規則之幾何形狀。 設叶實關’為具有錄結構強化層 f，件之電子封裝結構剖_，圖九B為 1Γ ^ ，本發明第五實施例之傾斜視角示意圖。第五封 =凡體谓中包含複數個電子元件，第—電子元件7〇4與第 -電子7〇件7。5利用接合層γ。2固定於支撐底板7Qi之丄 面，充填物703填充於電子元件間之孔穴，且其上平面與電子 f上平面接近；第一結構強化層、第二結構強化層716、 第三結構強化層717、第四結構強化層718與第五結構強化層 719可同時或分別完成於第一覆蓋層7〇9、第二覆蓋層71〇與 第三覆蓋層711之間’達到降低封裝體内部累積熱.機械應力 之目的，並保護第一電訊通道713、第二電訊通道72〇、第三 ，訊通道721與第四電訊通道722，提升其使用壽命。第一電 Λ通道713將來自第二電子元件705之接地訊號傳遞至第一結 構強化層708，藉此提高第二電子元件705之產品電氣特性； 另一方面，前述結構強化層設計有助擴散第一電子元件7〇4與 第二電子元件705所產生之熱能，降低封裝體整體熱阻値。前 述之較佳實施例結構只做一說明，並非用以限定本發明，尤其 並非用以限定結構強化層與佈線層在電子封裝結構中之對應 位置關係。 ‘ 本發明較佳實施例說明如上，而熟悉此領域技藝，在不脫離本 發明之精神範圍内，當可做些許更動潤飾，其專利保護範圍更 當視後附之申請專利範圍及其等同領域而定。 201015675 【圖式簡單説明】 本發明之較佳實施例將於下述說明中輔以下列圖形做更詳細 的闞述： 圖一為習知具有應力緩衝層設計之電子封裝結構。 圖二為習知内含金屬接地平面設計之電子封裝結構。 圖一 A為本發明之第一實施例，為具有結構強化層設計之電 子封裝結構剖面圖。A cross-sectional view of the electronic package structure. In the third package unit body 3 (8), the electronic component 304 is joined to the support base plate 301 by the bonding layer 302, and the flatness of the component signal side is achieved by the filler 303; and the first embodiment of the present invention is shown in FIG. 3a and FIG. In an embodiment, the electronic signals from the first contact pads 3〇5, the second contact pads 3〇6 and the second contact pads 307 are transferred to the third package unit by the first wiring layer 3 and the second wiring layer 311. The first structural strengthening layer 3〇8 and the first structural strengthening layer 309 are respectively located under the wiring layer, and the telecommunication insulation is provided by the second covering layer 313 and the fourth covering layer 315. The grounding signal from the second contact pad 306 is in communication with the second structural strengthening layer 3〇9, so that the second structural strengthening layer 309 can serve as a ground plane of the electronic signal in the third package unit body 3; and the first contact The signal of the pad 305 and the second contact pad 306 is transmitted to the outside of the package by the telescopic fixing structure 321 . DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT The structure of the foregoing preferred embodiment is merely illustrative of the invention. In particular, the scale rib defines a corresponding positional relationship between the structural strengthening layer and the wiring layer in the electronic package structure. Figure 6 is a cross-sectional view of the fourth package of the present invention as an electronic package structure having a junction layer design and a layer metal signal layer. The electronic component 404 in the fourth package unit body is bonded to the support substrate 4〇1 by the bonding layer 402, and the junction strengthening layer 406 is located between the first wiring layer 411 and the second wiring layer 412, and the structural strength of the main layer and the adjacent region is The deformation of the inner material of the package due to the thermal expansion coefficient mismatch is reduced; the ground signal of the second telecommunication channel 4 404 is transmitted to the structural strengthening layer 4〇6, and the overall position of the structural strengthening layer 406 is increased, as shown in FIG. Between the wiring layers, =β is located at the lowest or uppermost portion of the package wiring layer; the foregoing structure is only described and illustrated to limit the present invention, in particular, the corresponding position of the reinforcing layer and the wiring layer in the electronic package structure = 乂Limited to,,,,. Figure 7 is a possible arrangement of the electronic age-setting system of the invention. After the electronic component 502 is used above the substrate 505, the package unit body 5(1) having the structural reinforcement layer design is completed by the manufacturing method of the first embodiment, and the laser device is drilled and drilled. The hole, the dry work, the sub-package r is encapsulated in the packaged body 603. The substrate in the foregoing embodiment may be a metal material, a non-metal material, a semi-equal material or a combination of μ materials, and may have no The geometry of the rules. Let Ye Shiguan's be a structurally-enhanced layer f, the electronic package structure of the piece is cut, and FIG. 9B is 1Γ^, which is a schematic perspective view of the fifth embodiment of the present invention. The fifth element = a plurality of electronic components are included in the body, and the first electronic component 7〇4 and the first electronic component 77.5 are utilized by the bonding layer γ. 2 is fixed on the back surface of the support bottom plate 7Qi, the filling material 703 is filled in the hole between the electronic components, and the upper plane thereof is close to the upper plane of the electron f; the first structural strengthening layer, the second structural strengthening layer 716, and the third structural strengthening layer 717. The fourth structural strengthening layer 718 and the fifth structural strengthening layer 719 may be simultaneously or separately formed between the first covering layer 7〇9, the second covering layer 71〇 and the third covering layer 711 to reduce the internal accumulation of the package. For the purpose of thermal and mechanical stress, and protecting the first telecommunication channel 713, the second telecommunication channel 72, the third, the channel 721 and the fourth telecommunication channel 722, the service life is improved. The first electrical channel 713 transmits the ground signal from the second electronic component 705 to the first structural enhancement layer 708, thereby improving the electrical characteristics of the second electronic component 705; on the other hand, the structural reinforcement layer design helps diffusion The thermal energy generated by the first electronic component 7〇4 and the second electronic component 705 reduces the overall thermal resistance of the package. The structure of the preferred embodiment described above is only for illustrative purposes, and is not intended to limit the present invention, and is not particularly intended to limit the corresponding positional relationship between the structural strengthening layer and the wiring layer in the electronic package structure. The preferred embodiments of the present invention are described above, and the technical scope of the present invention can be modified without departing from the spirit and scope of the present invention. The scope of patent protection is more dependent on the scope of the patent application and its equivalent fields. And set. BRIEF DESCRIPTION OF THE DRAWINGS [0009] A preferred embodiment of the present invention will be described in more detail in the following description with reference to the following drawings: FIG. 1 is an electronic package structure having a stress buffer layer design. FIG. 2 is an electronic package structure of a conventional metal ground plane design. Figure 1A is a cross-sectional view of an electronic package structure having a structural reinforcement layer design in accordance with a first embodiment of the present invention.

，三B為對應於圖三A，本發明第一實施例之傾斜視角示意 圖。 圖四A為本發明之第二實施例，為具有多個結構強化層設計 之電子封装結構剖面圖。 ，四B為對應於圖四a ’本發明第二實施例之傾斜視角示意 圖五為本發明之第二實施例，為具有多層結構強化層設計之電 子封裝結構剖面圖。 Ϊ六為本發明之第四實關，為具有結構強化層設計及多層金 屬訊號層之電子封裝結構剖面圖。 圖七為本發明所提出之電子封裝結構在製造過程中於上 之可能排列情形。 、 圖八為本發明所提出之電子封裝結構在製造過程中於矩形載 板上之可能排列情形。 A為本發明之第五實施例’為具有多储構強化層設計 與夕個内埋電子元件之電子封裝結構剖面圖。 =九B為對應於圖九a，本發明第五實施例之傾斜視角示意 201015675 【主要元件符號說明】 001 電訊接點 002應力緩衝層 003 電子元件 004訊號連接線 005 絕緣層 010電子元件集合體 012電子封裝 014電子元件 016封裝體上部 ❿ 018突起結構 020第一接觸墊 022第二接觸墊 024 電子元件上部 026金屬線 028第三接觸墊 030焊錫接點 032電子元件下部 034第一導電層(接地層) 036第二導電層 ® 038第三導電層 040插梢 042封裝體底部 044 電路板 046第一導通孔 048第二導通孔 050散熱塊 100第一封裝單元體 101支撐底板 102接合層 12 201015675 103充填物 104 電子元件 105第一接觸墊 106第一覆蓋層 107結構強化層 108第二覆蓋層 109佈線層 110第三覆蓋層 111第一具電訊傳遞之固著結構 118第二具電訊傳遞之固著結構 ❹ 119第三具電訊傳遞之固著結構 120第四具電訊傳遞之固著結構 121第五具電訊傳遞之固著結構 112電訊接點保護層 113第二接觸墊 114第三接觸墊 115 第一電訊通道 116 第二電訊通道 117第三電訊通道 200第二封裝單元體 ® 201支撐底板 202接合層 203充填物 204 電子元件 205接觸墊 206第一覆蓋層 207第一結構強化層 208第二結構強化層 209第二覆蓋層 210第三覆蓋層 13 201015675 211電訊接點保護層 212具電訊傳遞之固著結構 213第三結構強化層 214第四結構強化層 215第五結構強化層 216佈線層 300第三封裝單元體 301支撐底板 302接合層 303 充填物 〇 304電子元件 305第一接觸墊 306第二接觸墊 307第三接觸墊 308第一結構強化層 309第二結構強化層 310 第一佈線層 311第二佈線層 312第一覆蓋層 313第二覆蓋層 ® 314第三覆蓋層 315第四覆蓋層 316第五覆蓋層 317第一電訊通道 318 第二電訊通道 319電訊接點保護層 320 第三電訊通道 321具電訊傳遞之固著結構 400第四封裝單元體 401支撐底板 201015675 402接合層 403充填物 404 電子元件 405接觸墊 406結構強化層 407第一覆蓋層 408第二覆蓋層 409第三覆蓋層 410第四覆蓋層 411第一佈線層 〇 412第二佈線層 413第一電訊通道 414第二電訊通道 415 第三電訊通道 416電訊接點保護層 417具電訊傳遞之固著結構 501封裝單元體 502 電子元件 503佈線層 504基板切割道 ® 505半導體材料基板 601基板 602基板切割道 603封裝單元體 700第五封裝單元體 701支撐底板 702接合層 703 充填物 7〇4 第一電子元件 705第二電子元件 15 201015675 706第一接觸墊 707第二接觸墊 708第一結構強化層 709第一覆蓋層 710第二覆蓋層 711第三覆蓋層 712佈線層 713第一電訊通道 714電訊接點保護層 715具電訊傳遞之固著結構 〇 716第二結構強化層 717第三結構強化層 718第四結構強化層 719第五結構強化層 720第二電訊通道 721第三電訊通道 722 第四電訊通道3B is a schematic perspective view of the oblique view corresponding to the first embodiment of the present invention corresponding to FIG. Figure 4A is a cross-sectional view of an electronic package structure having a plurality of structural reinforcement layers in accordance with a second embodiment of the present invention. 4B is a perspective view corresponding to the second embodiment of the present invention. FIG. 5 is a second embodiment of the present invention, which is a cross-sectional view of an electronic package structure having a multilayer structure reinforcing layer design. The sixth embodiment of the present invention is a fourth embodiment of the present invention, which is a cross-sectional view of an electronic package structure having a structural reinforcement layer design and a multilayer metal signal layer. Figure 7 is a diagram showing the possible arrangement of the electronic package structure proposed in the present invention in the manufacturing process. FIG. 8 is a possible arrangement of the electronic package structure proposed by the present invention on a rectangular carrier during the manufacturing process. A is a fifth embodiment of the present invention' which is a cross-sectional view of an electronic package structure having a multi-storage strengthening layer design and a buried internal electronic component. = Nine B corresponds to FIG. 9a, and the oblique viewing angle of the fifth embodiment of the present invention is shown in 201015675. [Main component symbol description] 001 Telecommunication contact 002 stress buffer layer 003 Electronic component 004 signal connection wire 005 Insulation layer 010 electronic component assembly 012 electronic package 014 electronic component 016 package upper ❿ 018 protrusion structure 020 first contact pad 022 second contact pad 024 electronic component upper 026 metal wire 028 third contact pad 030 solder joint 032 electronic component lower part 034 first conductive layer ( Grounding layer) 036 second conductive layer® 038 third conductive layer 040 insert tip 042 package bottom 044 circuit board 046 first via hole 048 second via hole 050 heat sink block 100 first package unit body 101 support bottom plate 102 bonding layer 12 201015675 103 filler 104 electronic component 105 first contact pad 106 first cover layer 107 structural reinforcement layer 108 second cover layer 109 wiring layer 110 third cover layer 111 first telecommunication transmission fixing structure 118 second telecommunication transmission Fixing structure 119 119 third fixed structure of telecommunication transmission 120 fourth fixed structure of telecommunication transmission 121 fifth fixed structure of telecommunication transmission 112 telecommunication contact protection layer 113 second contact pad 114 third contact pad 115 first telecommunication channel 116 second telecommunication channel 117 third telecommunication channel 200 second package unit body 201 201 support bottom plate 202 bonding layer 203 filling 204 electronic components 205 contact pad 206 first cover layer 207 first structural reinforcement layer 208 second structural reinforcement layer 209 second cover layer 210 third cover layer 13 201015675 211 telecommunication contact protection layer 212 with telecommunication transmission fixing structure 213 third structure Strengthening layer 214 fourth structural strengthening layer 215 fifth structure strengthening layer 216 wiring layer 300 third package unit body 301 supporting bottom plate 302 bonding layer 303 filling material 304 electronic component 305 first contact pad 306 second contact pad 307 third contact Pad 308 first structural reinforcement layer 309 second structural reinforcement layer 310 first wiring layer 311 second wiring layer 312 first cover layer 313 second cover layer 314 third cover layer 315 fourth cover layer 316 fifth cover layer 317 First telecommunication channel 318 second telecommunication channel 319 telecommunication contact protection layer 320 third telecommunication channel 321 telecommunication transmission fixing structure 400 fourth package unit body 401 supporting bottom plate 2 01015675 402 bonding layer 403 filling 404 electronic component 405 contact pad 406 structural strengthening layer 407 first covering layer 408 second covering layer 409 third covering layer 410 fourth covering layer 411 first wiring layer 〇 412 second wiring layer 413 A telecommunication channel 414, a second telecommunication channel 415, a third telecommunication channel 416, a telecommunication contact protection layer 417, a telecommunications transmission fixing structure 501, a package unit body 502, an electronic component 503, a wiring layer 504, a substrate cutting channel, a 505 semiconductor material substrate, a 601 substrate, a substrate 602, and a substrate. Cutting channel 603 package unit body 700 fifth package unit body 701 supporting bottom plate 702 bonding layer 703 filling material 7〇4 first electronic component 705 second electronic component 15 201015675 706 first contact pad 707 second contact pad 708 first structural reinforcement Layer 709 first cover layer 710 second cover layer 711 third cover layer 712 wiring layer 713 first telecommunication channel 714 telecommunication contact protection layer 715 with telecommunication transmission fixing structure 716 second structural strengthening layer 717 third structural strengthening Layer 718 fourth structural strengthening layer 719 fifth structural strengthening layer 720 second telecommunication channel 721 third telecommunication channel 722 fourth telecommunication channel

Claims (1)

201015675 七、申請專利範圍： 1.一種電子封裝結構，至少包含： 單或複數個電子元件支撐底板； 單或複數㈣子元件，佈於前述切底板之表面，該支擇底板 面積可大於，等於或小於該電子元件之面積； 一 單或複數個填充區域，形成於前述電子元件四周之 提供封裝結構上表面之平坦化； 單或複數層之覆蓋材料； 單或複數個電訊接點，形成於前述電子封裝結構之面，且 ❹ ❹ 該點所分佈之表面面積可大於，等於心、於前述之電子 兀•件上表面之面積； 道*形成於前述電子封裝結構電訊接點與電 部電路利用該電訊通道傳遞至 且與前述單 單或複數個結構強化層，形成於前述覆蓋材料間， 或複數個電訊通道相連接。 結構’其中所述結構強化層 料合金或他種具導m以上金屬材 3恳如申請翻第丨項之t子難 i之Ιί封裝結構中之電子元件接地訊號形成二 t如申請專利範圍帛i項之電子 二幾何形狀可包含圓形'矩形、多2形==b 如申請專利細第i項之電子封裝結構，其中所述位於封裝結 17 201015675 蓋材料’具有電之不良導體特性，除作為電㈣ 道間之絕緣㈣外，亦具錢訊倾魏。_為電减 撐底板=之電子封裝結構’其中所述電子元件支 的組合。’材料、非金屬材料、半導體材料或前述材料 微機電晶片或元=:?件、感測元件、測試元件、 項之電子封躲構，針觸之填充區 Ui具有_或_特性之㈣倾成，且具有應力緩衝 該填充區域可利用網版印刷、模板印刷、“式塗 佈、喷墨塗佈、齡、微職術或其他適合式塗 11 f之電子封裝結構，其中所述之電訊通 遇』馮錫、銀、金、銘、皱、銅、錄、 料合金或他種具導電性之材料的組合。、，$屬材 =·如申請專利翻第丨項之電子封裝結構，其中所述 微影技術或其他適合之方式形絲訊接、喷墨塗佈、 18201015675 VII. Patent application scope: 1. An electronic package structure comprising at least: a single or a plurality of electronic component supporting substrates; a single or plural (four) sub-components disposed on the surface of the cutting substrate, the area of the supporting substrate may be greater than or equal to Or less than the area of the electronic component; a single or a plurality of filling regions formed around the electronic component to provide planarization of the upper surface of the package structure; a cover material of a single or multiple layers; a single or a plurality of telecommunication contacts formed in The surface of the electronic package structure, and the surface area distributed by the point may be greater than, equal to, the area of the upper surface of the electronic device; the track* is formed in the electronic package structure telecommunications contact and the electric part circuit The plurality of telecommunication channels are connected to the cover material by the telecommunication channel and connected to the plurality of structural reinforcement layers, or a plurality of telecommunication channels are connected. The structure of the structurally-reinforced layer alloy or the metal material of the above-mentioned type is more than the same as the metal material of the metal element of the above-mentioned article, and the electronic component grounding signal in the package structure is formed as follows. The electronic two-dimensional shape of the item i may include a circular 'rectangular shape, a multi-shaped shape==b, as in the electronic package structure of the patent application item i, wherein the cover material 17 201015675 cover material 'has a poor electrical conductor characteristic, In addition to being the insulation between the electricity (4) roads (4), it also has the money to sway. _ is an electronic package structure in which the bottom plate = the combination of the electronic component branches. 'Materials, non-metallic materials, semiconductor materials or the aforementioned materials MEMS wafers or elements =: parts, sensing elements, test elements, electronic envelopes of the items, the filling area Ui of the needle touch has _ or _ characteristics of (four) And the stress buffering the filling area may utilize screen printing, stencil printing, "coating, inkjet coating, age, micro-skills or other suitable coatings for electronic packaging structures, wherein the telecommunications "Experience" Feng Xi, silver, gold, Ming, wrinkle, copper, recording, alloy or a combination of materials of its kind.,, $material = · If you apply for a patent, turn the electronic package structure of the third item, Wherein the lithography technique or other suitable means of wire-contacting, inkjet coating, 18
TW097137919A 2008-10-02 2008-10-02 An electronic packaging structure with enhanced design TWI426585B (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105720007A (en) * 2014-11-17 2016-06-29 矽品精密工业股份有限公司 Electronic package structure and method for fabricating the same
TWI756000B (en) * 2020-12-28 2022-02-21 欣興電子股份有限公司 Chip package structure and manufacturing method thereof

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI283055B (en) * 2005-01-12 2007-06-21 Phoenix Prec Technology Corp Superfine-circuit semiconductor package structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105720007A (en) * 2014-11-17 2016-06-29 矽品精密工业股份有限公司 Electronic package structure and method for fabricating the same
TWI756000B (en) * 2020-12-28 2022-02-21 欣興電子股份有限公司 Chip package structure and manufacturing method thereof

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