TW201011883A - Semiconductor package having isolated inner lead - Google Patents

Abstract

Disclosed is a semiconductor package having isolated inner lead. A chip is disposed on a leadframe and is encapsulated by a molding compound. Leadframe includes a plurality of usual leads, the isolated inner lead and a short outer lead. Each lead has an inner lead portion having a first finger at its inner end. The isolated inner lead is completely encapsulated by the molding compound. The outer lead has a portion inside the molding compound and the other portion extending from the molding compound. At least one of the inner lead portions of the leads is located between the isolated inner lead and the short outer lead to electrically-isolated separate the both. Two ends of the isolated inner lead are formed as a second finger and a third finger not covered by the chip. The first and second fingers are arranged along an outside of a first side of the chip, the third finger and a fourth finger of the outer lead are arranged along an outside of a second side of the chip. The jumper wire connects the third finger and the fourth finger to span the inner lead portion therebetween so that the lead's order can be adjusted without affecting wire-bonding. The package is specially applied to wire-bonding structure of multi-chip stacking.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a wafer is packaged, in particular, to a leadframe-based semiconductor package structure. [Prior Art] In many semiconductor package types, the ball grid array (BGA) type uses a substrate to carry a wafer, and the substrate-based circuit can be separated in different metal layers and plated through holes.鬣 鬣 , , , , , , , , rn rn rn rn rn rn rn rn rn rn rn rn rn COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL The package type ^ is based on the lead of the lead frame as 晶片F as the wafer carrier. It is always attached to the lead of the lead frame. Although the back of the cymbal is sturdy, although it can be cheaper, it has the limitation of the wire area and the difficulty of ordering the position of the foot. This is because the lead frame is cited. The foot can only be a single layer g ""added and mostly covered by the wafer, and the lead of the lead frame is molded. ^ π, must be clamped by the upper and lower molds, can not be like the multiple circuit metal of the substrate can be used Electrically isolated and layered. Related lead frame base semi-conducting seal belly sister * 4. Package structure This has been disclosed in China Patent No. 1287876 r 1Α Feng conductor package" patent case. 1 is a schematic cross-sectional view of a conventional lead frame of a ^ ^ _ storm bottom + conductor package structure 100, and FIG. 2 is a lead frame 12 of the base semiconductor package structure of the conventional lead frame, which is in the seal body 3 Partial plan view. Fig. 3 is a schematic plan view showing a part of the wire bond between the lead dies and the lead frame pins in the sealant body. The conventional wire edge slab base semiconductor package structure 6 201011883 100 mainly includes a colloid 110 a lead frame 120, at least one wafer 130 and 170, and a plurality of first bonding wires 141 and second bonding wires 142. The lead frame 120 has a plurality of pins 113 for carrying the wafers 130 and 170, and A plurality of short pins 126. Each of the pins 121 has a leg portion 124 in the encapsulant 110 and a leg portion 125 extending outside the encapsulant 110. The first wafer 1 3 0 The back side is attached to the inner leg portion 124 of the pin 121 by an adhesive tape. Therefore, the bearing portion of the inner leg portion 124 covered by the wafer 130 cannot be used for wire bonding. For example, the first and third figures are shown. As shown, usually the first bonding wires 141 are connected to the first wafer 1 The plurality of first electrodes 131 to the inner legs 124 extend beyond the inner ends of the first wafers 130 and the inner ends of the short pins 126. The second wafer 170 is stacked on the first wafer 130. And as shown in FIGS. 1 and 3, the plurality of second electrodes 171 of the second wafer 170 are connected to the second soldering wires 142 to the inner ends of the first wafers 130 and φ. The inner ends of the short pins 126. Therefore, the wire-bonding area of the wafer is limited and crowded, especially when multi-wafer stacking is performed, and the wire density is increased. The connection diagrams of the first bonding wires 141 and the second bonding wires 142 are shown in the figure. If the first bonding wires 141 and the second bonding wires 142 are not misaligned, the pins are The order of the positions of 121 is fixed. If the order of the positions of the feet is barely adjusted, the wire must be crossed and misaligned, resulting in a small gap between the wire and the wire at the intersection, which is easily short-circuited by the mode flow, so There is difficulty in adjusting the order of the feet. 7 201011883 Another US patent 5,206,536 proposes an The semiconductor package structure of the pin order adjustment, but it is a "Lead-On-Chip" (LOC), the pin is a knee strap attached to the active surface of the wafer, and the tape has a comb shape. The conductive layer is used as an electrical relay transfer between the pin and the wafer electrode to adjust the pin order. However, this technique is necessary for attaching pins and comb-like conductive layers on the active surface of the wafer, and cannot be transferred to "wafer-on-pin type" (COL,

Chip-On-Lead semiconductor packages cannot be used in multi-chip stacks. SUMMARY OF THE INVENTION In view of the above, the main object of the present invention is to provide a semiconductor package structure using independent internal leads, which can achieve the order adjustment of the lead pins of the lead frame without affecting or changing the limitation of the lead frame on the periphery of the wafer. The wire bonding area is particularly suitable for the wire bonding structure of the multi-wafer stack. The object of the present invention and solving the technical problems thereof are achieved by the following technical reference. According to the present invention, a semiconductor package structure using a separate inner lead mainly comprises a glue body, a lead frame, a first wafer, a plurality of first bonding wires, and a jumper bonding wire. The lead frame comprises a plurality of pins, a separate inner pin and an outer pin, the independent inner pin is completely formed in the seal body, and the outer lead is partially formed in the seal body and extends In addition to the sealant, each of the pins has an integral connection between the foot within the sealant and a foot extending beyond the sealant, at least one of the inner legs The electrical isolation is between the independent inner pin and the outer pin. The first wafer 8 201011883 is disposed on the lead frame and sealed by the sealant. The first wafer has a plurality of first electrodes, and the inner ends of each of the inner legs are formed not to be the first wafer. Covering the first finger, the two ends of the independent inner pin are formed as a second finger and a third finger not covered by the first chip, and the outer pin has a not a fourth finger of the wafer, wherein the first finger and the second finger are arranged on a first side of the first chip, and the third finger and the fourth finger are arranged at a second side of one of the first wafers. The first bonding wires are connected to the first electrodes of the first chip to the first fingers of the inner legs and the second fingers of the independent inner pins. The jumper line connects the third finger of the independent inner pin with the fourth finger of the outer pin and spans at least one of the inner legs. The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. In the foregoing semiconductor package structure, a chip may be further included, and the contact is attached to the lead frame such that the independent inner pin is electrically insulated between the inner leg portions. In the foregoing semiconductor package structure, the back surface of the first wafer may be formed with a first adhesive layer to place the first wafer on the lead frame. In the foregoing semiconductor package construction, the jumper bond wire may be located on the lead frame and adjacent to the second side of the first wafer. In the above semiconductor package structure, in the plan view of the semiconductor package structure, the jumper bond wire may be substantially parallel to the second side of the wafer 201011883.

In the foregoing semiconductor package structure, a first chip may be further disposed on the first wafer. In the foregoing semiconductor package structure, one of the second wafers may be formed with a second adhesive layer to place the second wafer on the wafer. In the foregoing semiconductor package structure, the second wafer is stepped on the first wafer and has a lateral protrusion that extends beyond the second side of the ® wafer, wherein the jumper is hidden in the Below the cross section. In the foregoing semiconductor package construction, the second adhesive layer may more closely cover the lateral convex portion. In the foregoing semiconductor package construction, the lead frame may further include a plurality of short pins which are shorter than the pins, and the first wafer is disposed on the short pins. Φ In the foregoing semiconductor package structure, the first side and the second side of the first wafer may be parallel to each other, and the short leads are oriented toward the first side. In the above semiconductor package structure, the first side and the second side of the first wafer may be perpendicular to each other. In the foregoing semiconductor package construction, the outer legs of the pins may be dispersed on two opposite parallel sides of the encapsulant. In the foregoing semiconductor package structure, the lead frame may further comprise a plurality of side support pads arranged on the inner legs of the pins, and the first stepped first convex protrusions are different The side of the side inner end is provided with a plurality of 10 201011883 sides for supporting the first wafer. In the foregoing semiconductor package structure, the side support pads may have a plurality of mold flow holes for filling the sealant. In the foregoing semiconductor package construction, the fourth finger can extend inwardly to cause the first wafer to be supported. In the foregoing semiconductor package construction, the inner leg portions may be width-amplified in a specific section below the first wafer to form a plurality of first locks. In the aforementioned semiconductor package construction, the individual inner leads are widened in a particular section below the first wafer to form a second lock. A π 蛩 蛩 篦 篦 锁 锁 锁 锁 锁 ❹ ❹ ❹ 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在The first finger, the second finger and the third, segment 'to make the covers.独立 not covered by the first wafer, the independent inner bow and the foot can be the same layer metal structure as the semi- & dry conductor package of the invention. It can be seen from the above technical solutions that the following advantages and effects are obtained: 1. By connecting the two ends of a separate inner pin as a connection without using a jumper wire to connect the pin pins in the gray that are not covered by the chip. Refers to and crosses at least the finger of the bow and the foot of the foot and the foot of the foot. The jump line of the 2010-11883 jumper can be separated from the common wire bond line on the lead frame, but the wire can be wired. At the same time, the pin order adjustment is formed and does not affect or can achieve the change of the lead wire in the limited wire-bonding area around the wafer', which is particularly suitable for the multi-chip stacking wire bonding structure. Second, the use-mount is attached to the lead frame so that the independent inner pins which are not covered by the wafer can be electrically insulated between the inner legs.

❹ 3. In a multi-wafer stack application, a second wafer is stepped over the first wafer to form a lateral protrusion that extends beyond the side of one of the non-wired regions of the first wafer to enable the The jumper fresh line can be hidden under the lateral protrusion without the risk of the exposed line being outside the sealant and the line being punched. Fourth, it is used to bridge the pins outside the independent inner leads so that the fingers extend inward to the die bond region to increase the load bearing support of the wafer. The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which Therefore, only the parts related to this case are displayed, and the components displayed are not drawn in the actual number, shape and size ratio. Some ratios of scales and other related sizes have been modified or simplified to provide clearer The description, actual implementation of the number, shape and size ratio is an optional design 'detailed component layout may be more complicated. 12 201011883 In accordance with a first embodiment of the present invention, a semi-guide boat package construction using separate inner pins is illustrated in FIG. 4 as a cross-sectional schematic circle including a cross-cut jumper wire. The semiconductor package structure 200 using the independent inner leads mainly comprises a sealant 21, a lead frame 220 as shown in FIG. 5, a first wafer 23, a plurality of first fresh wires 241, and a jumper solder. Line 250. In this embodiment, the semiconductor package structure 200 using the independent inner leads is applied to the multi-wafer stack, and further includes a first wafer 270 disposed on the first 曰μ罝230 on. Figure 5 is a partial plan view of the leadframe 220 within the sealant 210. Fig. 6 is a plan view showing a portion in which the first and second wafers 230, 270 and the lead of the lead frame 22 are wire-bonded in the semiconductor package structure 200. Fig. 7 is a partially enlarged plan view showing the semiconductor package structure 2 in the wire bonding region. Figure 8 is a partially enlarged plan view of the semiconductor package structure 2 〇〇 in the jumper region. Fig. 9 is a partial cross-sectional view showing the semiconductor package structure 200 in Fig. 8. The first drawing is not a schematic diagram of the jumper electrical connection in the semiconductor package structure. The encapsulant 210 is an electrically insulating thermosetting resin mixture, such as an epoxy molding compound (EMC), for sealing the first wafer 230, internal components, and pins of the lead frame 220. . The lead frame 220 is made of a sheet of all-metal material and may be made of copper, iron or an alloy thereof. As shown in FIG. 5, the lead frame 22 includes a plurality of pins 221, a separate inner pin 222, and an outer pin 223. The independent inner leg 222 is completely formed in the sealant 210, so it does not have the outer leg 13 201011883. The outer lead 223 is partially formed in the encapsulant 2 ι and extends outside the encapsulant 210. The outer lead 223 is electrically connected to the independent inner lead 222 but is not independent of the internal lead. The feet 222 are directly connected. Moreover, each of the pins 221 has an integrally connected leg portion 224 in the encapsulant 210 and an outer leg portion 225 extending beyond the encapsulant 21〇. At least one inner leg portion 224' of the inner leg portion 224 is electrically isolated between the independent inner pin 222 and the outer pin 223. In the present embodiment, there are two inner leg portions 224' between the independent inner pin 222 and the outer pin 223. Preferably, the independent inner pins 222 are in the same layer metal structure as the pins 221, so the independent inner pins 222 and the inner legs 224 of the pins 221 are horizontally spaced apart. There is no overlapping relationship between them. Therefore, the independent inner pins 222 are disposed in the same manner as the inner legs 224 of the pins 221; and the outer pins 223 are disposed in the same manner as the outer legs of the pins 221 225 ° G As shown in FIG. 4 , the first wafer 230 is disposed on the lead frame 22 0 and sealed by the sealant 210 . The first wafer 230 has a plurality of first electrodes 231 . As shown in FIGS. 4 and 6, a back surface 232 of the first wafer 230 is attached to the independent inner lead 222, and the inner leg portions 224 are aligned with the independent inner leads 222 and pass through the wafer setting area. Therefore, the back surface 232 of the first wafer 230 is also attached to the inner leg portions 224 at the same time. In an embodiment, the back surface 232 of the first wafer 230 may be formed with a first adhesive layer 235 to place the first wafer 230 on the lead frame 220. As shown in Figures 6 and 7 'every 14 201011883

Within the inner leg portion 224, the ribs are less than A, and the first finger 201 is not covered by the first wafer 23 . Further, as shown in the flute z, as shown in FIGS. 4 and 6, the two ends of the independent inner lead 222 are formed such that one of the wind horses is not covered by the first wafer 23

The second finger 202 (particularly seen in Figure 7) and the third finger 2〇3 (see in particular Figure 8). In addition, as shown in FIGS. 4, 6, and 8, the outer lead 223 has a fourth finger 204 that is not covered by the first die 23, wherein the first finger 201 and the second pin The second finger 233 is arranged on one of the first sides 233 of the first wafer 230 (as shown in FIG. 7 ), and the third finger 203 and the fourth finger 2 〇 4 are arranged on the first chip. One of the second sides 234 of 230 (as shown in Figure 8). Therefore, the area adjacent to the first side 233 can be used as a "wafer area in the lead-type J semiconductor package, and the area adjacent to the second side 234 can be used as a "wafer on the lead" semiconductor package. The jumper transfer area does not interfere with each other. In the present embodiment, as shown in Fig. 6, the first side 233 and the second side 234 are two corresponding sides of the first wafer 230 in parallel. The first bonding wires 241 and the jumper bonding wires 250 are formed by wire bonding. As shown in FIGS. 4, 6 and 7, the first bonding wires 241 are connected to the first electrodes 201 of the first wafer 230 to the first fingers 201 of the inner leg portions 224 and the independent The second finger of the inner pin 222 is 02. Since the first bonding wires 241 connecting the first electrodes 231 to the first fingers 201 are in a common form, the first electrodes 231 are connected only in the sixth and seventh figures. The first bonding wires 241 to the portion of the second finger 202. 15 201011883 As shown in Figures 4, 6 and 8 'the jumper wire 25 is connected to the third finger 203 of the independent inner pin 222 and the fourth finger 204 of the outer pin 223 and crosses the bit The inner leg portion 224 between the two. In the present embodiment, the jumper wire 250 spans the two inner legs 224. Except that when the number of the individual inner pins 222 and the outer bow pins 223 is plural, the jumper wire 250 can span at least the independent inner pin 222 or the outer pin 223 (as shown in FIG. 8). Preferably, the jumper wire 25 is located on the lead frame 220 and adjacent to the second side 234 of the first die 230, so that the first bond wires 241 and the jumper wire 25 are 〇 can be formed in the same wire bonding step without interfering with each other. As shown in FIG. 8, in the plan view of the semiconductor package structure, the jumper wire 250 can be substantially parallel to the second side 234 of the wafer 23 to avoid the impact of the mold flow. A displacement is generated that would contact the second side 234 of the wafer 2 3 . It can be further explained from Fig. 10 that the effect of the order adjustment of the position of the "wafer on the pin G" line is not affected. One of the first bonding wires 241 can connect the first pad 231 of the first chip 23 to the second finger 202 of the independent inner pin 222 without having to cross the adjacent first fresh wire 241. Conducted to the third finger 203 of the separate inner pin 222. The independent inner lead 222 of the trace on the back side of the first wafer 23 can move the third contact 203 away from the normal wiring area where the first fresh lines 241 are formed. One end of the jumper wire 25A is bonded to the third finger 203 of the independent inner pin 222, spans the inner leg 224 of the at least one general pin 221 and causes the jumper wire 250 to be another - 16 201011883 The terminal is bonded to the fourth finger 2〇4 of the outer pin 225. Therefore, the -th pad 231 electrically connected to the second die 230 can skip one or the upper leg 225 of the upper pin 221, and can be adjusted in the order of the pin. In the embodiment, the order of the pins is adjusted by skipping the two outer legs 225 (as shown in Fig. 6), which is not possible with the conventional "wafer-on-pin" semiconductor package architecture.

The connection between the independent inner lead 222 and the jumper bonding wire 250 in the lead frame base semiconductor package structure, especially the "wafer on the pin type", makes the jumper fresh line 25〇 The finite wire bonding region formed with the first bonding wires 241 can be away from each other and can be formed simultaneously with the first bonding wires 241 in the same wire bonding step, so that the order of the "wafer-on-pin type" pin can be adjusted and The limited wire area that does not affect or change the "wafer on the pin type" is more suitable for the wire bonding structure of the multi-wafer stack. In addition, since the independent inner lead 222 is not clamped by the upper and lower molds during molding, the semiconductor package structure 20 may further include a patch 260 attached to the lead frame 220 so that both ends thereof are not The individual inner leads 222 covered by the first wafer 230 can be electrically insulated between the inner legs 224. In this embodiment, the patch 260 is located within the footprint of the second wafer 230. As shown in FIG. 4, in a multi-wafer stacking operation, the semiconductor package structure 200 may further include a second wafer 270 disposed on the first crystal #230. The back surface 272 of the second wafer 270 can be formed with a second adhesive layer 273 ′ so that the second wafer 270 is disposed on the first wafer 230 of 17 201011883 and electrically connected by a plurality of second bonding wires 242 . The plurality of second electrodes 271 of the second wafer 27 are connected to the first fingers 201 of the pins 221 and the second fingers 202 of the independent pins 222, or one or more second bonding wires 242 Directly connected to the first electrode 230 having the same signal or the same function as the corresponding first electrode 231 ′, the wire bonding density of the wire bonding area is more dense, and any intersection of the bonding wires is easy to have a short line of the wire. . Preferably, as shown in FIGS. 4 and 8, the second wafer 270 is stepped over the first wafer sheet 230 and has a lateral protrusion 274 which extends beyond the first wafer 23 . The second side 234 ′, wherein the jumper wire 250 is hidden under the lateral protrusion 274 (as shown in FIGS. 8 and 9 ), the jumper wire 25 〇 does not have a line at the The risk of sealing the exterior of the body 210 and the line. More preferably, the second adhesive layer 273 can extend further and cover the underside of the lateral protrusion 274 to prevent the jumper wire 250 from accidentally touching the back surface 272 of the second wafer 27 (as shown in FIG. 9). ). However, without limitation, in different embodiments, the second wafer 270 may also be vertically stacked with the first wafer 23'. A spacer (such as a dummy wafer) or a covered layer may be disposed between the wafers. (FOW, Film-Over-Wire), to maintain a wire gap between the wafers, the jumper wire 250 may not be located below the second wafer 270. In the specific structure of the embodiment, the lead frame 220 may further include a plurality of short pins 226, which are shorter than the pins 221, and the first wafer 230 is not disposed on the short pins 226. Above. The first side 233 and the second side 234 of the first wafer 230 are parallel to each other, and the inner ends 226A of the short pins 226 are directed toward the ― 18 201011883 side 233 . In an embodiment, when the wafer is used in a lead-on-type architecture, particularly when applied to a multi-wafer stack, the first wafer 23 is supported by the legs 224 within the pins 22^, and even the first The wafer set of the two-wafer MO is slightly insufficient in strength. The present invention further proposes several solutions herein. Preferably, as shown in FIGS. 6 and 8, the fourth finger 204 of the outer lead 223 can extend inwardly to the first wafer 23QU cover area to enable the first wafer 23 of the branch. . In another preferred configuration, as shown in FIGS. 5 and 6 , the lead frame 22 另 can further include a plurality of side sills 227 disposed on the inner legs 224 of the pins 221 . On both sides, to support the 23rd. More specifically, the side support pads 227 can have a plurality of mold flow holes 227 Α for filling the sealant 210, and have mold flow control and dispersion, and the side support pads 227 are further The encapsulant 21 has a good bonding effect. In this embodiment, the inner leg portions 224 are enlarged in width to form a plurality of first locking pads 228 under one of the first wafers 23 . The individual inner leads 222 are width-amplified in a particular section below the first wafer 230 to form a second lock pad 229. The first locking 228 and the second locking pad 229 can be linearly arranged to strengthen the supporting force on the first wafer 230 and the inner leg 224 and the independent inner pin 222 are sealed and locked. In the sealant 210, there is no problem of bowing displacement and peeling. According to a second embodiment of the present invention, another semiconductor package structure is illustrated in the eleventh circle of the lead frame in the body of the seal body 19 201011883 plan view and the internal wafer and lead frame pin wire connection of the 12th figure The elements that are in the same function as the first embodiment will be denoted by the same names and the drawings, and will not be described again.

As shown in FIG. 11, one of the lead frame 220 included in the semiconductor package structure includes a plurality of pins 221, a separate inner pin 222, and an outer pin 223. Wherein each of the pins 221 has a body connection 224 in the seal body and a foot 225 ' extends to the outer end of the inner leg 224 One finger 201. The independent inner lead 222 is completely formed in the seal body, and the two ends of the independent inner lead 222 are formed as a second finger 2 〇 2 and a third finger 203 ′, wherein the second finger 202 It is arranged in the same group adjacent to the first fingers 2〇1. The outer lead 223 is partially formed in the sealant 210 and extends outside the sealant, and the outer lead 223 has a fourth finger 204' which is arranged adjacent to the third finger 203. In another group. At least one inner leg portion 224 of the inner leg portion 224 is electrically isolated between the independent inner pin 222 and the outer pin 223. In the present embodiment, the outer leg portion 225 of the pins 221 is dispersible on two opposite parallel sides of the encapsulant. As shown in FIG. 12, the first wafer 230 is disposed on the lead frame 220 and sealed by the sealant. The first wafer 23 has a plurality of first electrodes 231' as one of the first wafers 230. The back side is attached to the inner leg portion 224 and the independent inner pin 222, the first finger 201 of each inner leg portion 224, the second finger 202 and the third finger 203 of the independent inner pin 222, and The fourth finger 204 of the outer lead 223 is not covered by the 20 201011883 first chip 230, wherein the first finger 201 and the second finger 202 are arranged on one of the first wafers 23 The first side 233, the third finger 203 and the fourth finger 204 are arranged on the second parallel side 23 of the first wafer 203. In this embodiment, the first side 233 of the first wafer 230 and the second side 234 are perpendicular to each other. Therefore, the short pins can be omitted and all or most of the pins 221 can be omitted. Can be used to support the first wafer 23〇. In addition, the first bonding wires 241 are connected to the first electrodes 23 1 of the first die 230 to the first fingers 201 of the inner leg portions 24 and the independent inner pins 222. The second finger 202 is such that the first side 233 of the first wafer 230 is a general wire bonding region. The jumper wire 250 is connected to the third finger 203 of the independent inner pin 222 and the fourth finger 2 0 4 of the outer pin 2 2 3 and spans at least one of the inner chat portions 224 ′′ The second side 234 of the first wafer 230 is an electrical jumper region of the pin. Therefore, it is possible to achieve the "chip on-pin type" pin φ order adjustment and does not affect or change the "wafer on pin type" limited wire bonding area. The above description is only a preferred embodiment of the present invention and is not intended to limit the scope of the invention. The scope of the present invention is defined by the scope of the appended claims. Any person skilled in the art can make some modifications or modifications to the equivalent embodiments by using the technical content disclosed above, but the content of the technical solution of the present invention is made according to the technical essence of the present invention without departing from the technical solution of the present invention. Any simple modification, equivalent change and modification are still within the scope of 21 201011883 of the technical solution of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view showing a conventional lead frame semiconductor package structure. Fig. 2 is a partial plan view showing the lead frame of the conventional lead frame base semiconductor package structure in the seal body. Fig. 3 is a plan view showing the plane connection between the wafer and the lead frame pins in the conventional lead frame semiconductor package structure.

Fig. 4 is a cross-sectional view showing a semiconductor package structure using a separate inner lead according to a first embodiment of the present invention, including a cross-cut jumper. The first embodiment is a partial plan view of the lead frame of the semiconductor package according to the first embodiment of the present invention in the sealant body. The present invention is directed to a flat wire connection between a wafer in a semiconductor package and a lead frame lead in accordance with a first embodiment of the present invention. Φ : A partially enlarged plan view showing the inner wiring region of the semiconductor package in accordance with the first embodiment of the present invention.

9 _ 1 〇 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Schematic diagram of the electrical connection in the middle jumper. The semiconductor package of the embodiment is a partial plan view of the lead frame of another semi-conductor 22 201011883 body package structure in accordance with the second embodiment of the present invention. The figure is shown in the semiconductor package structure according to the second embodiment of the present invention, and the plane of the wafer and the lead frame are connected by a flat circle.不 不 ' [Main component symbol description] ❹ 100 lead frame base semiconductor package structure 110 sealant 124 inside chat part 203 first 栺 222 蜀 蜀 蜀 内 内 224 224 224 鲫 226 226 226 内121 pin 126 short pin 131 first electrode 142 first - fresh wire 171 second electrode made 202 first finger 120 lead frame 125 outer leg portion 13 〇 first wafer 141 first bonding wire 170 second wafer 1 200 semiconductor Package structure 201 first finger 221 221 pin 224 inner leg 226 short bow foot 227A wedge flow hole 231 234 first electrode side 232 back 235 first adhesive 204 fourth finger 210 sealant 220 lead frame 223 external lead Foot 225 outer leg 227 side support pad 229 second lock pad 230 first wafer 2 3 3 first side edge layer 23 201011883 241 first bond wire 250 jumper bond wire 270 second wafer 273 second adhesive layer 242 242 Second bonding wire 260 patch 271 second electrode 274 lateral convex portion 272 back

twenty four

Claims (1)

201011883 X. Patent application scope: 1. A semiconductor package structure comprising: a gel; a lead frame comprising a plurality of pins, an independent inner pin and an outer a pin, the independent inner pin is completely formed in the seal body, the outer lead is partially formed in the seal body and extends outside the sealant, wherein each pin has one of the integral connections The inner leg of the sealant body and a leg extending beyond the sealant body, at least one of the inner leg portions being electrically isolated between the independent inner pin and the outer pin; The wafer is disposed on the lead frame and sealed by the sealant. The first wafer has a plurality of first electrodes, and an inner end of each inner leg is formed as a first layer not covered by the first wafer. Connected to #, the two ends of the independent inner pin are formed so as not to be covered by the first wafer, and the second pin is not covered by the first wafer. The fourth finger 'the first finger and the second finger are arranged on the first side of the first chip, and the third finger and the fourth finger are arranged on the first chip a second side; the first electrode of the wafer to the plurality of first bonding wires connecting the inner leg portions The first finger and the pin of the single pin; and a jumper wire connecting the third finger of the independent inner pin and the fourth finger of the outer pin and crossing at least - the inner feet. The semiconductor package structure as described in claim 1, further comprising a chip attached to the lead frame, so that the independent inner pin is electrically insulated 25 2 201011883. Between the feet. 3. The semiconductor package structure of claim 1 or 2, wherein the back side of the first wafer is formed with a first adhesive width to allow the first wafer to be disposed on the lead frame. 4. The semiconductor package structure of claim 1, wherein the jumper wire is located on the lead frame and adjacent to the second side of the first wafer. Φ 5. The semiconductor package structure of claim 4, wherein the jumper bond wire is substantially parallel to the second side of the wafer in a plan view of the semiconductor package structure. 6. The semiconductor package structure of claim 1, further comprising a second wafer disposed on the first wafer. 7. The semiconductor package structure of claim 6, wherein a second adhesive layer is formed on one of the back sides of the second wafer such that the second wafer is disposed on the first wafer. The semiconductor package structure of claim 7, wherein the second wafer is stepped over the first wafer and has a lateral protrusion that extends beyond the second side of the first wafer The edge, wherein the jumper wire is hidden under the lateral protrusion. 9. The semiconductor package structure of claim 8, wherein the second adhesive layer extends further and covers the underside of the lateral protrusion. 10. The semiconductor package structure of claim 1, wherein the lead frame further comprises a plurality of short pins which are shorter than the pins, and the first chip is not disposed on the short leads. foot. 26 201011883 Conductor package construction, with side edges parallel to each other. Wherein, and 11, the first side of the semi-first wafer and the inner end of the second of the short pins are oriented toward the first 12, as in the scope of claim 1 The semiconductor package structure of claim 1, wherein the first wafer "the first side and the second side are perpendicular to each other. 13. The semiconductor package structure of claim 12, wherein the outer legs of the pins are dispersed on two opposite parallel sides of the encapsulant. 14. The semiconductor package structure of claim 1, wherein the back side of the first wafer is attached to the inner leg and the specific area of the independent inner pin to make the first connection The second finger and the third finger are not covered by the first wafer. The semiconductor package structure as described in claim 1 wherein the independent internal contact is in the same layer metal structure as the pins. 27