201011881 凡、贫明說明： 【發明所屬之技術領域】 I發明係有關於-種半導體封裝件及其晶片承載 件，尤指一種四邊扁平無外導腳之半導體封裴件 •用之導線架結構。 職 【先前技術】 傳統導線架式半導體㈣件係於—導線架之晶片座 上接置一半導體晶片，再利用打線及封膠作業，以形成包 ❹覆銲線及該半導體晶片之封裝膠體；其中用以 封裝膠體多為散熱性差之環氧樹脂(Ep〇xy —: 料’因此半導體晶片於運作時所產生之熱量將無法經由^ 裝膠體有效散逸至外界，造成敎i 、、' 半導體晶片之性能。纟…量逸政效率不佳而影響到 = 圖，為解決前述傳統⑽架式半導體封 =件的放熱問題，業界遂發展出—種四邊扁平無外導腳 Q=Flat N，leaded，㈣)半導體封裝件，其特徵在 F、投置有外導腳，即未形成有如習知四邊形平面(Quad at Package，QFP)半導體封裝件中用 之外導腳，以縮小半導體封梦杜十p二 电/·生運接 〜m 千等體封裝件之尺寸，同時該㈣半導 :封裝件1之導線架12的晶片座12!底面及導腳122底 Γ係外㈣封歸體15，以使該㈣半導體封裝件1 =用表W技術(謝)藉該導腳122外露底面，亦 (s | 冬端（tenninal )間隔銲錫材料而形成銲錫接合 (⑹齡J〇int)’進而電性連接至電路板卞上之銲塾 111021 5 201011881 〇同夺使《亥B曰片座121底面透過銲錫材料而接置於該 電路板17之-接地面（gr〇und piane)17l上，進而使接 ，於該晶片S1211之半導體晶片u運作所產生之熱量 得以透過該晶片座121而傳導至該接地面171，以有效解 决傳4* ‘線木式半導體封裝件散熱不佳問題。相關之㈣ 半導體封袭件技術可參見美國專利帛6’ 143, 981、 6,198, 171、6, 208, 020、6,400,004、6,433, 277、 6,583,499、6, 642, 609、6, 661，083、6, 696, 749、 ❹=967，125、6’979’866 及 7,030,474 號案；且該 QFN 半 導體封裝件之尺寸設計係依國際規範（JEDEC M0-220)所 規定。201011881 Where the invention is poor: [Technical field to which the invention pertains] The invention relates to a semiconductor package and a wafer carrier thereof, and more particularly to a semiconductor package having a four-sided flat external guide pin and a lead frame structure for use . [Previous Technology] A conventional lead frame semiconductor (4) device is connected to a wafer holder on a wafer holder of a lead frame, and then a wire bonding and sealing operation is performed to form a package bonding wire and an encapsulant of the semiconductor wafer; The epoxy resin (Ep〇xy-: material) used for encapsulating the colloid is often poor in heat generated by the operation of the semiconductor wafer, so that the heat can be effectively dissipated to the outside through the colloid, resulting in a semiconductor wafer. The performance of the 纟 量 量 逸 效率 效率 效率 = = = 量 量 量 量 量 量 量 量 量 量 量 量 量 量 量 量 量 量 量 量 量 量 量 量 量 量 量 量 量 量 量 量 量 量 量 量 量 量 量 量 量 量 量 量(4) a semiconductor package characterized in that F is placed with an external lead, that is, a guide pin is not formed in a conventional quad-package (QFP) semiconductor package to reduce the semiconductor seal Ten p two electric / · raw transport connection ~ m thousand body package size, while the (four) semi-conductor: package 1 of the lead frame 12 of the wafer holder 12! bottom and guide legs 122 bottom of the outer (four) seal body 15, to make the (four) semiconductor Mounting 1 = Using the W technology (Thanks) to expose the bottom surface of the lead 122, also (s | winter end (tenninal) spacing solder material to form a solder joint ((6) J〇int)' and then electrically connected to the board塾 之 021 021 021 021 021 021 021 021 021 021 021 021 021 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾The heat generated by the operation of the semiconductor wafer u of the wafer S1211 is transmitted to the ground plane 171 through the wafer holder 121, so as to effectively solve the problem of poor heat dissipation of the 4*'-line wood-type semiconductor package. Related (4) Semiconductor Sealing Parts Techniques can be found in U.S. Patents ' 6' 143, 981, 6, 198, 171, 6, 208, 020, 6, 400, 004, 6, 433, 277, 6, 583, 499, 6, 642, 609, 6, 661, 083, 6, 696, 749, ❹ = 967, 125, 6'979'866 and 7,030, 474; and the dimensional design of the QFN semiconductor package is in accordance with international regulations (JEDEC M0-220).
然而，請配合參閱第“圖，係為對應該第1A圖之底 部透視圖，前述QFN半導體封裝件仍存在著些許問題，主 要係因為習知_半導體封裝件lif過表面黏著技術接置 於電路板後，由於QFN半導體封裝件丨與電路板17間之 間隙h極小，亦即該銲錫接合之直立高度（stand_〇ff)極 罾為細小（約為25〜78微米）’同時因該QFN半導體封裝件與 電路板之熱脹係數（CTE)相差亦大，造成該QFN半導體封 裝件與電路板之間的銲錫接合承受大極大之熱應力（剪應 力）尤其是位於该QFN半導體封裝件角端外露出封裝膠 體之導腳（電性終端）處之銲錫接合，其所受之熱應力最 大，此熱應力關係於（α 2-a ，其中α 2為QFN 半導體封裝件熱脹係數’ 為電路板之熱脹係數，δτ 為QFN半導體封裝件與電路板之間的最大溫度差虬為 Π1021 6 201011881 2等體封裝件巾心至最遠處料接合（ 處之銲錫接合)的距離，"銲錫接直立高度因:：:: 易造成距離㈣I導體封裝件中心 發峰裂招pq BS 月^鮮鍚接合However, please refer to the "Figure, which is the bottom perspective view corresponding to Figure 1A. The QFN semiconductor package still has some problems, mainly because the conventional semiconductor package lif over-surface adhesion technology is placed in the circuit. After the board, the gap h between the QFN semiconductor package and the circuit board 17 is extremely small, that is, the stand-up height (stand_〇ff) of the solder joint is extremely small (about 25 to 78 μm), and because of the QFN. The difference between the thermal expansion coefficient (CTE) of the semiconductor package and the circuit board is also large, causing the solder joint between the QFN semiconductor package and the circuit board to undergo a large thermal stress (shear stress), especially at the corner of the QFN semiconductor package. The solder joint at the outer side of the lead of the encapsulant (electric terminal) is exposed to the maximum thermal stress, which is related to (α 2-a , where α 2 is the thermal expansion coefficient of the QFN semiconductor package The thermal expansion coefficient of the board, δτ is the maximum temperature difference between the QFN semiconductor package and the board. Π1021 6 201011881 2 The package of the package is the farthest material joint (the solder joint) From, " :::: solder bonding due to the height of the upright ㈣I easily lead conductor from the package center peak hair crack fresh move pq BS months ^ Sik engagement
Jest)之要求，嚴重影響產品信賴性。 因此’如何提供一種可右 封裝件及綠㈣，實為mm之半導體 【發明内容】“目—待思考之課題。 e 有鑑於上述習知技術之缺點，本發明之—目 -種半導體封裝件及其導㈣，可有效 封= 之銲接信賴性。 卞等餒封裝件 结怒本，明之又—目的係提供·'種半導體封裝件及a導 传以在_半導體封裝件之鮮錫接合直立高度^足 月況下，降低銲錫接合發生裂損問題。 ❹ 本發明之另—目的係提供—種半導體 線架，以強化_半導體封裝件掉落試驗之能力及其導 本發明之再:目_提供—料導體㈣件及其導 力:T強化半導體封裝件角端處銲錫接合抗裂損之能 括述目的’本發明揭露一種半導體封袭件，係包 之複數V·::導線架具有一晶片座及設於該晶片座周圍 、、中該導線架角端之導腳結構平面尺寸大於 它導腳平面尺寸；半導體日日日片，係接置於該日日日片座上、； 吁線’電性連接該半導體晶片及該導腳；以及封農膠體， 111021 7 201011881 、半導體晶片及部分導線架，並 座底面及導腳底面外露出該封I膠體。 "阳片 該半導體封裝件為一 qFn半 、 端至少二相鄰之導腳係透過-連接部相連一起D亥導線架角 封裝件可選擇於其任一角端起’5玄半導體 母角為、每邊至少一备 ^、或-對角之角端處使至少二相 另外為避Μ对料行+㈣封料之、t連切接 剎時’因複數導腳相連而加大導腳之寬戶造一刀 ❹過度損耗，該用以連接*線_ 、'彳刀刀具的 加/ 、 丧H条角端至少二相鄰導腳之連接 。糸可選擇退縮至封裝邊界内而未位於沖切路徑上。 本發明復揭露—種導線架係包括：—晶片座以及設 於忒晶片座周圍之複數導腳，其中該 構平面尺寸大於其它導腳平面尺寸。…、 腳結 該導線架角端至少二相鄰之導腳係透過—連接部相 ’該導線架可選擇於其任一角端、每一角端、至少 *而、《—對角之角端處使至少二相鄰之導腳相互連 。另t為避免半導體封裝件製程中，於進行半導體封裝 件之切單時’因複數導腳相連而加大導腳之寬度造成沖切 刀具的過度損耗’該用以連接導線架角端至少二相鄰導腳 之連接部係可選擇未位於沖切路徑上。 首财相較於習知Q F N半導體封裝件及導線架，本發明之半 導體封裝件及其導線架係使導線架之角端至少二相鄰之 T腳連接一起，以形成一面積較習知QFN半導體封裝件角 埏大至少二倍之電性終端，進而提供較大之銲錫接合面 Π1021 8 201011881 積，以柢抗熱應力作用，避免銲錫接合發生裂損問題 升半導體封裝件之信賴性，及強化半導體封裝件掉落試驗 之能力。 * 【實施方式】 以下係藉由特定的具體實施例說明本發明之實施方 式，热悉此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點與功效。 第一實施例： Ο 請參閱第2A及2B圖，係為本發明之半導體封裝件平 面及剖面示意圖。 、 本發明所揭露之半導體封裝件2包括有：一導線架 22、至少一半導體晶片21、複數銲線23、以及一封裝膠 體25 。 、夕 該半導體封裝件2為一 QFN半導體封裝件，該導線架 22包括有.一晶片座221以及設於該晶片座周圍之 複數導腳222，其中該導線架22角端之導腳結構平面尺 寸大於其匕導腳平面尺寸，例如該導線架角端至少二 相鄰之導腳222係可透過一連接部222〇相連一起，以於 '•亥導線架22角端形成大尺寸之導腳結構。 如第2A圖所示’該導線架22可選擇於一對角之角端 處使至少二相鄰之導腳222相互連接。 該半導體晶片21具有相對之主動面及非主動面，並 使°亥半導體晶片21以其非主動面間隔-導熱黏著層（未 圖示）而接置於該晶片座221上。 111021 9 201011881 體曰ΓΓΛ打線作業，以利用銲線23電性連接該半導 肢日日片21主動面及導腳222。 守 -半導it二行7·乍業’以形成包覆該銲線㈡、 .曰y曰 及部分導線架22之封裝勝體25，且使該 日日片座221底面外露出該封裳 " 底面外露出該封裝卿25以心5以及使料腳222 接d構成用以與外部裝置電性連 222外^^terminai)°而後進行沖切作業，使該導腳 ❹ 裝件。、 封裝朦體25,以形成本發明之半導體封 如此’後續將本發明之丰莫 之導腳底面(電性裝件外露出封裝膠艘 而電性連接至例如電路板之外Λ|5=著技術間隔薛錫材料 至少二相鄰之導置;^由^架角端 ::終:免合二== 之Θ生1^貝問續而影響半導體封裝件 ❹第二例化半導體封裝件掉落試驗之能力。 二實係為本發明之半導體封裝件第 架除ίΓ=:-，纽相同，主要差異在於導線 二除^ 2Α圖所不在一對角之角端處使至少二相鄰之 :::接外：亦可選擇於每一角端(如第_ 邊至少一角端(如第3β圖所示)處使至少二相鄰之i 腳322透過一連接部3220而相互連接。 導 Π1021 10 201011881 當然’亦可選擇於任-角端使至少二相鄰之 連接。 第三實施例： 請參閱第^及4B圖，係顯示本發明之半導體封裝件 及其導線架第三實施例之示意圖，其中第4A圖為導線架 之底面不意圖，帛4B圖係為半導體封裝件之底面示意圖。 本實施例與前述實施例大致相同，主 rr堅作業後，進行半導體封裝件之沖切時 線力木角端複數導腳相互連接而加大導腳之寬度造成沖 切刀具的過度知耗，本實施例係使沖切路徑（或封裝邊界 L)外側之導腳寛度及間距與習知導線架結構相同，惟使沖 =路徑（或封裝邊界L)内侧之導、㈣42角❹少 ==透過連接部㈣而連接，以加大導線架角端 之導腳、、Ό構面積（電性終端面積）。 及、、中後續於該導線架上完成置晶、打線、封裝模壓 ❹用表Μ」㈣成半導體封裝件，並將該半導體封裝件利 2黏者技術接置於電路板上時，得以利用增加角端電 裂損問題，同時亦可避免二避免接發生 择ο:* 具直接沖切至導腳加大面 積之處而故成沖切刀具過度損耗的問題。 ^此’本發明之半導體難件及其導線㈣使導線苹 之角鳊至少二相鄰之導腳連接一 ’、 ㈣半導體封裝件角端大至:二心 較大之銲錫接合面積，以抵抗 fn進而提供 、 _柷*，、、览力作用，避免銲錫接合 】】 11]〇2] 0 201011881 發生裂損問題，提升半導體封裳件之信賴#，及強化半導 體封裝件掉落試驗之能力。 ,▲上述貫施例僅為例示性說明本發明之原理及其功 •效，二非用於限制本發明。任何熟習此項技藝之人士均可 f不延背本發明之精神及範，下，對上述實施例進行修倚 專^图因此，本發明之權利保護範圍，應如後述之申請 寻利乾圍所列。 【圖式簡單說明】 ❹示意圖係為習知㈣彻封裝件剖面及平面 其導線架 二實施例 扣第2Α及2β圓係為本發明之半導體封裝件及 第一實施例之示意圖； 一第3Α及3Β圖係為本發明之半導體封裝 之示意圖；以及 卞弟The requirements of Jest) seriously affect product reliability. Therefore, 'how to provide a right-hand package and green (four), which is a semiconductor of mm [invention]] "the subject to be considered. e In view of the above-mentioned shortcomings of the prior art, the present invention - the semiconductor package And its guide (4), can effectively seal the solder reliability. 卞 卞 馁 馁 馁 结 , , , , , , 馁 — — — 目的 目的 目的 目的 目的 目的 目的 目的 目的 ' ' ' ' ' ' ' ' ' ' ' ' ' 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体Under the condition of full height, the problem of cracking of solder joint is reduced. ❹ Another object of the present invention is to provide a semiconductor wire frame to enhance the ability of the semiconductor package to drop test and to guide the invention: _ providing material conductor (four) and its guiding force: T-strengthened semiconductor package at the corner end of the solder joint crack resistance can be included in the purpose of the present invention discloses a semiconductor encapsulation, the package of the plural V ·:: lead frame Having a wafer holder and a periphery of the lead frame disposed at the corner end of the lead frame, the plane size of the lead structure is larger than the plane size of the lead leg; the semiconductor day and day film is attached to the day and day seat, ; call line 'electricity Connecting the semiconductor wafer and the lead pin; and sealing the agricultural body, 111021 7 201011881, the semiconductor chip and a part of the lead frame, and the bottom surface of the seat and the bottom surface of the lead leg are exposed to the outer surface of the sealing body I. "positive piece of the semiconductor package is a qFn The at least two adjacent lead pins are connected through the connecting portion. The D-Hail lead frame angle package may be selected from any corner end thereof, and the '5-semiconductor female corner is at least one for each side, or - pair At the corner end of the corner, at least two phases are additionally used to avoid the material row + (four) sealing material, and the t-connection cutting moment is caused by the connection of the plurality of guiding legs and increasing the width of the guiding foot to cause excessive wear and tear. Connect the * line _, 'the knives of the boring tool, and the connection of at least two adjacent guide legs at the end of the H. The 糸 can be retracted into the package boundary without being located on the punching path. The lead frame comprises: a wafer holder and a plurality of guide pins disposed around the crucible wafer holder, wherein the plane of the plane is larger than the plane dimensions of the other guide legs. ..., the foot knots are at least two adjacent guide legs of the lead frame. Connection section 'The lead frame can be selected from its One corner end, each corner end, at least * and "- at the corner end of the diagonal, at least two adjacent lead legs are connected to each other. Another t is to avoid the semiconductor package when the semiconductor package is cut. Due to the connection of the plurality of lead pins, the width of the lead pins is increased to cause excessive loss of the punching cutter. The connecting portion for connecting at least two adjacent guide legs of the lead frame of the lead frame may be selected not to be located on the punching path. Compared with the conventional QFN semiconductor package and the lead frame, the semiconductor package of the present invention and the lead frame thereof are connected to at least two adjacent T legs of the lead end of the lead frame to form an area similar to the conventional QFN semiconductor package. The electrical terminal is at least twice as large as the corner, and thus provides a larger solder joint surface Π 1021 8 201011881 product, which is resistant to thermal stress, avoids the problem of cracking of the solder joint, increases the reliability of the semiconductor package, and strengthens the semiconductor package. The ability to drop the test. * EMBODIMENT The following describes the embodiments of the present invention by way of specific embodiments, and those skilled in the art can readily understand other advantages and advantages of the present invention from the disclosure of the present disclosure. First Embodiment: Ο Refer to Figures 2A and 2B for a plan view and a cross-sectional view of a semiconductor package of the present invention. The semiconductor package 2 disclosed in the present invention comprises: a lead frame 22, at least one semiconductor wafer 21, a plurality of bonding wires 23, and an encapsulant 25. The semiconductor package 2 is a QFN semiconductor package, and the lead frame 22 includes a wafer holder 221 and a plurality of lead pins 222 disposed around the wafer holder, wherein the lead frame structure plane of the corner end of the lead frame 22 The size of the guide pin is greater than the size of the guide pin. For example, at least two adjacent guide pins 222 of the lead frame can be connected together through a connecting portion 222 to form a large-sized guide pin at the corner end of the 'Hai lead frame 22 structure. As shown in Fig. 2A, the lead frame 22 can be selected to connect at least two adjacent lead pins 222 to each other at the corner ends of the pair of corners. The semiconductor wafer 21 has opposing active and inactive surfaces, and the semiconductor wafer 21 is placed on the wafer holder 221 with its inactive surface spacer-thermally conductive adhesive layer (not shown). 111021 9 201011881 The body is threaded to electrically connect the semi-limb day 21 active surface and the lead 222 with the wire 23. Shou-semi-conducting the second line 7·乍业' to form the packaged body 25 covering the bonding wire (2), .曰y曰 and part of the lead frame 22, and exposing the cover to the outside of the day piece 221 " The outer surface of the package is exposed to the core 5 and the foot 222 is connected to the d to form an external connection with the external device 222, and then the punching operation is performed to make the guide pin. The package body 25 is packaged to form the semiconductor package of the present invention. Thus, the bottom surface of the lead of the present invention is subsequently formed (the electrical package is exposed outside the package rubber and electrically connected to, for example, a circuit board)|5= The technical interval of the Xuexi material is at least two adjacent guides; ^ by the ^ corner end:: the end: the free of the two == the twin 1 ^ shell continues to affect the semiconductor package ❹ the second instantiation of the semiconductor package The ability to drop the test. The second is the semiconductor package of the invention. The frame is the same as ΓΓ=:-, and the new difference is that the wire is divided into two. The figure is not at the corner end of the pair of corners to make at least two adjacent The ::: outside: can also be selected at each corner end (such as at least one corner end of the _ side (as shown in Figure 3β), at least two adjacent i feet 322 are connected to each other through a connecting portion 3220. Π1021 10 201011881 Of course, it is also possible to select at least two adjacent connections at any-corner end. Third Embodiment: Referring to FIGS. 4 and 4B, showing a semiconductor package of the present invention and a lead frame thereof according to a third embodiment Schematic diagram, wherein FIG. 4A is a schematic view of the bottom surface of the lead frame, and the 帛4B diagram is a semiconductor package. The embodiment is substantially the same as the foregoing embodiment. After the main rr is hardened, the punching of the semiconductor package is performed, and the plurality of lead pins are connected to each other to increase the width of the guide pins, thereby causing excessive punching tools. In the present embodiment, the guide leg width and spacing on the outer side of the punching path (or the package boundary L) are the same as those of the conventional lead frame structure, but the inner side of the punch=path (or package boundary L), (four) 42 angle ❹少==Connected through the connection part (4) to increase the lead of the corner end of the lead frame, the Ό structure area (electrical termination area), and then complete the crystallization, wire bonding and packaging on the lead frame. When the molded device is used as a semiconductor package and the semiconductor package is placed on the circuit board, the problem of increasing the electrical crack at the corner end can be utilized, and the second option can be avoided. ο:* has the problem of directly punching to the enlarged area of the guide pin and thus causing excessive loss of the punching tool. ^This 'the semiconductor difficult part of the invention and its wire (4) make the corner of the wire 鳊 at least two adjacent Lead pin connected to a ', (four) semiconductor The corner end of the package is as large as: the larger the solder joint area of the two cores, in order to resist fn and provide, _柷*,,, and view the force to avoid solder joints]] 11]〇2] 0 201011881 Cracking problem, improve The reliability of the semiconductor package and the ability to enhance the drop test of the semiconductor package. ▲ The above examples are merely illustrative of the principles and functions of the present invention, and are not intended to limit the present invention. The person skilled in the art can recite the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as listed in the application for the following. [Simplified description of the drawings] The schematic diagram is a conventional (four) complete package profile and plane, the lead frame of the second embodiment, the second and second β-rings are the semiconductor package of the present invention and the first embodiment; 3Α and 3Β图 are schematic diagrams of the semiconductor package of the present invention;
第4A及4B圖係為本發明之半導體封 第二實施例之示意圖。 及其導線架 【主要元件符號說明】 1 QFN半導體封裝件 11 半導體晶片 12 導線架 121 晶片座 122 導腳 15 封裝膠體 16 銲錫材料 111021 12 ㈣觀電路板 170 銲墊 171 接地面 2 半導體封裝件 • 21 半導體晶片 22 導線架 221 晶片座 222 導腳 A 2220 G 連接部 23 銲線 25 封裝膠體 322 導腳 3220 連接部 42 導線架 422 導腳 4220 連接部 G L 封裝邊界 13 1110214A and 4B are schematic views of a second embodiment of the semiconductor package of the present invention. And its lead frame [Main component symbol description] 1 QFN semiconductor package 11 semiconductor wafer 12 lead frame 121 wafer holder 122 lead pin 15 package colloid 16 solder material 111021 12 (four) view circuit board 170 pad 171 ground plane 2 semiconductor package • 21 Semiconductor wafer 22 Lead frame 221 Wafer holder 222 Lead A 2220 G Connection 23 Bond wire 25 Encapsulant 322 Lead 3220 Connection 42 Lead frame 422 Lead 4220 Connection GL Package boundary 13 111021