CN214848611U - Lead frame pin and lead frame - Google Patents

Lead frame pin and lead frame Download PDF

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Publication number
CN214848611U
CN214848611U CN202022277292.7U CN202022277292U CN214848611U CN 214848611 U CN214848611 U CN 214848611U CN 202022277292 U CN202022277292 U CN 202022277292U CN 214848611 U CN214848611 U CN 214848611U
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CN
China
Prior art keywords
lead frame
chip
pin
accommodating
plane
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Active
Application number
CN202022277292.7U
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Chinese (zh)
Inventor
廖弘昌
陈晓林
田亚南
刘振东
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Riyuexin semiconductor (Weihai) Co.,Ltd.
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Riyueguang Semiconductor Weihai Co ltd
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Priority to CN202022277292.7U priority Critical patent/CN214848611U/en
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Publication of CN214848611U publication Critical patent/CN214848611U/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401Disposition
    • H01L2224/40151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic

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  • Lead Frames For Integrated Circuits (AREA)

Abstract

According to some embodiments of the present disclosure, a lead frame pin is disclosed. The lead frame pins are used for preventing the wire jumper connected to the chip from deviating. The lead frame pin comprises a plane part and an inclined part. The inclined plane parts are arranged on two sides of the plane part. According to some embodiments of the present disclosure, a leadframe is disclosed, comprising: chip holding portion and leg portion. The chip accommodating portion is used for accommodating a semiconductor chip. The pin portion is used for accommodating a jumper wire connected to the semiconductor chip. The pin portion comprises a plane portion and an inclined portion, wherein the inclined portion is arranged on two sides of the plane portion.

Description

Lead frame pin and lead frame
Technical Field
The present invention relates to the field of semiconductor packaging, and more particularly, to a lead frame pin and a lead frame.
Background
In the prior art, when a semiconductor chip is packaged, the chip is first adhered to a chip accommodating portion of a lead frame by solder, then a jumper wire is connected between the chip and a pin by solder, and then the package is sealed and the lead frame is punched. However, during the transfer process, the part of the jumper wire bonded with the pin may rotate, shift or even disengage. In addition, the solder used for bonding the jumper wire and the pin is easy to leak.
SUMMERY OF THE UTILITY MODEL
Accordingly, the present application provides a lead frame and a lead frame to solve the above problems.
According to an embodiment of the present application, a lead frame pin is disclosed. The lead frame is used for preventing a jumper wire connected to the chip from deviating. The lead frame pin comprises a plane part and an inclined part. The inclined plane parts are arranged on two sides of the plane part.
According to an embodiment of the present application, a leadframe is disclosed, including: chip holding portion and leg portion. The chip accommodating portion is used for accommodating a semiconductor chip. The pin portion is used for accommodating a jumper wire connected to the semiconductor chip. The pin portion comprises a plane portion and an inclined portion, wherein the inclined portion is arranged on two sides of the plane portion.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application and not to limit the application. In the drawings:
fig. 1 illustrates a perspective view of a lead frame according to an embodiment of the present application.
FIG. 2 illustrates a front view of a tube foot according to an embodiment of the present application.
Fig. 3 illustrates a perspective view of a lead frame according to an embodiment of the present application.
Fig. 4A to 4D illustrate the steps of a chip packaging operation according to an embodiment of the present application.
Detailed Description
The following disclosure provides various embodiments or illustrations that can be used to implement various features of the disclosure. The embodiments of components and arrangements described below serve to simplify the present disclosure. It is to be understood that such descriptions are merely illustrative and are not intended to limit the present disclosure. For example, in the description that follows, forming a first feature on or over a second feature may include certain embodiments in which the first and second features are in direct contact with each other; and may also include embodiments in which additional elements are formed between the first and second features described above, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or characters in the various embodiments. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Moreover, spatially relative terms, such as "under," "below," "over," "above," and the like, may be used herein to facilitate describing a relationship between one element or feature relative to another element or feature as illustrated in the figures. These spatially relative terms are intended to encompass a variety of different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
Although numerical ranges and parameters setting forth the broad scope of the application are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain standard deviations found in their respective testing measurements. As used herein, "about" generally refers to actual values within plus or minus 10%, 5%, 1%, or 0.5% of a particular value or range. Alternatively, the term "about" means that the actual value falls within the acceptable standard error of the mean, subject to consideration by those of ordinary skill in the art to which this application pertains. It is understood that all ranges, amounts, values and percentages used herein (e.g., to describe amounts of materials, length of time, temperature, operating conditions, quantitative ratios, and the like) are modified by the term "about" in addition to the experimental examples or unless otherwise expressly stated. Accordingly, unless indicated to the contrary, the numerical parameters set forth in the specification and attached claims are approximations that may vary depending upon the desired properties sought to be obtained. At the very least, these numerical parameters are to be understood as meaning the number of significant digits recited and the number resulting from applying ordinary carry notation. Herein, numerical ranges are expressed from one end to the other or between the two ends; unless otherwise indicated, all numerical ranges set forth herein are inclusive of the endpoints.
Fig. 1 illustrates a perspective view of a lead frame 100 according to an embodiment of the present application. The lead frame 100 includes a chip accommodating portion 100A and a lead portion 100B. In some embodiments, the chip-accommodating portion 100A is a planar structure for accommodating a semiconductor chip. In some embodiments, the chip-holding portion 100A may be a groove structure for holding a semiconductor chip. The structure of the chip-accommodating portion 100A is not limited in the present application and may be adjusted according to actual design requirements. In some embodiments, the chip-receiving portion 100A includes a conductor. In some embodiments, the chip-receiving portion 100A comprises copper. The chip-holding portion 100A can be used as a heat sink, and when the semiconductor chip is placed on the chip-holding portion 100A and packaged in a package, the good thermal conductivity of the chip-holding portion 100A can help the semiconductor chip dissipate heat.
The leg portion 100B includes a flat surface portion 110 and an inclined surface portion 120. In some embodiments, the planar portion 110 is coplanar with the chip-receiving portion 100A. In some embodiments, the planar portion 110 and the chip-receiving portion 100A are different in position in the height direction. The inclined surfaces 121 and 122 of the inclined surface portion 120 are respectively disposed on both sides of the planar portion 110. In certain embodiments, the pin portion 100B comprises a conductor. In some embodiments, the pin portion 100B comprises copper. In some embodiments, the chip receiving portion 100A and the pin portion 100B are not in direct contact. In some embodiments, the chip-receiving portion 100A and the tube portion 100B are integrally stamped and designed.
Fig. 2 illustrates a front view of a foot portion 100B according to an embodiment of the present application. In some embodiments, the included angle θ 1 between the inclined surface 121 and the plane portion 110 is the same as the included angle θ 2 between the inclined surface 122 and the plane portion 110. In some embodiments, the included angle θ 1 is in a range of about 90 ° to about 170 ° with respect to the included angle θ 2. In other embodiments, the included angle θ 1 and the included angle θ 2 may be different. In certain embodiments, the thickness 121w of the bevel 121 is the same as the thickness 122w of the bevel 122. In some embodiments, the thickness 121w and the thickness 122w are approximately 30% to 50% of the planar portion thickness 110 w. In other embodiments, the thickness 121w and the thickness 122w may be different. In some embodiments, the inclined surface 121 and the inclined surface 122 are symmetrically disposed with respect to the planar portion 110. In other embodiments, the positions of the inclined surface 121 and the inclined surface 122 on the planar portion 110 may be different.
Fig. 3 illustrates a perspective view of a lead frame 200 according to an embodiment of the present application. The leadframe 200 shown in fig. 3 is substantially the same as the leadframe 100 shown in fig. 1, except that the leadframe 200 further includes an outer frame 100C. The outer frame 100C surrounds the chip accommodating portion 100A and the pin portion 100B. The chip accommodating portion 100A is connected to the outer frame portion 100C via the first support portion 21. The leg portion 100B is connected to the outer frame portion 100C via the second support portion 22. The lead frame 200 connects the chip accommodating portion 100A and the lead frame portion 100B through the outer frame portion 100C, so that the semiconductor chip packaging operation is more convenient. In certain embodiments, the outer frame portion 100C is a rectangular structure. However, the present application does not limit the structural shape of the outer frame portion 100C.
In the example of fig. 3, the positions of the first supporting portion 21 and the second supporting portion 22 are only exemplary. Those skilled in the art should understand that the first supporting portion 21 and the second supporting portion 22 are only used for connecting the chip accommodating portion 100A and the pin portion 100B to the outer frame portion 100C, and the positions, the number and the sizes of the first supporting portion 21 and the second supporting portion 22 can be adjusted according to actual design requirements.
In some embodiments, the outer frame portion 100C may surround a plurality of sets of the chip accommodating portions 100A and the pin portions 100B, and the plurality of sets of the first supporting portions 21 and the second supporting portions 22 connect the chip accommodating portions 100A and the pin portions 100B to the outer frame portion 100C, so as to perform a plurality of sets of semiconductor chip packaging operations simultaneously.
Fig. 4A to 4D illustrate steps 41 to 44 of a chip packaging operation according to an embodiment of the present application. If substantially the same result is obtained, the present application is not limited to performing the steps completely in accordance with the flow of steps shown in FIGS. 4A-4D. In the example of fig. 4A to 4D, a lead frame 100 is illustrated as an example. The chip packaging operation comprises the following steps:
at step 41, semiconductor die 51 is placed on leadframe 100. In detail, the semiconductor chip 51 can be adhered to the chip-holding portion 100A by the solder 52. In the present embodiment, the solder 52 may be a mixture of tin, silver, etc. to help the heat of the semiconductor chip 51 to be conducted to the chip accommodating portion 100A.
Step 42, connecting the semiconductor chip 51 to the pin part 100B. As shown in fig. 4B, the semiconductor chip 51 is connected to the pin portion 100B by the jumper wire 53. In detail, the jumper wire 53 includes a conductor for transferring a signal between the semiconductor chip 51 and the pin portion 100B. In the present embodiment, the jumper wire 53 is adhered to the semiconductor chip 51 by the solder 54, and is adhered to the pin portion 100B by the solder 55. In the present embodiment, the solders 54 and 55 may be a mixture of tin, silver, or the like.
With the lead frame 100 (or the lead frame 200) and the lead frame base 100B, when the jumper wire 53 is adhered to the lead frame base 100B, the inclined surface 120 forms a baffle, so that the part where the jumper wire 53 is adhered to the lead frame base 100B can be effectively prevented from rotating, deviating and even separating. Meanwhile, the inclined surface portion 120 also effectively prevents the solder 55 from leaking out from the side surface.
At step 43, package 56 is attached to leadframe 100 to encapsulate semiconductor chip 51. In the embodiment of fig. 4C, the encapsulant 56 may include phenolic-based resin (Novolac-based resin), epoxy-based resin (epoxy-based resin), silicone-based resin (silicone-based resin), or other suitable encapsulant. In other embodiments, the package 56 may also include a suitable filler, such as powdered silicon dioxide. In addition, the package 56 may package the semiconductor chip 51 by different techniques, such as compression molding (compression molding), injection molding (injection molding), transfer molding (transfer molding), and the like, which are not limited in this application.
In step 44, a die cutting operation is performed to cut the lead portions 100B to obtain semiconductor package chips 57.
Note that, when the lead frame 200 is taken as an example to perform the above-described die-sealing operation, the difference is that the first supporting portion 21 and the second supporting portion 22 are cut to separate the chip accommodating portion 100A and the pin portion 100B from the outer frame portion 100C to obtain the semiconductor package chip 57.

Claims (10)

1. A lead frame pin for preventing a wire jumper connected to a chip and the lead frame pin from shifting, the lead frame pin comprising:
plane portion and inclined plane portion, wherein the upper surface of plane portion be used for with the wire jumper is connected, inclined plane portion set up in the both sides of upper surface, and follow the upper surface is to the wire jumper direction extends.
2. The lead frame pin according to claim 1, wherein the thickness of the inclined portion is 30 to 50% of the thickness of the planar portion.
3. The lead frame pin according to claim 1, wherein an angle between the inclined surface portion and the planar portion is in a range of 90 ° to 170 °.
4. The lead frame pin according to claim 1, wherein the lead frame pin includes a conductor.
5. The lead frame pin according to claim 4, wherein the lead frame pin comprises copper.
6. A leadframe, comprising:
a chip accommodating portion for accommodating a semiconductor chip; and
a pin portion for accommodating a jumper wire connected to the semiconductor chip, comprising:
plane portion and inclined plane portion, wherein the upper surface of plane portion be used for with the wire jumper is connected, inclined plane portion set up in the both sides of upper surface, and follow the upper surface is to the wire jumper direction extends.
7. The lead frame of claim 6, further comprising:
and the outer frame part surrounds the chip accommodating part and the pin part, wherein the chip accommodating part is connected with the outer frame part through a first supporting part, and the pin part is connected with the outer frame part through a second supporting part.
8. The lead frame according to claim 6, wherein the thickness of the inclined portion is 30 to 50% of the thickness of the planar portion.
9. The lead frame according to claim 6, wherein an angle between the inclined surface portion and the planar portion is in a range of 90 ° to 170 °.
10. The lead frame of claim 6, wherein the chip receiving portion is not in direct contact with the lead portion.
CN202022277292.7U 2020-10-14 2020-10-14 Lead frame pin and lead frame Active CN214848611U (en)

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Application Number Priority Date Filing Date Title
CN202022277292.7U CN214848611U (en) 2020-10-14 2020-10-14 Lead frame pin and lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202022277292.7U CN214848611U (en) 2020-10-14 2020-10-14 Lead frame pin and lead frame

Publications (1)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115295510A (en) * 2022-09-06 2022-11-04 日月新半导体(威海)有限公司 Semiconductor discrete device package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115295510A (en) * 2022-09-06 2022-11-04 日月新半导体(威海)有限公司 Semiconductor discrete device package

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GR01 Patent grant
GR01 Patent grant
CP03 Change of name, title or address

Address after: 264205 No. 16-1, Hainan Road, North District, comprehensive bonded zone, Weihai Economic and Technological Development Zone, Shandong Province

Patentee after: Riyuexin semiconductor (Weihai) Co.,Ltd.

Address before: No.16-1, Hainan Road, export processing zone, Weihai Economic Development Zone, Weihai City, Shandong Province 264205

Patentee before: RIYUEGUANG SEMICONDUCTOR(WEIHAI) Co.,Ltd.

CP03 Change of name, title or address