201011783 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種晶片電阻器及其製造方法= 係關於一種具有正面輔助電極之晶 晶片電阻器及其製造方 法》 【先前技術】 參考圖！，顯示習知晶片電阻器之剖視示意圖。該晶片 Φ 電阻器i是-種銲黏在-積層電路板上的被動元件，用於 &供電阻值。該晶片電阻^包括—基材u、二正面電極 12、二背面電極13、一電阻層14、一第—保護層15、一第 二保護層16、二側面電極17、二第一鍍層18及二第二鍍層 19 〇 該基材11是以絕緣材料構成，大致上係為矩形板狀並具 有一背面111、二側面112及一正面113。該等側面112係分 別自該背面111的相對兩側向上延伸。該正面丨13係相對應 φ 該背面1U。該等正面電極12是可導電並相間隔地位於該 基材11之正面113上。每一正面電極12具有一内側面121、 一外侧面122及一内端部123。該正面電極丨2之外侧面122 係與該基材11之侧面112切齊。 該等背面電極13是可導電並相間隔地位於該基材n之背 面111上。每一背面電極13具有一内側面131及一外側面 132。該背面電極13之外側面132係與該基材11之側面112 切齊’使得該等正面電極12及該等背面電極13彼此相對 稱。 134268.doc 201011783 該電阻層14具有預定的電阻值，其設置在該基材11之正 面113 ’且位於該等正面電極12之内側面121之間的區域 内。該電阻層14係延伸至該等正面電極12上方，使得該電 阻層14之二端部係疊接（〇verlap)於該正面電極12之端部 123。該第一保護層15是以可切割的絕緣材料構成，其係 覆蓋該電阻層14使該電阻層14與外界相隔絕。該第二保護 層16是以絕緣材料構成，其係覆蓋該第一保護層15及部分 該等正面電極12,使該電阻層14及該第一保護層15與外界 相隔絕。 該等側面電極17以可導電的材料構成。每一側面電極17 係形成在該基材11之側面112、該正面電極丨2之外側面122 及該背面電極13之外側面132上，用以電性連接該正面電 極12及該背面電極13 ^該等第一鍍層18係為鎳層，每一第 一鍍層18係覆盍該正面電極12、該背面電極13及該側面電 極17。該等第二鑛層19係為錫層，每一第二鍍層丨9係覆蓋 該第一鍍層18。 該習知晶片電阻器1之缺點如下。當在高硫氣及高腐蝕 性氣體的環境中，具有腐蝕性的氣體會容易經由該第二保 護層16與該第一鍍層18及該第二鍍層19之界面滲透進入該 晶片電阻器1中，而與該正面電極12中的銀起化學反應而 產生硫化銀，進而改變電阻值；嚴重者，會形成開路而使 該晶月電阻器1所在之系統失效。 因此，有必要提供-種創新且具進步性的晶片電阻器及 其製造方法，以解決上述問題。 134268.doc 201011783 【發明内容】 本發明係提供一種晶片電阻器’其包括一基材、二背面 電極、一電阻層、二正面電極、二正面辅助電極、一第一 保護層、一第二保護層、二側面電極及至少一鍍層。該基 材具有一背面、二側面及一正面。該等背面電極係相間隔 地位於該基材之背面上’每一背面電極具有一内側面及一 外側面。該電阻層係位於在該基材之正面，該電阻層具有 _ 二端部。該等正面電極係相間隔地位於該基材之正面上， 每一正面電極具有一内端部、一内側面及一外側面，且該 正面電極之内端部係疊接於該電阻層之端部。 該等正面輔助電極係相間隔地位於該等正面電極上，每 一正面辅助電極係覆蓋每一正面電極。該第一保護層覆蓋 該電阻層。該第二保護層覆蓋該第一保護層及部分該正面 辅助電極。每一側面電極係位於該基材之側面、該正面電 極之外側面及該背面電極之外側面上，用以電性連接該正 • 面電極及該背面電極。該至少一鍍層覆蓋該等正面輔助電 極、該等背面電極及該等侧面電極。 本發明另提供一種晶片電阻器之製造方法，包括以下步 驟.（a)提供一基材’該基材具有一背面、二側面及一正 面；（b)形成二個背面電極於該基材之背面，該等背面電極 係相間隔，且每一背面電極具有一内側面及一外側面； 形成一電阻層於該基材之正面之中間區域；（d)形成二個正 面電極於該基板之正面，該等正面電極係相間隔，每一正 面電極具有一内端部、一内側面及一外側面，且該正面電 134268.doc -8 - 201011783 極之内端邛係疊接於該電阻層之端部；（e)形成二個正面辅 助電極於該等正面電極上，且每一正面輔助電極係覆蓋每 一正面電極，（f)形成一第一保護層於該電阻層上；形 成一第一保護層於該第一保護層上；（h)形成二個側面電 極，每一側面電極係形成在該基材之側面、該正面電極之 外側面及該背面電極之外側面上，用以電性連接該正面電 極及該背面電極；及⑴形成至少一鍍層以覆蓋該等正面電[Technical Field] The present invention relates to a wafer resistor and a method of manufacturing the same, and to a wafer resistor having a front auxiliary electrode and a method of manufacturing the same. [Prior Art] Reference FIG. A schematic cross-sectional view showing a conventional chip resistor. The wafer Φ resistor i is a passive component soldered to a laminated circuit board for & resistance values. The chip resistor includes a substrate u, two front electrodes 12, two back electrodes 13, a resistive layer 14, a first protective layer 15, a second protective layer 16, two side electrodes 17, and two first plating layers 18 and The second plating layer 19 is made of an insulating material and is substantially rectangular plate-shaped and has a back surface 111, two side surfaces 112 and a front surface 113. The sides 112 extend upwardly from opposite sides of the back side 111, respectively. The front side 13 corresponds to φ the back side 1U. The front electrodes 12 are electrically conductive and spaced apart on the front side 113 of the substrate 11. Each front electrode 12 has an inner side 121, an outer side 122 and an inner end 123. The outer surface 122 of the front electrode 丨2 is aligned with the side surface 112 of the substrate 11. The back electrodes 13 are electrically conductive and spaced apart on the back side 111 of the substrate n. Each of the back electrodes 13 has an inner side surface 131 and an outer side surface 132. The outer side surface 132 of the back surface electrode 13 is aligned with the side surface 112 of the substrate 11 such that the front surface electrodes 12 and the back surface electrodes 13 are symmetrical to each other. 134268.doc 201011783 The resistive layer 14 has a predetermined resistance value disposed in the area between the front side 113' of the substrate 11 and the inner side 121 of the front side electrodes 12. The resistive layer 14 extends over the front side electrodes 12 such that the two ends of the resistive layer 14 are overlapped at the end portion 123 of the front side electrode 12. The first protective layer 15 is formed of a cleavable insulating material that covers the resistive layer 14 to isolate the resistive layer 14 from the outside. The second protective layer 16 is made of an insulating material, and covers the first protective layer 15 and a portion of the front electrodes 12 to isolate the resistive layer 14 and the first protective layer 15 from the outside. The side electrodes 17 are made of an electrically conductive material. Each of the side electrodes 17 is formed on the side surface 112 of the substrate 11 , the outer surface 122 of the front surface electrode 2 and the outer side surface 132 of the back surface electrode 13 for electrically connecting the front surface electrode 12 and the back surface electrode 13 . The first plating layer 18 is a nickel layer, and each of the first plating layers 18 covers the front surface electrode 12, the back surface electrode 13, and the side surface electrode 17. The second ore layers 19 are tin layers, and each of the second plating layers 9 covers the first plating layer 18. The disadvantages of the conventional chip resistor 1 are as follows. When in a high sulfur gas and a highly corrosive gas environment, a corrosive gas can easily enter the wafer resistor 1 through the interface between the second protective layer 16 and the first plating layer 18 and the second plating layer 19. The silver reacts with the silver in the front electrode 12 to generate silver sulfide, thereby changing the resistance value; in severe cases, an open circuit is formed to disable the system in which the crystal moon resistor 1 is located. Therefore, it is necessary to provide an innovative and progressive wafer resistor and a method of manufacturing the same to solve the above problems. The present invention provides a wafer resistor comprising a substrate, two back electrodes, a resistive layer, two front electrodes, two front auxiliary electrodes, a first protective layer, and a second protection. a layer, two side electrodes, and at least one plating layer. The substrate has a back side, two side faces and a front side. The back electrodes are spaced apart on the back side of the substrate. Each back electrode has an inner side and an outer side. The resistive layer is located on the front side of the substrate, and the resistive layer has _ two ends. The front electrodes are spaced apart from each other on the front surface of the substrate. Each front electrode has an inner end portion, an inner side surface and an outer side surface, and the inner end portion of the front surface electrode is overlapped with the resistive layer. Ends. The front auxiliary electrodes are spaced apart on the front electrodes, and each of the front auxiliary electrodes covers each of the front electrodes. The first protective layer covers the resistive layer. The second protective layer covers the first protective layer and a portion of the front auxiliary electrode. Each of the side electrodes is located on a side of the substrate, an outer side of the front electrode, and an outer side of the back electrode for electrically connecting the positive electrode and the back electrode. The at least one plating layer covers the front auxiliary electrodes, the back electrodes, and the side electrodes. The invention further provides a method for manufacturing a wafer resistor, comprising the following steps: (a) providing a substrate having a back surface, two side surfaces and a front surface; (b) forming two back electrodes on the substrate a back surface, the back electrodes are spaced apart, and each back electrode has an inner side surface and an outer side surface; a resistive layer is formed in an intermediate portion of the front surface of the substrate; and (d) two front electrodes are formed on the substrate The front side electrodes are spaced apart from each other, and each of the front electrodes has an inner end portion, an inner side surface and an outer side surface, and the front end is electrically connected to the resistor 134268.doc -8 - 201011783 (e) forming two front auxiliary electrodes on the front electrodes, and each front auxiliary electrode covers each front electrode, and (f) forming a first protective layer on the resistive layer; a first protective layer on the first protective layer; (h) two side electrodes are formed, each side electrode is formed on a side of the substrate, an outer side surface of the front electrode, and an outer side surface of the back electrode Used to electrically connect the positive Electrode and the back electrode; ⑴ and forming at least one plating layer such as to cover the surface of the electrically
極、該等背面電極及該等側面電極，以形成一晶片電阻 器。 由於該等正面輔助電極具有抗硫化、抗腐蝕能力，其能 有效地保護該等正面電極，不受硫氣、與其他具有腐钱性 的氣體影響’可改善習知晶片電阻器容易因環境影響而改 變電阻值或甚至造成開路而使系統失效的缺點。此外，本 發明之製程係先形成該電阻層之後再形成該等正面電極， 如此可容許該等正面電極、該等正面辅助電極、該第二保 護層有些許偏移量，而仍然可以確保有效地保護該等正面 電極，不受硫氣、與其他具有腐蝕性的氣體影響。 【實施方式】 請參考圖2,顯示本發明之晶片電阻器之製造方法之流 程示意圖。請參考圖3a至3j’顯示本發明之晶片電阻器之 製造方法之各個製程步驟之立體示意圖。請參考圖^至 4j，顯示對應圖3a至3j之各個製程步驟之剖視示意圖。 步驟S2CH係提供一基材21，該基材幻具有一背面211、 二側面212及一正面213，如圖3&及“所示。 134268.doc -9- 201011783 步驟S202係形成二個背面電極23於該基材以之背面 211。該等背面電極23係相間隔而互不連接，且每一背面 電極23具有一内側面231及一外側面232，如圖儿及仆所 示。在本文中，「内側」係指靠近該基材21之中間區域之 方向，「外側」係指遠離該基材2丨之中間區域之方向。在 本實施例中，該等背面電極23係以印刷方式形成。The electrodes, the back electrodes and the side electrodes are formed to form a wafer resistor. Since the positive auxiliary electrodes have anti-vulcanization and anti-corrosion ability, they can effectively protect the front electrodes from sulfur gas and other corrosive gases, which can improve the environmental impact of conventional chip resistors. The disadvantage of changing the resistance value or even causing an open circuit to disable the system. In addition, the process of the present invention first forms the resistive layer and then forms the front electrodes, which can allow the front electrodes, the front auxiliary electrodes, and the second protective layer to be slightly offset, and still ensure effective These front electrodes are protected from sulfur gas and other corrosive gases. [Embodiment] Referring to Figure 2, there is shown a schematic flow chart of a method of manufacturing a wafer resistor of the present invention. Referring to Figures 3a to 3j', there are shown perspective views of various process steps of the method of fabricating the wafer resistor of the present invention. Referring to Figures 2 to 4j, a schematic cross-sectional view of each process step corresponding to Figures 3a to 3j is shown. Step S2CH provides a substrate 21 having a back surface 211, two side surfaces 212 and a front surface 213, as shown in Figures 3 & and "134268.doc -9-201011783. Step S202 forms two back electrodes. 23 is on the back surface of the substrate 211. The back electrodes 23 are spaced apart from each other, and each back electrode 23 has an inner side 231 and an outer side 232, as shown in the figure. The term "inside" refers to the direction of the intermediate portion of the substrate 21, and the "outer side" refers to the direction away from the intermediate portion of the substrate 2丨. In the present embodiment, the back electrodes 23 are formed by printing.
步驟S203係形成一電阻層24於該基材21之正面213之中 間區域，且該電阻層24具有二端部241，如圖孔及勑所 示在本實施例中，該電阻層24係以印刷方式形成，其材 質例如釕、銅、銀、鈀等導電油墨。 步驟S204係形成二個正面電極22於該基板以之正面 213，該等正面電極22係相間隔而互不連接。每一正面電 極22具有一内端部221、一内側面222及一外側面223。該 正面電極22係延伸至該電阻層24上，使得該正面電極22之 内端部221係疊接於該電阻層24之端部241，如圖^及牝所 示。在本實施例中’該等正面電極22係以印刷方式形成。 步驟S205係形成二個正面辅助電極3〇於該等正面電極22 上，且每一正面辅助電極30係完全覆蓋每一正面電極22之 寬邊’使得該正面輔助電極30會接觸到該基材21之正面 213 ’如圖3e及4e所示。該等正面辅助電極3〇係可以印刷 方式、物理沉積方式或化學沉積方式形成。每一正面輔助 電極30具有一内側面301及一外側面302，較佳地，該正面 輔助電極30之内側面301係不超出該正面電極22之内側面 222 ’該正面辅助電極3〇之外側面3〇1係不超出該正面電極 134268.doc -10· 201011783 22之外側面223。該正面輔助電極3〇之型式可以是薄膜、 塊材或油墨，但不限於上述所列；且其具有可導電可抗 硫化，可抗腐蝕的化學特性。 步驟S206係形成一第一保護層25於該電阻層24上，如圖 3f及4f所示。該第一保護層25是以可切割的絕緣材料構 成。較佳地’該步驟S206之後更包括一以一高能量射束精 確切割該電阻層24以調變其電阻值之步驟。 φ 步驟S207係形成一第二保護層26於該第一保護層25上及 部分該正面輔助電極30，如圖3g及4g所示。 步驟S208係形成二個侧面電極27，每一侧面電極27係形 成在該基材21之側面212、該正面電極22之外側面223及該 背面電極23之外側面232上，用以電性連接該正面電極22 及該背面電極23,如圖3h及4h所示。該等側面電極27係可 以塗覆或真空濺鑛方式形成。 接著，形成至少一鑛層以覆蓋該等正面辅助電極3〇、該 φ 等背面電極23及該等側面電極27，以形成一晶片電阻器 2’在其他應用中’該鑛層更覆蓋該等正面電極22。在本 實施例中該至少一鍍層係包含二層鍍層。步驟S2〇9係形成 一第一鍍層28以覆蓋該正面辅助電極3〇、該背面電極23及 該側面電極27，如圖3i及4i所示。在其他應用中，如果該 正面辅助電極30並未完全覆蓋每一正面電極22之上表面 (即該正面輔助電極3〇之寬度小於該正面電極22之寬 度），而顯露部分該正面電極22，此時該第一鍍層28會更 覆蓋到該顯露之正面電極22。 134268.doc 201011783 步驟S210係形成一第二鍍層29以覆蓋該第一鍍層28，如 圖3j及4j所示。 參考圖3j及4j，分別顯示本發明晶片電阻器之立體圖及 剖視圖。該晶片電阻器2包括一基材21、二背面電極23、 一電阻層24、二正面電極22、二正面辅助電極3〇、一第一 保護層25、一第二保護層26、二側面電極27及至少一鑛 層。 該基材21係為絕緣材質且其外觀為板狀，其具有一背面 211、二側面212及一正面213。該等背面電極23係相間隔 地位於該基材21之背面211上。每一背面電極23具有一内 側面23 1及一外側面232。該背面電極23之外側面232係與 該基材21之側面212切齊。該等背面電極23係為可導電材 質。該電阻層24係位於在該基材21之正面213。該電阻層 24具有一端部241 ’其材質例如釘、銅、銀、把等導電油 墨。 該等正面電極22係相間隔地位於該基材21之正面213 上。每一正面電極22具有一内端部221、一内側面222及一 外侧面223，且該正面電極22之内端部221係疊接於該電阻 層24之端部241上。該正面電極22之外側面223係與該基材 21之侧面212切齊》該等正面電極22係為可導電材質。 該等正面輔助電極30之材質係選自由鈀、鉑、金、石 墨、碳及其組合物所組成之群。該等正面輔助電極3〇係相 間隔地位於該等正面電極22上’每一正面輔助電極30係完 全覆蓋每一正面電極22之寬邊，使得該正面輔助電極3〇會 134268.doc 12- 201011783 接觸到該基材21之正面213 ^該等正面辅助電極30係為可 導電材質。每一正面辅助電極3〇具有一内側面3〇1及一外 側面302，較佳地，該正面辅助電極3〇之内側面3〇 1係不超 出該正面電極22之内侧面222 ’該正面辅助電極3〇之外侧 面301係不超出該正面電極22之外側面223。該正面輔助電 極30之型式可以是薄膜、塊材或油墨，但不限於上述所 列；且其具有可導電，可抗硫化，可抗腐蝕的化學特性。 該第一保護層25係覆蓋該電阻層24，該第一保護層25是 以可切割的絕緣材料構成。該第二保護層26係覆蓋該第一 保護層25及部分該正面辅助電極3〇。 每一側面電極27係位於該基材21之側面212、該正面電 極22之外側面223、該正面輔助電極3〇之外側面302及該背 面電極23之外侧面232上，用以電性連接該正面電極22及 該背面電極23。該等側面電極27係為可導電材質。 該至少一鍍層係覆蓋該等正面辅助電極30、該等背面電 極23及該等側面電極27’在其他應用中，該鍍層更覆蓋該 等正面電極22。在本實施例中，該至少一鍍層包括一第一 鐘層28及一第二鍍層29。該第一鍍層28係為鎳層且覆蓋該 正面辅助電極30、該背面電極23及該侧面電極27。在其他 應用中’如果該正面辅助電極3〇並未完全覆蓋每一正面電 極22之上表面（即該正面辅助電極3〇之寬度小於該正面電 極22之寬度），而顯露部分該正面電極22，該第一鍍層28 會更覆蓋到該顯露之正面電極22。該第二鍍層29係為錫層 且覆蓋該第一鍛層28。 134268.doc •13· 201011783 本發明優點在於增加具有抗硫化、抗腐蝕能力的該等正 面輔助電極30,其能有效地保護該等正面電極22，不受硫 氣、與其他具有腐蝕性的氣體影響，可改善習知晶片電阻 器1容易因環境影響而改變電阻值或甚至造成開路而使系 統失效的缺點。此外，本發明之製程係先形成該電阻層24 之後再形成該等正面電極22,如此可容許該等正面電極 22、該等正面辅助電極3〇、該第二保護層％有些許偏移 φ 量，而仍然可以確保有效地保護該等正面電極22，不受硫 氣、與其他具有腐蝕性的氣體影響。 請參考圖5,顯示本發明之晶片電阻器之批次製造方法 之流程示意圖。請參考圖6至17，顯示本發明之晶片電阻 器之批次製造方法之各個製程步驟之剖視示意圖。 步驟S501係提供一絕緣基板31，該基板31具有一背面 311、一正面313、複數條橫向槽314及複數條縱向槽315。 該等橫向槽314及該等縱向槽315係位於該正面313且彼此 • 交錯而定義出複數個元件單體區316,如圖6及7所示。該 絕緣基板31可以是例如玻璃基板、陶瓷基板’或是以環氧 樹輯為材料所構成的基板’較佳地，該等橫向槽314及該 等縱向槽315的深度設定在數微米之内，而可於後續的製 程中以物理方式破裂取得預定的半成品。 步驟S502係形成複數條背面電極條33於該基板31之背面 311。該等背面電極條33係對應該等縱向槽315，在本實施 例中’該等背面電極條33係位於該等縱向槽315之正下 方，如圖8所示。在本實施例中，該等背面電極條33係以 134268.doc •14· 201011783 印刷方式形成。 步驟S5°^3係形成一電阻層24於每-元件單體區316之正 面之中間區域，且該電阻層24具有二端部⑷，如圖9所 示在本實施例中，該電阻層24係以印刷方式形成，其材 質例如钉、銅、銀、鈀等導電油墨。 步驟S5 04係形成複數條正面電極條32於該基板3 1之正面 313，每正面電極條32係位於二相鄰電阻層24之間且橫 越該縱向槽315。該等正面電極條32係延伸至該電阻層24 上’使得該等正面電極條32之端部係疊接於該等電阻層24 之端部241 ’如圖10所示β在本實施例中，該等正面電極 條32係以印刷方式形成。 步驟S5 05係形成一正面辅助電極條4〇於每一正面電極條 32上’且每一正面輔助電極條4〇係完全覆蓋每一正面電極 條32之寬邊，使得該正面辅助電極條4〇會接觸到該基板31 之正面3 13,如圖11所示。該等正面辅助電極條40係可以 印刷方式、物理沉積方式或化學沉積方式形成。該正面辅 助電極條40之型式可以是薄膜、塊材或油墨，但不限於上 述所列；且其具有可導電，可抗硫化，可抗腐蝕的化學特 性。 步驟S506係形成一第一保護層25於每一電阻層24上，如 圖12所示。該第一保護層25是以可切割的絕緣材料構成。 較佳地，該步驟S506之後更包括一以一高能量射束精確切 割該電阻層24以調變其電阻值之步驟。 步驟S507係形成一第二保護層26於每一第一保護層25上 134268.doc -15- 201011783 及部分該正面輔助電極條40，如圖13所示。 步驟S508係沿著該等縱向槽⑴物理破裂該基板3ΐ，以 • #成複數個條狀半成品41，每—半成品41具有三個破裂面 411，如圖14所示。 步驟S509係形成一側面電極條37於該半成品“之每一破 裂面411，以電性連接該正面電極條“及該背面電極條 33。該等侧面電極條37係可以塗覆或真空⑽方式形成， 如圖15所示。 步驟S510係沿著該等橫向槽314物理破裂該半成品4ι， 以形成複數個晶片電阻器半成品42,其中每一晶片電阻器 半成品42至少具有二背面電極23、二正面電極22、二正面 輔助電極30及二側面電極27，如圖16所示。 接著，形成至少一鍍層於每一晶片電阻器半成品42之表 面，以形成複數個晶片電阻器2。在本實施例中該至少一 銀層係包含二層鍍層。步驟S511係形成一第一鍍層28以覆 φ 蓋該正面輔助電極30、該背面電極23及該側面電極27。在 其他應用中，如果該正面輔助電極3〇並未完全覆蓋每一正 面電極22之上表面（即該正面辅助電極條4〇之寬度小於該 正面電極條32之寬度），而顯露部分該正面電極22，該第 一鍵層28會更覆蓋到該顯露之正面電極22。步驟S512係形 成一第一鑛層29以覆蓋該第一链層28，如圖17。圖17所示 之晶片電阻器2與圖4j所示之晶片電阻器2相同。 惟上述實施例僅為說明本發明之原理及其功效，而非用 以限制本發明。因此，習於此技術之人士對上述實施例進 134268.doc •16- 201011783 行修改及變化仍不脫本發明之精神❶本發明之權利範圍應 如後述之申請專利範圍所列。 【圖式簡單說明】 圖1顯示習知晶片電阻器之剖視示意圖； 圖2顯示本發明之晶片電阻器之製造方法之流程示意 圖； 圖3a至3j顯示本發明之晶片電阻器之製造方法之各個製 程步驟之立體示意圖； 圖4a至4j顯示對應圖3a至3j之各個製程步驟之剖視示意 圖； 圖5顯示本發明之晶片電阻器之批次製造方法之流程示 意圖， 圖6至17顯示本發明之晶片電阻器之批次製造方法之各 個製程步驟之剖視示意圖。 【主要元件符號說明】 1 習知晶片電阻器 2 本發明之晶片電阻器 11 基材 12 正面電極 13 背面電極 14 電阻層 15 第一保護層 16 第二保護層 17 側面電極 134268.doc • 17· 201011783Step S203 is to form a resistive layer 24 in the middle of the front surface 213 of the substrate 21, and the resistive layer 24 has two end portions 241. As shown in the figure, the resistor layer 24 is in the embodiment. The printing method is formed, and the material thereof is a conductive ink such as bismuth, copper, silver or palladium. In step S204, two front electrodes 22 are formed on the front surface 213 of the substrate, and the front electrodes 22 are spaced apart from each other. Each front electrode 22 has an inner end portion 221, an inner side surface 222 and an outer side surface 223. The front electrode 22 extends over the resistive layer 24 such that the inner end portion 221 of the front electrode 22 is overlapped with the end portion 241 of the resistive layer 24, as shown in FIG. In the present embodiment, the front electrodes 22 are formed by printing. Step S205 is to form two front auxiliary electrodes 3 on the front electrodes 22, and each front auxiliary electrode 30 completely covers the wide side of each front electrode 22 such that the front auxiliary electrode 30 contacts the substrate. The front side 213' of 21 is shown in Figures 3e and 4e. The front auxiliary electrode 3 can be formed by printing, physical deposition or chemical deposition. Each of the front auxiliary electrodes 30 has an inner side surface 301 and an outer side surface 302. Preferably, the inner side surface 301 of the front auxiliary electrode 30 does not extend beyond the inner side surface 222 of the front surface electrode 22. The side surface 3〇1 does not exceed the outer side surface 223 of the front surface electrode 134268.doc -10· 201011783 22 . The front auxiliary electrode 3A may be in the form of a film, a block or an ink, but is not limited to the above-listed; and it has a chemical property which is resistant to vulcanization and corrosion-resistant. Step S206 forms a first protective layer 25 on the resistive layer 24, as shown in Figures 3f and 4f. The first protective layer 25 is constructed of a cleavable insulating material. Preferably, the step S206 further comprises the step of accurately cutting the resistive layer 24 with a high energy beam to modulate its resistance value. φ Step S207 forms a second protective layer 26 on the first protective layer 25 and a portion of the front auxiliary electrode 30, as shown in Figures 3g and 4g. In step S208, two side electrodes 27 are formed, and each of the side electrodes 27 is formed on the side surface 212 of the substrate 21, the outer side surface 223 of the front surface electrode 22, and the outer side surface 232 of the back surface electrode 23 for electrical connection. The front electrode 22 and the back electrode 23 are as shown in Figs. 3h and 4h. The side electrodes 27 can be formed by coating or by vacuum sputtering. Next, at least one mineral layer is formed to cover the front auxiliary electrodes 3, the φ and other back electrodes 23 and the side electrodes 27 to form a wafer resistor 2'. In other applications, the layer covers the same Front electrode 22. In this embodiment, the at least one plating layer comprises two layers of plating. Step S2〇9 forms a first plating layer 28 to cover the front surface auxiliary electrode 3A, the back surface electrode 23, and the side surface electrode 27, as shown in Figs. 3i and 4i. In other applications, if the front auxiliary electrode 30 does not completely cover the upper surface of each front electrode 22 (ie, the width of the front auxiliary electrode 3 is smaller than the width of the front electrode 22), a portion of the front electrode 22 is exposed. At this time, the first plating layer 28 will more cover the exposed front electrode 22. 134268.doc 201011783 Step S210 forms a second plating layer 29 to cover the first plating layer 28, as shown in Figures 3j and 4j. Referring to Figures 3j and 4j, perspective and cross-sectional views of the wafer resistor of the present invention are shown, respectively. The wafer resistor 2 includes a substrate 21, two back electrodes 23, a resistive layer 24, two front electrodes 22, two front auxiliary electrodes 3A, a first protective layer 25, a second protective layer 26, and two side electrodes. 27 and at least one layer of mine. The substrate 21 is made of an insulating material and has a plate shape in appearance, and has a back surface 211, two side surfaces 212, and a front surface 213. The back electrodes 23 are spaced apart from each other on the back surface 211 of the substrate 21. Each of the back electrodes 23 has an inner side 23 1 and an outer side 232. The outer surface 232 of the back surface electrode 23 is aligned with the side surface 212 of the substrate 21. These back electrodes 23 are electrically conductive. The resistive layer 24 is located on the front side 213 of the substrate 21. The resistive layer 24 has an end portion 241' of a material such as a nail, a copper, a silver, a conductive ink or the like. The front electrodes 22 are spaced apart from each other on the front side 213 of the substrate 21. Each of the front electrodes 22 has an inner end portion 221, an inner side surface 222 and an outer side surface 223, and the inner end portion 221 of the front surface electrode 22 is overlapped on the end portion 241 of the resistive layer 24. The outer surface 223 of the front electrode 22 is aligned with the side surface 212 of the substrate 21. These front electrodes 22 are electrically conductive. The material of the front auxiliary electrode 30 is selected from the group consisting of palladium, platinum, gold, graphite, carbon, and combinations thereof. The front auxiliary electrodes 3 are spaced apart on the front electrodes 22. Each front auxiliary electrode 30 completely covers the wide side of each front electrode 22, so that the front auxiliary electrode 3 is 134268.doc 12- 201011783 is in contact with the front side 213 of the substrate 21. The front auxiliary electrodes 30 are electrically conductive. Each of the front auxiliary electrodes 3A has an inner side surface 3〇1 and an outer side surface 302. Preferably, the inner side surface 3〇1 of the front auxiliary electrode 3〇 does not extend beyond the inner side surface 222′ of the front surface electrode 22 The outer side surface 301 of the auxiliary electrode 3 does not extend beyond the outer side surface 223 of the front electrode 22. The front auxiliary electrode 30 may be of a film, a block or an ink, but is not limited to the above; and it has an electrical property which is resistant to vulcanization and corrosion resistance. The first protective layer 25 covers the resistive layer 24, and the first protective layer 25 is formed of a cleavable insulating material. The second protective layer 26 covers the first protective layer 25 and a portion of the front auxiliary electrode 3A. Each of the side electrodes 27 is located on the side surface 212 of the substrate 21, the outer side surface 223 of the front surface electrode 22, the outer side surface 302 of the front auxiliary electrode 3 and the outer side surface 232 of the back surface electrode 23 for electrical connection. The front electrode 22 and the back surface electrode 23. The side electrodes 27 are electrically conductive. The at least one plating layer covers the front auxiliary electrode 30, the back surface electrodes 23, and the side surface electrodes 27'. In other applications, the plating layer covers the front side electrodes 22. In this embodiment, the at least one plating layer includes a first clock layer 28 and a second plating layer 29. The first plating layer 28 is a nickel layer and covers the front surface auxiliary electrode 30, the back surface electrode 23, and the side surface electrode 27. In other applications, 'if the front auxiliary electrode 3 〇 does not completely cover the upper surface of each front electrode 22 (ie, the width of the front auxiliary electrode 3 小于 is smaller than the width of the front electrode 22), the portion of the front electrode 22 is exposed. The first plating layer 28 will cover the exposed front electrode 22. The second plating layer 29 is a tin layer and covers the first forged layer 28. 134268.doc •13· 201011783 The invention has the advantages of increasing the positive auxiliary electrodes 30 having anti-vulcanization and corrosion resistance, which can effectively protect the front electrodes 22 from sulfur gas and other corrosive gases. The effect is that the conventional chip resistor 1 can easily change the resistance value due to environmental influences or even cause an open circuit to cause the system to fail. In addition, the process of the present invention first forms the resistive layer 24 and then forms the front electrodes 22, so that the front electrodes 22, the front auxiliary electrodes 3A, and the second protective layer are slightly offset. The amount can still ensure that the front electrodes 22 are effectively protected from sulfur gas and other corrosive gases. Referring to Fig. 5, there is shown a flow chart showing a method of manufacturing a wafer resistor of the present invention. Referring to Figures 6 through 17, there are shown schematic cross-sectional views of various process steps of the batch manufacturing method of the wafer resistor of the present invention. Step S501 provides an insulating substrate 31 having a back surface 311, a front surface 313, a plurality of lateral grooves 314, and a plurality of longitudinal grooves 315. The transverse grooves 314 and the longitudinal grooves 315 are located on the front surface 313 and are interleaved to define a plurality of component cell regions 316, as shown in Figures 6 and 7. The insulating substrate 31 may be, for example, a glass substrate, a ceramic substrate, or a substrate made of an epoxy tree. Preferably, the depths of the lateral grooves 314 and the longitudinal grooves 315 are set within a few micrometers. The predetermined semi-finished product can be physically ruptured in a subsequent process. In step S502, a plurality of back electrode strips 33 are formed on the back surface 311 of the substrate 31. The back electrode strips 33 are aligned with the longitudinal grooves 315. In the present embodiment, the back electrode strips 33 are located directly below the longitudinal grooves 315, as shown in FIG. In the present embodiment, the back electrode strips 33 are formed by printing on 134268.doc • 14· 201011783. Step S5°^3 forms a resistive layer 24 in the middle of the front surface of each of the element cell regions 316, and the resistive layer 24 has two end portions (4). As shown in FIG. 9, in the present embodiment, the resistive layer The 24 series is formed by printing, and the material thereof is a conductive ink such as nail, copper, silver or palladium. Step S5 04 forms a plurality of front electrode strips 32 on the front side 313 of the substrate 31, and each front electrode strip 32 is located between two adjacent resistive layers 24 and traverses the longitudinal grooves 315. The front electrode strips 32 extend over the resistive layer 24 such that the ends of the front electrode strips 32 are spliced to the ends 241 of the resistive layer 24 as shown in FIG. 10 in the present embodiment. The front electrode strips 32 are formed by printing. Step S5 05 forms a front auxiliary electrode strip 4 on each of the front electrode strips 32' and each of the front auxiliary electrode strips 4 completely covers the wide side of each of the front electrode strips 32 such that the front auxiliary electrode strips 4 The crucible will come into contact with the front surface 3 of the substrate 31, as shown in FIG. The front auxiliary electrode strips 40 can be formed by printing, physical deposition or chemical deposition. The front auxiliary electrode strip 40 may be of a film, a block or an ink, but is not limited to the above; and it has a chemical property which is electrically conductive, resistant to vulcanization, and resistant to corrosion. Step S506 forms a first protective layer 25 on each of the resistive layers 24, as shown in FIG. The first protective layer 25 is constructed of a cleavable insulating material. Preferably, after step S506, the step of accurately cutting the resistive layer 24 with a high energy beam to modulate its resistance value is further included. Step S507 forms a second protective layer 26 on each of the first protective layers 25 134268.doc -15-201011783 and a portion of the front auxiliary electrode strip 40, as shown in FIG. Step S508 physically ruptures the substrate 3 along the longitudinal grooves (1) to form a plurality of strip-shaped semi-finished products 41, each of which has three fracture faces 411, as shown in FIG. Step S509 forms a side electrode strip 37 on each of the semi-finished products "to electrically connect the front electrode strip" and the back electrode strip 33. The side electrode strips 37 can be formed by coating or vacuum (10), as shown in FIG. Step S510 physically ruptures the semi-finished product 4 ι along the transverse grooves 314 to form a plurality of wafer resistor blanks 42 , wherein each of the wafer resistor blanks 42 has at least two back electrodes 23 , two front electrodes 22 , and two front auxiliary electrodes 30 and two side electrodes 27 are as shown in FIG. Next, at least one plating layer is formed on the surface of each of the wafer resistor blanks 42 to form a plurality of wafer resistors 2. In this embodiment, the at least one silver layer comprises two layers of plating. In step S511, a first plating layer 28 is formed to cover the front auxiliary electrode 30, the back surface electrode 23, and the side surface electrode 27. In other applications, if the front auxiliary electrode 3〇 does not completely cover the upper surface of each front electrode 22 (ie, the width of the front auxiliary electrode strip 4〇 is smaller than the width of the front electrode strip 32), the front portion is exposed. The electrode 22, the first key layer 28 will more cover the exposed front electrode 22. Step S512 forms a first ore layer 29 to cover the first chain layer 28, as shown in FIG. The wafer resistor 2 shown in Fig. 17 is the same as the wafer resistor 2 shown in Fig. 4j. However, the above-described embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Therefore, those skilled in the art will be able to make modifications and variations to the above-described embodiments without departing from the spirit of the invention. The scope of the invention should be as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional view showing a conventional wafer resistor; FIG. 2 is a flow chart showing a method of manufacturing a wafer resistor of the present invention; and FIGS. 3a to 3j are views showing a method of manufacturing a wafer resistor of the present invention. 3a to 4j are schematic cross-sectional views showing respective process steps corresponding to Figs. 3a to 3j; Fig. 5 is a flow chart showing the batch manufacturing method of the wafer resistor of the present invention, and Figs. 6 to 17 show A schematic cross-sectional view of various process steps of a batch manufacturing method for a wafer resistor of the invention. [Major component symbol description] 1 conventional wafer resistor 2 wafer resistor 11 of the present invention substrate 12 front electrode 13 back electrode 14 resistance layer 15 first protective layer 16 second protective layer 17 side electrode 134268.doc • 17· 201011783
18 第一鍍層 19 第二鍍層 21 基材 22 正面電極 23 背面電極 24 電阻層 25 第一保護層 26 第二保護層 27 側面電極 28 第一鍍層 29 第二鍍層 30 正面輔助電極 31 絕緣基板 32 正面電極條 33 背面電極條 37 側面電極條 40 正面輔助電極條 41 條狀半成品 42 晶片電阻半成品 111 基材之背面 112 基材之側面 113 基材之正面 121 正面電極之内側面 122 正面電極之外側面 134268.doc •18- 201011783 123 正面電極之内端部 131 背面電極之内侧面 132 背面電極之外側面 211 基材之背面 212 基材之側面 213 基材之正面 221 正面電極之内端部 Φ 222 正面電極之内侧面 223 正面電極之外側面 231 背面電極之内侧面 232 背面電極之外側面 241 電阻層之端部 301 正面辅助電極之内側面 302 正面輔助電極之外側面 311 基板之背面 313 基板之正面 314 橫向槽 315 縱向槽 316 元件單體區 411 破裂面 134268.doc -19-18 First plating layer 19 Second plating layer 21 Substrate 22 Front electrode 23 Back electrode 24 Resistance layer 25 First protective layer 26 Second protective layer 27 Side electrode 28 First plating layer 29 Second plating layer 30 Front auxiliary electrode 31 Insulating substrate 32 Front side Electrode strip 33 Back electrode strip 37 Side electrode strip 40 Front auxiliary electrode strip 41 Strip semi-finished product 42 Wafer resistor semi-finished product 111 Back surface of substrate 112 Side surface of substrate 113 Front side of substrate 121 Inner side of front electrode 122 Front side of front electrode 134268.doc •18- 201011783 123 The inner end of the front electrode 131 The inner side of the back electrode 132 The back side of the back electrode 211 The back side of the substrate 212 The side of the substrate 213 The front side of the substrate 221 The inner end of the front electrode Φ 222 Inner side surface 223 of front electrode Front side surface 231 of front side electrode Inner side surface 232 of back surface electrode Side surface 241 of back surface electrode End portion 301 of resistive layer Inner side surface 302 of front auxiliary electrode Side surface of front auxiliary electrode 311 Back side of substrate 313 Substrate Front side 314 transverse groove 315 longitudinal groove 31 6 component cell area 411 fracture surface 134268.doc -19-