201009568 九、發明說明： 【發明所屬之技術領域】 本發明為一種電腦重置系統及系統重置方法，尤指一 種於中央處理單元發生程序異常時’可對中央處理單元重 置的電腦重置系統及方法。 【先前技術】 參考第一圖與第二圖。第一圖為傳統的電腦重置系統 之電路功能方塊示意圖。第二圖為傳統電腦重置系統的信 號示意圖。電腦重置系統1包括一重置電路1〇、一中央處 理單元12及一週邊裝置14。當電腦（未標示）開機時，重置 電路10接收到一致能的開機電源Vcc，並開始啟動。重置 電路10於接收到致能的開機電源Vcc後，經過第一延遲 時間Tdl，即輸出一高準位之系統重置信號SR給中央處 理單元12,用以啟動中央處理單元12，此時中央處理單元 12開始執行重置程序，以進行啟始化(Initializati〇n)操作。201009568 IX. Description of the Invention: [Technical Field] The present invention relates to a computer reset system and a system reset method, and more particularly to a computer reset capable of resetting a central processing unit when a program abnormality occurs in a central processing unit. System and method. [Prior Art] Reference is made to the first figure and the second figure. The first picture shows the circuit function block diagram of a traditional computer reset system. The second picture shows the signal diagram of a traditional computer reset system. The computer reset system 1 includes a reset circuit 1A, a central processing unit 12, and a peripheral device 14. When the computer (not shown) is turned on, the reset circuit 10 receives the consistent power-on power supply Vcc and starts up. After receiving the enabled power-on power supply Vcc, the reset circuit 10 outputs a high-level system reset signal SR to the central processing unit 12 for activating the central processing unit 12 after the first delay time Tdl. The central processing unit 12 begins executing a reset procedure to perform an Initialization operation.
接著，中央處理單元12在接收到高準位之系統重置 信號SR後，經過第二延遲時間Td2，隨即輸出一高準位 之硬體重置信號HR給週邊裝置14，用以啟動週邊裝置 14，以進行週邊裝置14的啟始化(脇地加㈣操作。其 中，週邊裝置14可以為一記憶體單元。 八 _另外，由於重置電路10僅能對中央處理單幻2提供 手-脈衝的系統重置信號SR，因此，當 ^ 執行重置㈣時發㈣序錯觸重置失敗時因^有2 得整個系統無法操作。此時 置程序’使 ^ J以扪用一手動開關SW1 201009568 控制重置電路IG再次產生系統重置信號SR。 復參考第一囷與第二圖，一般於中央處理單元内 =置-看Hmt_(WATCH臓雇R)，#中央處 入，兀12發生錯誤事件如執行懸停或看門狗計時器的内 ，計時值未被規律清除時，將發生脉，使得巾央處理單 =12的硬體重置腳位發出的硬體重置信號服由高準位短 處成低準位’形成—脈衝訊號，用以重置連接於中央 ❹ 置。丨…、忐於糸統異常發生時，對中央處理單元12進行重 【發明内容】 2於此’本發明的電腦重置祕及純重置方法， 體重置，根據中央處理單元產生的硬 電路，訊號之負緣’而觸發-重置 =以在中央處理單元重新啟動後，再次被中央= 路、ί Γ:卢較二實施例的電腦重置系統包括-重置電 單元輕接二元。其中’中央處理 以且=處理單元於異常發輸 電路二u產生單元減於該巾域理較與該重Ϊ 該硬體iC單元在中央處理單元發生異常時，接收 重置電路，用以控制該重置電路 ^ 201009568 本發明較佳實施例的系統重 先，_中央處理單元所送出的 重置二驟包括·· f 根據該硬體重置信號，用㈣ =置彳§號。然後， 異常，在此可以根據硬體重二==是否發j 當異常發生時，根據該號。另外， 生單元’以對該中央處理單元進行5重置操作觸發-信號產 機：法=====理單元因為程式當 當週邊裝置如記憶趙，其讀效二題本二 :;有效對中央處理單元進行重置，使整個系時二 以上的概述與接下來的詳細說明皆為 了進-步說明本發明的中請專利範圍。 其 他目的與優點，將在後續的說明與圖示加以^發 【實施方式】 ❹ 參考第三圖與第四圖。第三圖為本發明較佳實施例的 電腦重置系統之電路功能方塊示㈣。第四圖為本發明較 佳實施例的電腦重置系統的信號示意圖 系統2包括一重置電路2〇、一中央處理單元m二 產生單元24。 中央處理單元22耦接於重置電路20，係從重置電路 20接收一系統重置信號SR，並且，中央處理單元22於異 常發生時，係輸出一硬體重置信號HR。信號產生單元24 ，接於該中央處理單元22與該重置電路2〇，該信號產生 單元24在中央處理單元22發生異常時，接收該硬體重置 201009568 信號HR’以及根據該硬體重置信號HR以輸出一控制信號 MC給該重置電路20,用以控制該重置電路20重置該中央 處理單元22。 復參考第三圖與第四圖’當電腦（未標示）開機時，重 置電路20接收到一致能的開機電源Vcc’並開始啟動。重 置電路20於接收到致能的開機電源Vcc後，經過第一延 遲時間Tdl，即輸出系統重置信號SR給中央處理單元22, 用以啟動中央處理單元22，此時中央處理單元22開始執 行重置程序，以進行啟始化(Initialization)操作。中央處理 單元22在接收到系統重置信號SR後’經過第二延遲時間 Td2，隨即輸出硬體重置信號HR給週邊裝置26，用以啟 動週邊裝置26,以進行週邊裝置26的啟始化(initialization) 操作。 在中央處理單元22程序執行過程中，如果發生異常， 將使得看門狗計時器（WATCH DOG TIMER)發生溢位，因 而導致中央處理單元22發出的硬體重置信號HR產生一低 準位脈衝訊號。此低準位脈衝訊號可用以重置連接於中央 處理單元22的週邊裝置26。另外，當信號產生單元24接 收到硬體重置信號HR的低準位脈衝訊號，將會由該低準 位脈衝訊號之負緣觸發輸出除能的該控制信號MC至該重 置電路20的一手動重置腳位MR，用以截止該重置電路2〇 的動作。前述的信號產生單元24可以由一硬體電路或一可 程式邏輯電路所實施。 重置電路20接收除能的該控制信號MC之後，經過 一第三延遲時間Td3 ,即停止輸出系統重置信號SR至該 中央處理單元22。再經過一第四延遲時間Td4，該中央處 201009568 - 理單元22也停止硬體重置信號HR的輸出。此時，中央處 理單元22與週邊裝置26將進入停滯的狀態。 同時，信號產生單元24根據硬體重置信號HR的低準 位脈衝訊號之負緣所觸發，輸出除能的該控制信號Mc 一 段設定時間Tdm，並於該段設定時間Tdm到達時，信號產 生單元24的輸出將由除能的該控制信號撾(：轉換為致能的 該控制信號MC ’此時，致能的該控制信號Mc用以重新 啟動該重置電路20。 ❿ 前述中，信號產生單元24可以調整設定時間Tdm的 長短，且设定時間Tdm必須長於重置電路可接受之最 短觸發時間。因為每一家所生產的重置電路2〇，豆可接為 之最短觸發時間規格皆不相同，因此，前述的信號產^ 元24所調整的設定時間Tdmi少需大於重置電路2〇所要 求的最短觸發時間。同時，為確保重置電路2 Q可被作 生單元24送出之控制信號MC所觸發，而可調整該言^時 間Tdm略長·~些。 早儿22,以再次啟始化中央處理單元22 j .間加，也再次輸出硬體重 再次啟動化週邊裝置26。 浐置26以 綜上所述，本發明的電腦重置“ 計時器溢位時，根據中央處理單 ’、在看門狗 HR的低準位脈衝訊號之負緣 ^的㈣重置信號 所觸發，用以控制重置電路 201009568 t 央處理單元2 2再次的進行重置操作。而週邊楚 Ϊ田…在中央處理單元22錄啟動後，再次被中麥 處理早兀22重置。 穴 ?此，本發明的電難置祕2將可以有效解決中央 為程式當機’卻無法獲得重置而導致整個系 ❹ 驗狢士 ^。同時’當週邊裝置26如記憶體，其讀/寫 f巧生，'常時’本發明的電腦重置系統2也可以有效對 中央處理單元22進行重置，使整個系統可以回復正常政對 四圖’參考第五圖。第五圖為本發明的流程示 忍圖本發明的系統4置方法步驟如下：首先，在 ϋ]先Ϊ中央處理單元2 2所送出的硬體重置信號HR進 仃偵測，而該中央處理單元22送出該硬體 會傳送給週邊裝置26。(_。然後 也 皿，用以靖中央處理單元22是否發生異常(Sl2)。^ 步驟S12中’乃是根據硬體重置信號HR的低準位脈衝 硬=重置域HR的低準位脈衝訊號尚未發生時，即表二 硬重置彳5號hr保持致能狀態，中央處理單元u ^ ^ t的硬2體重置信號HR的低準位脈衝訊號 態，中二=广從致能狀態變為除能狀 在步驟S12之後，當判斷結果是中央處理 未發生異常’則回到步驟S10’繼續偵測硬體 祙 心另外，若是判斷結果是中央處理單元^ 號 ，號產生單元24將根據硬體重置信號以位: 訊號所觸發，以產生除能的控制信號Mc給重=== 201009568 用以截止重置電路20。在該重置電路2〇 ^ 號產生單元24係經過一設定時間止之後，該信 致能的控制信號MC以重新啟動重置電路圖）接著產生 的控制信號MC用以控制重置電路2〇 〇。此時，致能 22(S14)。而週邊裝置26也可以在中 ^中央處理單元 動後，再次被中央處理單元22重置。單元22重新啟Then, after receiving the system reset signal SR of the high level, the central processing unit 12 outputs a high-level hardware reset signal HR to the peripheral device 14 after the second delay time Td2, to activate the peripheral device 14 In order to perform the initialization of the peripheral device 14 (the fourth operation), the peripheral device 14 may be a memory unit. In addition, since the reset circuit 10 can only provide the hand-pulse for the central processing unit 2 The system reset signal SR, therefore, when ^ is reset (four), the (four) sequence error reset fails. Because the ^ has 2, the whole system cannot be operated. At this time, the program is set to 'make a manual switch SW1. 201009568 Control reset circuit IG generates system reset signal SR again. Refer to the first and second pictures, generally in the central processing unit = set - see Hmt_ (WATCH 臓 hire R), #中央处入, 兀12 occurs If an error event occurs in the hover or watchdog timer, the timing value will not be cleared regularly, and the pulse will be generated, so that the hardware reset signal issued by the hardware resetting single=12 hardware reset signal is subject to Micro Motion. Bit short into low level 'formation-pulse No. is used to reset the connection to the central device. 丨..., when the system abnormality occurs, the central processing unit 12 is heavy. [Inventive content] 2 The computer resetting secret and pure reset method of the present invention , body reset, according to the hard circuit generated by the central processing unit, the negative edge of the signal's trigger-reset = after the central processing unit is restarted, again by the central = road, Γ Γ: Lu compared to the computer of the second embodiment The system includes a resetting unit that is connected to the binary, wherein the 'central processing and the = processing unit are in the abnormal transmission circuit and the second generation unit is subtracted from the area and the unit is processed in the central unit. When the unit is abnormal, receiving a reset circuit for controlling the reset circuit ^ 201009568 The system of the preferred embodiment of the present invention first, the reset second step sent by the central processing unit includes ·· f according to the hardware reset letter No., use (4) = set § §. Then, abnormal, here can be based on hard weight two == whether to send j when the abnormality occurs, according to the number. In addition, the raw unit 'to reset the central processing unit 5 Operation trigger-signal Machine: law ===== rational unit because the program Dangdang peripheral device such as memory Zhao, its effect two questions: 2; effectively reset the central processing unit, so that the entire system is more than two overview and the following details The description of the present invention is intended to provide a further understanding of the scope of the present invention. Other objects and advantages will be apparent from the following description and drawings. [Embodiment] 第三 Referring to the third and fourth figures. The circuit function block of the computer reset system of the preferred embodiment of the present invention is shown in (4). The fourth figure shows the signal schematic system 2 of the computer reset system according to the preferred embodiment of the present invention. The system 2 includes a reset circuit 2 and a central processing unit m. The second processing unit 22 is coupled to the reset circuit 20 to receive a system reset signal SR from the reset circuit 20, and the central processing unit 22 outputs a hardware reset signal HR when an abnormality occurs. . The signal generating unit 24 is connected to the central processing unit 22 and the reset circuit 2, and the signal generating unit 24 receives the hardware reset 201009568 signal HR' and according to the hardware reset signal when the central processing unit 22 is abnormal. The HR outputs a control signal MC to the reset circuit 20 for controlling the reset circuit 20 to reset the central processing unit 22. Referring to the third and fourth figures, when the computer (not shown) is turned on, the reset circuit 20 receives the power-on power supply Vcc' of the same power and starts up. After receiving the enabled power-on power Vcc, the reset circuit 20 passes the first delay time Tdl, that is, outputs the system reset signal SR to the central processing unit 22 to start the central processing unit 22, and the central processing unit 22 starts. Perform a reset procedure for the Initialization operation. After receiving the system reset signal SR, the central processing unit 22 passes the second delay time Td2, and then outputs the hardware reset signal HR to the peripheral device 26 to activate the peripheral device 26 to initiate the peripheral device 26 ( Initialization) operation. During the execution of the program of the central processing unit 22, if an abnormality occurs, the watchdog timer (WATCH DOG TIMER) will overflow, thereby causing the hardware reset signal HR sent by the central processing unit 22 to generate a low level pulse signal. . This low level pulse signal can be used to reset peripheral device 26 connected to central processing unit 22. In addition, when the signal generating unit 24 receives the low level pulse signal of the hardware reset signal HR, the output signal MC that is disabled by the output of the low level pulse signal is triggered to one of the reset circuit 20 The pin MR is manually reset to cut off the action of the reset circuit 2〇. The aforementioned signal generating unit 24 can be implemented by a hardware circuit or a programmable logic circuit. After receiving the disabled control signal MC, the reset circuit 20 stops outputting the system reset signal SR to the central processing unit 22 after a third delay time Td3. After a fourth delay time Td4, the central unit 201009568 - the unit 22 also stops the output of the hardware reset signal HR. At this time, the central processing unit 22 and the peripheral device 26 will enter a stagnant state. At the same time, the signal generating unit 24 is triggered according to the negative edge of the low-level pulse signal of the hardware reset signal HR, and outputs the disabled control signal Mc for a set time Tdm, and when the set time Tdm arrives, the signal generating unit The output of 24 will be deactivated by the control signal (: converted to the enabled control signal MC'. At this time, the control signal Mc is enabled to restart the reset circuit 20. 前述 In the foregoing, the signal generating unit 24 can adjust the length of the set time Tdm, and the set time Tdm must be longer than the shortest trigger time acceptable by the reset circuit. Because each of the reset circuits produced by the manufacturer has the shortest trigger time specifications, the beans can be connected to each other. Therefore, the set time Tdmi adjusted by the aforementioned signal generating unit 24 needs to be smaller than the minimum triggering time required by the reset circuit 2〇. Meanwhile, the control signal for ensuring that the reset circuit 2 Q can be sent by the generating unit 24 is provided. The MC triggers, and the statement can be adjusted. The time Tdm is slightly longer. Some children 22, to start the central processing unit 22 j again, and again, the hard weight is restarted. In the above, the computer 26 of the present invention resets the "fourth reset" of the low-level pulse signal of the watchdog HR according to the central processing unit when the timer overflows. The signal is triggered to control the reset circuit 201009568, and the processing unit 2 2 performs the reset operation again. However, after the central processing unit 22 starts to be activated, it is reset by the middle wheat processing. In this case, the electric hard-to-find 2 of the present invention can effectively solve the problem that the central station is a program's failure to obtain a reset, resulting in the entire system being tested by the gentleman ^. At the same time 'when the peripheral device 26 is like a memory, its reading/ Write the computer, 'normally' the computer reset system 2 of the present invention can also effectively reset the central processing unit 22, so that the entire system can return to the normal political map four reference 'fifth map. The fifth figure is the invention The process of the system 4 of the present invention is as follows: First, the hardware reset signal HR sent by the central processing unit 2 is detected first, and the central processing unit 22 sends the hardware. Transfer to peripheral device 26. (_. Then The dish is used to determine whether an abnormality has occurred in the central processing unit 22 (S12). ^ In step S12, 'the low level pulse according to the hardware reset signal HR is hard=when the low level pulse signal of the reset domain HR has not occurred yet, That is, the table 2 hard reset 彳 5 hr remains enabled state, the central processing unit u ^ ^ t hard 2 body reset signal HR low level pulse signal state, the middle two = wide from the enabling state to the de-energized state After the step S12, when the result of the determination is that the central processing has not occurred abnormally, then returning to step S10' to continue detecting the hardware core, and if the result of the determination is the central processing unit, the number generating unit 24 will reset the signal according to the hardware. Triggered by the bit: signal to generate the de-energized control signal Mc to give weight === 201009568 to turn off the reset circuit 20. After the reset circuit 2 产生 产生 generating unit 24 has passed a set time, the signal enable control signal MC is used to control the reset circuit 2 by restarting the reset circuit diagram. . At this time, enable 22 (S14). The peripheral device 26 can also be reset by the central processing unit 22 again after the central processing unit is activated. Unit 22 restarts
综上所述’本發明的系統重置方 央處理單元22因為程式當機，卻無法猝俨^以有效解決中 系統失效的問題。㈣，當週邊裝置^f置而導致整個 寫操作發生異料，本發明的系統重置魏體’其讀/ 中央處理單元22騎重置，使整㈣、財正有^對 按，以上所述，僅為本發明最佳之具 發明之特徵並不侷限於此，任何熟錢項私者^本 範Γ易思及之變化或修飾，皆可:蓋在以;本 【圖式簡單說明】 第-圖為傳統的電腦重置緖之電路功能方塊示意圖； 第二圖為傳統電腦重置系統的信號示意圖； 第三圖為本發明較佳實施例的電腦重置系統之電路功能方 塊示意圖； 第四圖為本發明較佳實施例的電腦重置系統的信號示意 圖；及 第五圖為本發明的流程示意圖。 【主要元件符號說明】 習知： 11 201009568In summary, the system resetting unit processing unit 22 of the present invention cannot solve the problem of system failure because the program is down. (4) When the peripheral device is placed to cause the entire write operation to occur, the system of the present invention resets the Wei body's read/central processing unit 22 to ride the reset, so that the whole (four), the wealth is positively pressed, the above As described above, the features of the invention are not limited thereto, and any change or modification of the skilled person can be: cover; The first figure is a schematic diagram of the circuit function of the traditional computer reset system; the second figure is the signal diagram of the traditional computer reset system; the third figure is a schematic diagram of the circuit function of the computer reset system according to the preferred embodiment of the present invention; The fourth figure is a schematic diagram of signals of a computer reset system according to a preferred embodiment of the present invention; and the fifth figure is a schematic flow chart of the present invention. [Main component symbol description] Convention: 11 201009568
電腦重置系統1 重置電路10 中央處理單元12 週邊裝置14 開機電源Vcc 第一延遲時間Tdl 第二延遲時間Td2 系統重置信號SR 0 硬體重置信號HR 手動開關SW1 本發明：Computer reset system 1 reset circuit 10 central processing unit 12 peripheral device 14 power-on power supply Vcc first delay time Tdl second delay time Td2 system reset signal SR 0 hardware reset signal HR manual switch SW1 The present invention:
電腦重置系統2 重置電路20 信號產生單元24 中央處理單元22 週邊裝置26 系統重置信號SR • 硬體重置信號HRComputer reset system 2 reset circuit 20 signal generation unit 24 central processing unit 22 peripheral device 26 system reset signal SR • hardware reset signal HR
控制信號MC 開機電源Vcc 第一延遲時間Tdl 第二延遲時間Td2 第三延遲時間Td3 第四延遲時間Td4 設定時間Tdm 手動重置腳位MR 12Control signal MC Power-on power supply Vcc First delay time Tdl Second delay time Td2 Third delay time Td3 Fourth delay time Td4 Set time Tdm Manual reset pin MR 12