201009529 九、發明說明： 【發明所屬之技術領域】 本發明係關於一電壓穩壓器，尤指具有消除或是降低衝擊電 流的一低壓降穩壓器與其控制方法。 【先前技術】 低壓降穩壓器(Low Drop-out Regulator)是一種習知簡易的直 ❹ 流轉直流(DC to DC)的電壓穩壓器。如果沒有讓低壓降穩壓器於啟 動時先進入一緩啟動(softstart)狀態，就直接進入一正常狀態，則 低壓降穩壓器於電源啟動時便會產生一高額的衝擊電流(Inmsh current)。此衝擊電流可能會造成提供給該低壓降穩壓器的電源來 不及反應而產生一電源端的壓降，如此便可能影響到耦接於該電 源的其他電路。因此，當啟動該低壓降穩壓器時一般需要先進入 所謂的緩啟動(softstart)狀態，以降低或是消除不必要的衝擊電 流。但是緩啟動狀態如何控制則是有不同的作法。 【發明内容】 本發明之一實施例提供一種控制 爾路’翻於-電壓穩壓器 (voltage regulator)。該電壓穩壓器包令右— h入七^ 匕矛有一功率開關。該控制電路 包含有一可變電阻產生單元以及一彳貞 一 Ί〜巧*%路。該 產單 元提供阻值隨時間變化之一可變雷卩日- 欒雷阳…#… 其中一參考電流流經該可 關之-電流。該侧電路__^⑽係代表流經該功率開 第通授電壓達到或是高於201009529 IX. Description of the Invention: [Technical Field] The present invention relates to a voltage regulator, and more particularly to a low-dropout voltage regulator and a control method thereof for eliminating or reducing the surge current. [Prior Art] The Low Drop-out Regulator is a conventional simple DC to DC voltage regulator. If the low-dropout regulator is not put into a softstart state at startup, it will enter a normal state, and the low-dropout regulator will generate a high amount of inrush current when the power is turned on. . This inrush current may cause the power supply to the low-dropout regulator to react to a voltage drop at the power supply, which may affect other circuits coupled to the power supply. Therefore, when starting the low-dropout regulator, it is generally necessary to enter a so-called softstart state to reduce or eliminate unnecessary surge currents. However, there are different ways to control the slow start state. SUMMARY OF THE INVENTION One embodiment of the present invention provides a control circuit that turns on a voltage regulator. The voltage regulator package makes the right-h into the seven^ spear with a power switch. The control circuit includes a variable resistance generating unit and a circuit. The production unit provides one of the resistance values as a function of time. Thunder Day - 栾雷阳...#... One of the reference currents flows through the calibratable current. The side circuit __^(10) is representative of the power flowing through the power to reach or exceed the voltage.
S 201009529 一預設值時，降低該功率開關之導通程度。 本發明之另-實酬提供—種碰穩㈣，包含有一如前段 所述之控制電路以及-放大器。該放A||係根據1二迴授電壓又 與-參考值來產生-補該功補關之控制輯，其中該第二迴 授電壓係代表該電壓穩虔器之一輸出電壓。 〇 本㈣實施織供—種㈣綠，適轉-電壓麵 器。該電壓穩壓器包含有—功率_。該控制方法包含有下列步 驟：提供-可變電阻；產生代表流經該神糊之1流之一參 考電流；使該參考f流流經該可㈣阻：細财變電阻上之一 第一迴授電壓；當_職第—迴授縣制或是高於-預設值 時，降低該功率_之導通程度；以及，隨_變化改變該可變 電阻之阻值。 ❹ 【實施方式】 在說明書及後續的申請專利範圍當中使用了某些詞彙來指稱 ^疋的70件。所屬領域巾具有通常知識者應可理解，硬體製造商 可此會用不同的名詞來稱啤同-個元件。本說明書及後續的申請 專利&圍並名稱的差異來作為區分元件的方式，而是以元件 能上的差異來作為區分的準則。在通篇說明書及後續的請求 =田中所提及的「包含」係為一開放式的用語，故應解釋成「包 S但不限定於」。此外，「耦接」一詞在此係包含任何直接及間接 201009529 的電氣連接手段’因此，若文中描述—第—裝置耦接於一第二裝 置，則代表該第一裝置可直接電氣連接於該第二裝置，或者透過 其他裝置或連接手段間接地電氣連接至該第二裝置。 切參考第1圖。第i圖所示係依據本發明電壓穩壓器(v〇ltage regulator)l〇〇之一實施例示意圖。電壓穩壓器励&含有一電壓穩 壓電路102以及一控制電路1〇4,其中電壓麵電路102係將-輸 ❹入電壓轉換成一輸出電壓Vout。控制電路1〇4防止電壓穩壓電路 102 的衝擊電流(inrushcurrent)e 電壓穩壓電路1G2包含有-誤差放大器师沉 amplifler)i022、一功率開關pM〇s電晶體⑷以及一電阻分塵器 1024 輸出電容Cout係轉接於一輸出端N〇ut,熟習此項技術者 應可瞭解輸出電容C〇ut之一功能係可以穩定本發明電壓穩壓器 之輸出電壓Vout。電壓穩壓電路1〇2其内部電路連接如圖所 © 不’為業界具有普通知識者可以了解，不再多述。簡單的說，電 壓穩壓電路102利用迴授電壓Vfi所提供之負迴授控制，希望將 輸出電壓V〇ut穩定在約等於Vout_target(=參考電屋 ;其中，Rx為電阻Rx的阻值。 控制電路104包含有一 PM0S電晶體M2、一偵測電路1〇44、 -控制訊號產生器嶋以及—電阻產生器麗。控制喊產生器 1046和電阻產生器1042構成一可變電阻產生單元。pM〇s電晶體 7 201009529 M2與功率開關PMOS電晶體Ml形成一電流鏡(curremmirr〇r)， 用來依據流經功率開關PM0S電晶體Ml之一輸出電流Iout來產 生大約等比例之一參考電流lref。依據輸出電壓v〇ut、緩啟動時間 Ts以及參考電壓Vthl ’控制訊號產生器1〇46產生一控制訊號 Sad’來決定當下電阻產生器麗之電阻值〜^電阻產生器難 包含有一電阻Ra串聯於一電阻Rb以及一_〇3電晶體M3並聯 於電阻Rb，其中NMOS電晶體M3之一閘極端N2耦接至控制訊 ❹ 號Sad。偵測電路1044,圖中以一比較器為例，偵測參考電流㈣ 所導致的-迴授電壓Vf2。當迴授電壓Vf2達到或高於一參考電 壓Vth2時，偵測電路1〇44改變功率開關PM〇s電晶體M1的導 通程度，譬如說，降低PM0S電晶體Ml的導通程度或是完全關 閉PM0S電晶體Ml。簡單的說，控制電路1〇4利用負迴授控制， 希望將輸出電流lout限制在最大容許值lHmit(=參考電壓 以下’且電阻值可隨時間變化而改變。匕細可以在緩啟動 ❹時，先給-個比較大的值’所以Ilimit比較小，藉以消除衝擊電流 的發生；而一過了緩啟動後，則給予一比較小的值，所以— 變大’來定義正常狀態時貞朗需限綱最大電流。相較於電壓 穩壓電路102，控制電路1〇4的開路迴_寬(〇卿1〇〇p band ^她） 可以设計的比較大，也就是反應逮度比較快。控制電路1〇4可以 比較快的反應速度，快速地防止輸出電流1〇加過高的情形發生。 第2圖為第1圖之電屢穩壓器1〇〇的參考電壓VtM、輸出電 壓Vout和控制訊號Sad，於一實施例中的時序圖。當電壓穩壓器 8 201009529 100於時間T1被啟動時，會直接使參考電壓Vthi達一個預設值， 然後進入-緩啟動(softstart)的狀態(緩啟動時間Ts的時段内介 ;寺門T1到T2之間）。在s亥緩啟動時間Ts内，輸出電壓v〇ut還 未達到-預定值Voutjarget，因此電壓穩壓電路1〇2會希望開啟 p=〇s電晶體M1 ’來對輸出電容c〇ut充電，拉高輸出電壓v⑽； 但疋’此時PMOS電晶體Ml所能供應的最大容許值Iiim“，是被 控制電路104所控制。由第！圖可推知，電阻產生器1〇42之電阻 Ο 值與控制訊號Sad之電位值是呈一反相關係；而電阻值S 201009529 When a preset value is reached, reduce the conduction level of the power switch. The invention provides a control circuit and an amplifier as described in the preceding paragraph. The discharge A|| is generated according to the 1st feedback voltage and the - reference value, and the control voltage is added, wherein the second feedback voltage represents an output voltage of the voltage stabilizer. 〇 This (4) implementation of woven supply - species (four) green, suitable for - voltage surface device. The voltage regulator contains - power _. The control method comprises the steps of: providing a -variable resistor; generating a reference current representative of a stream flowing through the god paste; causing the reference f stream to flow through the (four) resistor: one of the first fine-grain resistors The feedback voltage; when the _ job-return county system or higher than the preset value, reduce the degree of conduction of the power _; and, change the resistance value of the variable resistor with _ change. ❹ [Embodiment] Some words are used in the specification and subsequent patent applications to refer to 70 pieces of 疋. It should be understood by those of ordinary skill in the art that the hardware manufacturer may use different nouns to refer to the same components. This specification and subsequent applications differ from the patent & name and the name as a means of distinguishing components, but as a criterion for distinguishing between component energies. In the entire specification and subsequent requests = "include" mentioned in Tanaka is an open term, so it should be interpreted as "package S but not limited to". In addition, the term "coupled" is used herein to include any direct and indirect electrical connection means of 201009529. Therefore, if the device is coupled to a second device, it means that the first device can be directly electrically connected to The second device is indirectly electrically connected to the second device via other devices or connection means. Refer to Figure 1 for details. Figure i is a schematic diagram showing an embodiment of a voltage regulator (v〇ltage regulator) according to the present invention. The voltage regulator excitation & includes a voltage stabilization circuit 102 and a control circuit 1〇4, wherein the voltage plane circuit 102 converts the input-to-input voltage into an output voltage Vout. The control circuit 1〇4 prevents the inrush current of the voltage regulator circuit 102. The voltage regulator circuit 1G2 includes an error amplifier (amplifier), a power switch pM〇s transistor (4), and a resistor dust collector 1024. The output capacitor Cout is switched to an output terminal N〇ut, and those skilled in the art should understand that one of the output capacitors C〇ut can stabilize the output voltage Vout of the voltage regulator of the present invention. The voltage regulator circuit 1〇2 its internal circuit connection as shown in the figure © does not have a general knowledge of the industry can be understood, no more. Briefly, the voltage regulator circuit 102 utilizes the negative feedback control provided by the feedback voltage Vfi, and it is desirable to stabilize the output voltage V〇ut at approximately equal to Vout_target (= reference house; where Rx is the resistance of the resistor Rx. The control circuit 104 includes a PMOS transistor M2, a detection circuit 1 〇 44, a control signal generator 嶋, and a resistance generator. The control shunt generator 1046 and the resistor generator 1042 constitute a variable resistance generating unit. 〇s transistor 7 201009529 M2 and the power switch PMOS transistor M1 form a current mirror (curremmirr〇r) for generating an approximately equal ratio reference current lref according to one of the output currents Iout flowing through the power switch PM0S transistor M1. According to the output voltage v〇ut, the slow start time Ts, and the reference voltage Vth1 'the control signal generator 1〇46 generates a control signal Sad' to determine the resistance value of the current resistance generator 〜^ the resistor generator is difficult to include a resistor Ra The resistor Rb and the _3 transistor M3 are connected in series to the resistor Rb, wherein a gate terminal N2 of the NMOS transistor M3 is coupled to the control signal Sad. The detection circuit 1044 has a ratio For example, the comparator detects the reference current (4) and returns the voltage Vf2. When the feedback voltage Vf2 reaches or exceeds a reference voltage Vth2, the detecting circuit 1〇44 changes the power switch PM〇s the transistor M1. The degree of conduction, for example, reduces the conduction level of the PM0S transistor M1 or completely turns off the PM0S transistor M1. Briefly, the control circuit 1〇4 uses negative feedback control, and it is desirable to limit the output current lout to the maximum allowable value lHmit ( = Below the reference voltage 'and the resistance value can change with time. 匕 Fine can give a relatively large value when the ❹ is slowly started '' so Ilimit is relatively small, so as to eliminate the occurrence of rush current; After startup, a relatively small value is given, so - becomes larger to define the maximum current when the normal state is defined. Compared with the voltage regulator circuit 102, the open circuit of the control circuit 1〇4 is wide_〇 1〇〇p band ^her) It can be designed to be relatively large, that is, the reaction catching speed is faster. The control circuit 1〇4 can react faster and quickly prevent the output current from being too high. 2 is the first picture A timing diagram of the reference voltage VtM, the output voltage Vout, and the control signal Sad of the voltage regulator 1 in an embodiment. When the voltage regulator 8 201009529 100 is activated at time T1, the reference voltage is directly applied. Vthi reaches a preset value, and then enters the state of "softstart" (the period of the slow start time Ts; between the gates T1 and T2). During the start time Ts, the output voltage v〇ut is also Not reaching the predetermined value Voutjarget, so the voltage regulator circuit 1〇2 would like to turn on the p=〇s transistor M1 ' to charge the output capacitor c〇ut and pull up the output voltage v(10); but 疋' PMOS transistor Ml at this time The maximum allowable value Iiim "supplied" is controlled by the control circuit 104. By the first! It can be inferred that the resistance Ο of the resistance generator 1 〇 42 is in an inverse relationship with the potential value of the control signal Sad;
Reffect，如同先前所述，則跟輸出電流I〇ut的最大容許值^呈另 一反相關係。換言之’控制訊號Sad的電壓準位越高，電阻值 就越小，最大容許值ilimit越大。因此，第2圖中的控制訊號Sad 便意味著，在一開始進入緩啟動時間Ts時，先給最大容許值 一個比較小的值，如此在對輸出電容C〇ut充電的同時，也消除了 衝擊電流的發生。而在緩啟動時間Ts内，最大容許值慢慢上 Q 升，讓對輸出電容匚〇1^充電之充電電流可以慢慢增加。到離開緩 啟動時間Ts後，最大容許值Ilimit設定為一最大值，來定義正常狀 態時負載所需限制的最大電流。 本發明並不受限於本實施例控制訊號產生器1〇46的逐漸地 提升控制訊號Sad以逐漸地減小可變電阻值R之方法，任何單調 地（monotonically)變化控制訊號Sad之方法均為本發明之範疇所 在。舉例來說’控制訊號產生器1046亦可以階級式地提升控制訊 號Sad以階級式地減小電阻值。控制訊號產生器ι〇46也可 9 201009529 以依據輸出電壓Vout來改變控制訊號Sad。另一方面，熟習此項 技術者在閱讀兀本發明所揭路之實施例後，亦可適當地調整控制 訊號Sad以控制一 PM0S電晶體來改變電阻值t。 時間T2 ’也就是離開緩啟動時間Ts的時間點，可以用各種 不同的方法決定。譬如說’當輸&電壓Vc)Ut;^_達到預定值 Vout—target時’便可以認定為緩啟動時間Ts结束’所以控制訊號 ❹產生器1046將最大容許值W設定為-最大值。舉另一例來說， 控制訊號產生器祕中可具有一計時器，使得控制訊號產生器 腿在_ τι過後的-歡時間後，便自行認定緩啟動時間Ts 結束。在實施例中，緩啟動時間結束可由控制訊號產生器麗 自行判疋’叙Φ其他裝置來欺而告知控觀號產生器藝。 请參考第3圖。第3圖所述係依據本發明一控制方法3〇〇之 -實施顺織。控财法3⑽個來防止―電壓穩壓電路的一 衝擊電流控制方法3⑽將以第丨圖所示之實施例 電壓穩壓器100為例作為說明。另一方面，倘若大體上可達到相 同的結果，本發明之實施例並不需要一定照第3圖所示之流程中 的步驟順序來進行，料3 _示之步驟不—定要連續進行，亦 即其他步驟亦可插人其中。控制方法300包含有： 步驟302 :啟動電壓穩壓電路1〇2 ; 步驟304 .利用電阻產生器1042來提供電阻值Reffect，其職 值為一最大值Rmax; 201009529 步驟306:產生代表流經功率開關PM〇s電晶體M1之輸出電 流lout之參考電流lref ; 步驟308 :隨時間變化減小電阻值; 步驟310:使參考電流Iref流經電阻產生器1〇42的電阻值心^^ 以產生迴授電壓νβ ; 步驟312 :偵測電阻產生器1〇42的上之迴授電壓νβ ; 步驟314 :當偵測到迴授電壓Vf2達到或高於第二參考電壓 ❹ Vth2時’改變功率開關PM〇s電晶體mi之導通 程度；以及 步驟316. g輸出電壓v〇ut達到預定值時，將電 阻值Reffeet §免定為一最小值Rtnijj。 由於電壓穩壓電路102於步驟302被啟動時，其會先進入緩 啟動的狀態。為了防止電壓穩壓電路1〇2於啟動電源時的衝擊電 流現象’控制方法300利用控制電阻產生器1〇42之電阻值心細 〇 來控制輸出電流lout的最大容許值Ilimit。控制方法3〇〇於電源啟 動後會逐漸地減小電阻值心疗⑽，因此最大容許值Iiimu亦會逐漸地 增加。最後，於步驟316中，當輸出電壓v〇ut大約到達到預定值 Vout_target時，便將電阻值心抱“設定為最小值，以使得輸 出電流lout可以容許用較大之最大容許值工來正常地供應一麵 接於電壓穩壓電路102的負載。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範 201009529 做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖係依據本發明電壓穩壓器之一實施例示意圖。 第2圖係第1圖之該電壓穩壓器的一第一參考電壓、一輸出電壓 和一控制訊號之時序圖。 第3圖係依據本發明一控制方法之一實施例流程圖。 【主要元件符號說明】 100 電壓穩壓器 102 電壓穩壓電路 104 控制電路 304、306 曲線 1022 誤差放大器 1024 電阻分壓器 1042 電阻產生器 1044 偵測電路 1046 控制訊號產生器 12Reffect, as previously described, is in another inverse relationship with the maximum allowable value of the output current I〇ut. In other words, the higher the voltage level of the control signal Sad, the smaller the resistance value and the larger the maximum allowable value ilimit. Therefore, the control signal Sad in Fig. 2 means that when the start-up time Ts is initially entered, the maximum allowable value is given a relatively small value, so that the output capacitor C〇ut is charged while being eliminated. The occurrence of inrush current. During the slow start time Ts, the maximum allowable value is slowly increased by Q liters, so that the charging current for charging the output capacitor 匚〇1^ can be gradually increased. After leaving the slow start time Ts, the maximum allowable value Ilimit is set to a maximum value to define the maximum current required for the load in the normal state. The present invention is not limited to the method of gradually increasing the control signal Sad of the control signal generator 1 to 46 to gradually reduce the variable resistance value R, and any method for monotonically changing the control signal Sad All are within the scope of the invention. For example, the control signal generator 1046 can also stepwise increase the control signal Sad to reduce the resistance value in a stepwise manner. The control signal generator ι 46 can also be 9 201009529 to change the control signal Sad according to the output voltage Vout. On the other hand, after reading the embodiment of the invention, the control signal Sad can be appropriately adjusted to control a PM0S transistor to change the resistance value t. The time T2', that is, the time point from which the slow start time Ts is left, can be determined in various ways. For example, when the input & voltage Vc) Ut; ^_ reaches the predetermined value Vout_target, it can be regarded as the end of the slow start time Ts. Therefore, the control signal generator 1046 sets the maximum allowable value W to the maximum value. For another example, the control signal generator may have a timer so that the control signal generator leg determines that the slow start time Ts ends after the _ τι. In the embodiment, the end of the slow start time can be determined by the control signal generator, and the other devices are used to bully and inform the control device. Please refer to Figure 3. Figure 3 is a control method according to the present invention. The control method 3 (10) to prevent the "voltage current control circuit" of the inrush current control method 3 (10) will be described by taking the embodiment of the voltage regulator 100 shown in the figure. On the other hand, if the same result can be substantially achieved, the embodiment of the present invention does not need to be performed in the order of the steps in the flow shown in FIG. 3, and the step of the process is not determined to be continuous. That is, other steps can also be inserted into it. The control method 300 includes: Step 302: Start the voltage stabilization circuit 1〇2; Step 304. Use the resistance generator 1042 to provide the resistance value Reffect, whose value is a maximum value Rmax; 201009529 Step 306: Generate representative flow current a reference current lref of the output current lout of the switch PM〇s transistor M1; Step 308: decreasing the resistance value with time; Step 310: causing the reference current Iref to flow through the resistance value of the resistance generator 1〇42 to generate The feedback voltage νβ is returned; Step 312: Detecting the feedback voltage νβ on the resistance generator 1 〇 42; Step 314: Changing the power switch when detecting that the feedback voltage Vf2 reaches or is higher than the second reference voltage ❹ Vth2 The degree of conduction of the PM〇s transistor mi; and the step 316. g when the output voltage v〇ut reaches a predetermined value, the resistance value Reffeet § is set to a minimum value Rtnijj. Since the voltage regulator circuit 102 is activated in step 302, it will first enter a slow start state. In order to prevent the surge current phenomenon of the voltage regulator circuit 1〇2 when the power is turned on, the control method 300 controls the maximum allowable value Ilimit of the output current lout by the resistance value of the control resistor generator 〇42. Control method 3 gradually reduces the resistance value (10) after the power is turned on, so the maximum allowable value Iiimu also gradually increases. Finally, in step 316, when the output voltage v〇ut reaches a predetermined value Vout_target, the resistance value is "set to a minimum value, so that the output current lout can be allowed to work with a larger maximum allowable value. The load is connected to the load of the voltage regulator circuit 102. The above description is only a preferred embodiment of the present invention, and the equal variation and modification of the patent application model 201009529 according to the present invention are all covered by the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic diagram of an embodiment of a voltage regulator according to the present invention. Fig. 2 is a first reference voltage, an output voltage and a control of the voltage regulator of Fig. 1. The timing diagram of the signal. Fig. 3 is a flow chart of an embodiment of a control method according to the present invention. [Main component symbol description] 100 voltage regulator 102 voltage regulator circuit 104 control circuit 304, 306 curve 1022 error amplifier 1024 resistance Voltage divider 1042 resistance generator 1044 detection circuit 1046 control signal generator 12