JP2011055692A - Switching regulator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the occurrence of overshoots by the fluctuation of an input voltage in a switching regulator. <P>SOLUTION: The switching regulator includes a switching element which converts an input voltage into a pulse voltage; a smoothing means which smoothes the pulse voltage; a first detection means which detects an output voltage; a first control means which controls the switching element by the output voltage detected by the detection means; and a second control means which is provided with a second detection means that detects the switching duty ratio of the switching element and a third detection means that detects the input voltage and which controls the switching element by the switching duty ratio and the input voltage detected by the detection means. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a switching regulator having a function of preventing output voltage overshoot.

Switching regulators are widely used because an arbitrary output voltage can be obtained by the duty ratio of switching pulses (hereinafter referred to as switching duty ratio) for driving the switching elements. In general, a switching regulator tends to cause overshoot when the output voltage is increased. In particular, when the output voltage rises rapidly when the power is turned on, overshoot is likely to occur. For this reason, a switching regulator is generally provided with a soft start circuit or the like, and a method of gradually increasing the output voltage is employed.

Further, a circuit for overcurrent protection or the like is provided on the assumption that the current flowing through the switching element changes or the load applied to the output side changes. In particular, the current flowing through the switching element is detected to protect the switching regulator from destruction or deterioration.

(Conventional embodiment)
FIG. 7 shows the electrical configuration of a conventional switching regulator.

The switching regulator 700 includes a switching element 702, a driver 704, a flip-flop 706, a PWM modulator 708, an error amplifier 709, a soft start circuit 712, a reference voltage source 714, a slope compensation circuit 716, and an oscillator 718. The switching regulator 700 includes an input power source 724, a capacitor 722 and a resistor 720 connected thereto, a reactor 726, a diode 728, a capacitor 730, and resistors RB1 and RB2.

The first control device 710 includes a PWM modulator 708 and an error amplifier 709. The output voltage detection circuit 734 includes resistors RB1 and RB2. The smoothing circuit 732 includes a reactor 726 and a capacitor 730.

When the input voltage Vin is applied to the switching regulator 700 from the power source 724 via the resistor 720, the monitor voltage Vfbi input to the inverting input terminal of the error amplifier 709 is the lower of the reference voltage Vref or the voltage VSS of the soft start circuit 712. Compared with voltage, error is amplified. At startup, the capacitor C20 of the soft start circuit 712 shown in FIG. 8 is not charged, and the soft start voltage VSS of the soft start circuit 712 is at the ground level. Therefore, differential amplification is performed by using the soft start voltage VSS of the soft start circuit 712 lower than the reference voltage Vref as a voltage on the inverting input side of the error amplifier 709.

The soft start circuit 712 includes a capacitor C20, a constant current source CC, and a transistor Q20.

When the input voltage Vin is applied to the switching regulator 700 and the reset pulse VP is input to the transistor Q20 after start-up, the transistor Q20 changes from the on state to the off state, and the charge charged in the capacitor C20 is reset. For this reason, the capacitor C20 starts to be charged from the constant current source CC. The soft start voltage VSS of the soft start circuit 712 gradually increases from 0V in accordance with the electric charge charged in the capacitor C20. The soft start voltage VSS finally reaches the reference voltage Vref over a period of several tens of milliseconds, for example. The length of time for the soft start voltage VSS to reach the reference voltage Vref is set by the capacitance of the capacitor C20 and the current of the constant current source CC.

When the soft start voltage VSS of the soft start circuit 712 gradually rises from 0 V to several tens of milliseconds after starting, the monitor voltage Vfib of the output voltage Vo rises gradually in synchronization with this. If it is activated by the reference voltage Vref, the output voltage Vo is activated from the ground level, so that the switching duty ratio becomes almost the maximum value (for example, 100%).

However, since the switching duty ratio is gradually increased by the soft start circuit 712, it is possible to prevent a current from flowing through the capacitor 730 rapidly. The capacitor 730 smoothes the pulse voltage generated by the switching element 702 and supplies an output voltage Vo corresponding to the electric charge accumulated in the capacitor 730. For this reason, the overshoot of the output voltage Vo is suppressed by preventing the current from flowing suddenly.

When the switching regulator 700 is activated, the output voltage Vo is divided by the resistors RB1 and RB2, and the monitor voltage Vfbi is generated. Since the monitor voltage Vfbi is input to the inverting input terminal of the error amplifier 709, control by negative feedback is performed. When the feedback voltage VFB output from the error amplifier 709 is higher than the slope voltage Vsl of the slope compensation circuit 716, the PWM modulator 708 inputs a reset pulse for turning on the switching element 702 to the reset terminal R of the flip-flop 706. A clock signal is input from the oscillator 718 to the set terminal S of the flip-flop 706. The flip-flop 706 generates a pulse voltage by switching the switching element 702. The pulse voltage flows through a reactor 726 and charges the capacitor 730 to output the pulse voltage as a smooth output voltage Vo.

When the charge amount of the capacitor 730 increases, the output voltage Vo also increases, so that the monitor voltage Vfbi also increases. When the monitor voltage Vfbi exceeds the reference voltage Vref, control for turning off the switching element 702 is performed, so that the output voltage Vo is kept constant. Moreover, there exists a thing of the patent document 1 which the applicant proposed as an example of the conventional switching regulator. This switching regulator includes a soft start circuit, and protects the switching regulator from an overcurrent that occurs when the load with respect to the output voltage fluctuates.

The relationship between the input voltage Vin, the output voltage Vo and the switching duty ratio will be described with reference to FIG.

FIG. 9 is a timing chart showing the relationship among the output voltage Vo, the feedback voltage VFB of the error amplifier 709, the slope voltage Vsl, and the switching pulse SW.

FIG. 9A shows the input voltage Vin input to the switching regulator 700.

FIG. 9B shows the voltage VFB of the error amplifier circuit 709.

FIG. 9C shows the slope voltage Vsl of the slope compensation circuit 716.

FIG. 9D shows the switching pulse signal SW input to the switching element 702. The switching element 702 is turned on when the switching pulse signal SW is high and turned off when the switching pulse signal SW is low.

FIG. 9E shows the output voltage Vo.

FIG. 9F shows the period T. In the period T1, the input voltage Vin drops below the set voltage of the output voltage Vo, and the switching duty ratio becomes almost the maximum value (for example, 100%). In the period T2, the switching duty ratio becomes almost the minimum value (for example, 0%) after the input voltage Vin increases. A period T3 indicates a period after the switching duty ratio becomes almost the minimum value (for example, 0%). A period T4 indicates a steady state. A period T5 indicates a state in which the feedback voltage VFB is high and the switching pulse SW is nearly 100%.

In the period T1, the input voltage Vin is a set value of the output voltage Vo, for example, a voltage lower than 5V, for example, 4V.

For this reason, the monitor voltage Vfbi has a voltage value lower than the reference voltage Vref, and the feedback voltage VFB output from the error amplifier 709 is in a high state. In the PWM modulator 708 to which the feedback voltage VFB is input, the switching duty ratio is set so that the switching element 702 is turned on when the slope voltage Vsl of the slope compensation circuit 716 is lower than the feedback voltage VFB. Therefore, the feedback voltage VFB becomes higher than the slope voltage Vsl output from the slope compensation circuit 716, and the switching element 702 continues to be kept on.

As a result, in the period T1, the output voltage Vo continues to maintain substantially the same value as the input voltage Vin.

JP 2005-323413 A

In the period T2, since the input voltage Vin rises rapidly, the value of the output voltage Vo also rises. When the output voltage Vo rises, the monitor voltage Vfbi also begins to rise. However, even if the monitor voltage Vfbi is input to the inverting input terminal of the error amplifier 709, a certain time is required until the feedback voltage VFB becomes low level.

This is due to the responsiveness of the error amplifier 709. As shown in FIG. 9B, a predetermined time is required until the feedback voltage VFB sufficiently decreases. For this reason, the switching duty ratio does not become the minimum value, for example, 0% until the feedback voltage VFB is completely lowered with respect to the slope voltage Vsl. In particular, in the first half of the period T2, the switching duty ratio keeps substantially the maximum value, and overshoot occurs in the output voltage Vo during this period.

In the period T3, normal control by the monitor voltage Vfbi is performed so that the switching duty ratio reaches almost the minimum value, for example, 0%, and the output voltage Vo becomes the target value, for example, 5V.

In the period T4, the output voltage Vo substantially reaches the set voltage, and the switching duty ratio becomes a steady state. The steady state indicates a state where the switching duty ratio is stable in the vicinity of Vo / Vin, for example, 5V / 12V = about 40%.

As described above, there is a case where the input voltage Vin is not constant and the input voltage Vin drops below the set voltage. Specifically, a power supply circuit used for in-vehicle use steps down the voltage of a battery, for example, 12V, and supplies it to an electronic device such as a meter as 5V, for example. After the power supply is started, the battery voltage temporarily drops below a set voltage, for example 5V, to become 4V, for example, in order to start the engine. In such a case, the output voltage Vo and the input voltage Vin are substantially the same voltage (for example, 4V), and the switching duty ratio is also the maximum value (for example, 100%).

Here, when the start of the engine of the car is finished, the input voltage Vin recovers rapidly, so that the output voltage Vo also increases rapidly. Theoretically, the monitor voltage Vfbi also rises as the output voltage Vo rises, so that the control for turning off the switching element 702 functions, and the rise in the output voltage Vo is suppressed.

However, as described above, the feedback voltage VFB decreases, and a predetermined time is required until the control functions. Therefore, overshoot occurs during this time. Since the input voltage Vin recovers to a normal voltage value (for example, 12V) with the switching duty ratio at the maximum value (for example, 100%) during the time until the control functions, the output voltage Vo increases accordingly. So-called overshoot occurs.

Since the input voltage Vin rises in a state where the input voltage Vin and the output voltage Vo are substantially the same voltage value, the overshoot behaves so that the output voltage Vo is also the same voltage (for example, 12V) as the input voltage Vin. Show. For this reason, a voltage (for example, 12V) exceeding the rating (for example, 5V ± 10%) is applied to an electronic device (not shown) connected to the switching regulator 700. When a voltage (for example, 12V) exceeding a voltage rating (for example, 5V ± 10%) is applied, the electronic device is placed in a defective state.

One of the reasons for such a problem is that the response of the error amplifier 709 is slow and it takes time for the feedback voltage VFB to fall to a low level.

It takes about 0.1 to 1000 μsec for the feedback voltage VFB of the error amplifier 709 to become low level. During this time, the switching element 702 maintains the ON state, so that the input voltage Vin (for example, 12V) and the output voltage Vo are substantially the same voltage (for example, 12V), and so-called overshoot occurs.

An object of the present invention is to provide a switching regulator capable of supplying a stable output voltage by preventing the overshoot of the output voltage Vo due to the fluctuation of the input voltage Vin by suppressing the overshoot.

The switching regulator according to the present invention includes (a) a switching element that converts an input voltage into a pulse voltage, (b) smoothing means that generates an output voltage by depleting the pulse voltage, and (c) a first that detects the output voltage. (D) first detection means for detecting the output voltage, (e) first control means for controlling the switching element by the output voltage detected by the first detection means, and (f) And (g) a first control means including a second detection means for detecting a duty ratio of the switching pulse signal for driving the switching element and a third detection means for detecting the magnitude of the input voltage. The switching regulator drives the switching element by the output signals of the control means and the second control means. According to this configuration, when the duty ratio of the switching pulse signal is in a steady state, control is performed by the output voltage, and the input voltage rapidly increases from a state where the input voltage drops and the switching duty ratio becomes close to the maximum value. It is possible to prevent the occurrence of overshoot due to. Further, in the steady state, the second control means does not work even if an instantaneous change in the input voltage Vin is detected, and malfunction can be prevented.

In another embodiment, the switching regulator is the above-described switching regulator in which the second detection means detects an arbitrary value in which the duty ratio of the switching pulse signal is 50% or more of the maximum value. According to this configuration, since the switching duty ratio is started with the threshold value being 50% or more of the maximum value after the second control means is started, malfunction due to instantaneous fluctuations in the input voltage can be prevented.

In another embodiment, the switching regulator is the switching regulator in which the first control means is controlled by a soft start circuit. According to this configuration, the soft start circuit can be restarted when the second control unit operates.

In another embodiment, the switching regulator is the above-described switching regulator in which the second detection unit detects the output voltage of the first detection unit and detects the duty ratio of the switching pulse signal. According to this configuration, it is possible to determine whether the duty ratio of the switching pulse signal exceeds the threshold by grasping the feedback voltage level.

In another embodiment, the switching regulator is the above switching regulator in which the second control means outputs a logical product signal of the output signal of the second detection means and the output signal of the third detection means. According to this configuration, an appropriate switching pulse signal corresponding to the output voltage can be generated.

In another embodiment, the switching regulator is the switching regulator in which the switching element is driven by a logical sum signal of the output signal of the first control means and the output signal of the second control means. According to this configuration, even when the control by the first control means is performed, the control by the second control means can be made to intervene.

In a switching regulator in another embodiment, the first control means is the switching regulator having an error amplifier and a PWM modulator to which an output voltage of the error amplifier is input. According to this configuration, it is possible to appropriately output the duty ratio of the switching pulse signal for controlling the switching element.

In another embodiment, the switching regulator is the switching regulator described above, in which the output voltage of the error amplifier is input to the second detection means. According to this configuration, it is possible to determine whether the duty ratio of the switching pulse signal exceeds the threshold by grasping the level of the feedback voltage that is the output voltage of the error amplifier.

In a switching regulator in another embodiment, a logical sum signal is input to a reset terminal of a flip-flop, a clock signal is input to the set terminal of the flip-flop, and a switching pulse signal that drives a switching element by the output signal of the flip-flop Is the switching regulator described above. According to this configuration, a feedback loop using flip-flops can be configured and the output voltage can be stabilized.

The switching regulator of the present invention enables control to prevent overshoot without malfunctioning by detecting the feedback voltage and the input voltage. As a result, it is possible to provide a switching regulator having a stable output voltage characteristic that is hardly affected by the input voltage.

1 shows a first embodiment of a switching regulator according to the present invention. 1 shows a timing chart according to a first embodiment of a switching regulator according to the present invention. 1 shows a feedback voltage detection circuit of a switching regulator according to the present invention. 1 shows an input voltage detection circuit of a switching regulator according to the present invention. 2 shows a second embodiment of a switching regulator according to the present invention. 4 shows a timing chart according to a second embodiment of a switching regulator according to the present invention. 1 shows an embodiment of a conventional switching regulator. 1 shows an embodiment of a conventional soft start circuit. The timing chart which concerns on embodiment of the conventional switching regulator is shown.

(First embodiment)
FIG. 1 shows a step-down switching regulator according to a first embodiment of the present invention. The switching regulator 100 includes a switching element 102, a driver 104, a flip-flop 106, a PWM modulator 108, an error amplifier 110, a soft start circuit 112, a reference voltage source 114, a slope compensation circuit 116, an oscillator 118, resistors 120, RB1, RB2, The capacitors 122 and 130, the power supply 124, the reactor 126, the diode 128, and the control device 140 are configured.

When the input voltage Vin is applied from the power supply 124 to the switching regulator 100, the monitor voltage Vfbi input to the inverting input terminal of the error amplifier 109 is the reference voltage and soft start voltage Vsl input to the first and second non-inverting input terminals. The error is amplified by comparing with the lower of the two. The differentially amplified output voltage is output as a feedback voltage VFB. Here, the monitor voltage Vfbi is expressed by the equation (1).
Vfbi = Vo * RB2 / (RB1 + RB2) (1)

As an example of the soft start circuit 112, a soft start circuit 712 shown in FIG. First, since the reset pulse VP is applied to the transistor Q20 of the soft start circuit 112 at the time of startup, the charge of the capacitor C20 is reset, and the soft start voltage VSS of the soft start circuit 112 becomes the ground level. Therefore, the monitor voltage Vfbi is lower than the reference voltage Vref. The soft start voltage VSS of the soft start circuit 112 is compared with the error amplifier 110, and the error amplified output voltage is output to the output terminal of the error amplifier 109.

When the input voltage Vin is applied, charging starts from the constant current source CC to the capacitor C20 of the soft start circuit 112. The soft start voltage VSS supplied from the soft start circuit 112 gradually increases accordingly, and finally reaches the reference voltage Vref. As the soft start voltage VSS of the soft start circuit 112 increases, the switching duty ratio of the switching pulse signal applied to the switching element 112 also gradually increases. This prevents a current from rapidly flowing into the capacitor 130 immediately after startup. By gradually accumulating the electric charge of the capacitor 130, the output voltage Vo of the switching regulator 100 is also gradually increased and the overshoot at the start-up is suppressed.

After the soft start voltage VSS reaches the reference voltage Vref, the output voltage Vo is divided by the resistors RB1 and RB2 to generate the monitor voltage Vfbi. Since the monitor voltage Vfbi is input to the error amplifier 110, control by negative feedback is performed. When the monitor voltage Vfbi is lower than the reference voltage Vref, the feedback voltage VFB output from the error amplifier 109 increases. When the feedback voltage VFB is higher than the slope voltage Vsl from the slope compensation circuit 116, the PWM modulator 108 inputs a reset pulse for turning on the switching element 102 to the reset terminal R of the flip-flop 106. In response to the reset pulse, the flip-flop 106 turns on and off the switching element 102 to generate a pulse voltage.

The pulse voltage is supplied to a reactor 128 and a capacitor 130 which are examples of smoothing means, and energy is supplied to a load connected to an output terminal (not shown). The capacitor 130 functions as a smoothing capacitor that temporarily stores the supplied charge and supplies a voltage corresponding to the charge as the output voltage Vo. In addition, when the load increases while the switching element 102 is off, the energy stored in the reactor 128 is recirculated by the diode 128 and applied to the load. The smoothing means outputs the pulse voltage as a smooth output voltage Vin.

When the output voltage Vo increases, the monitor voltage Vfbi also increases. When the monitor voltage Vfbi exceeds the reference voltage Vref, the feedback voltage VFB decreases, and the output voltage Vo is maintained constant by performing control to turn off the switching element 102.

Here, when the input voltage Vin drops below the set voltage, the output voltage Vo cannot be output beyond the input voltage Vin, and the monitor voltage Vfbi also drops accordingly. In order to bring the output voltage Vo close to the set voltage, the control to turn on the switching element 102 works.

In such a case, the switching duty ratio becomes almost the maximum value (for example, 100%), and the input voltage Vin and the output voltage Vo can be almost the same value (for example, 4V). When the input voltage Vin quickly recovers to a normal voltage value (for example, recovers from 4 V to 12 V), the timing at which the switching element 102 is turned off is delayed due to the delay of the feedback voltage VFB as described above, and an overshoot occurs. To do. However, the switching regulator 100 can be controlled by the control device 140 to prevent the occurrence of the overshoot.

When the VFB detection device 146 detects an increase in the feedback voltage VFB, it is possible to detect that the switching duty ratio of the switching element 102 is at or near the maximum value.

The Vin detection device 148 is a device that detects the rise of the input voltage Vin.

First, the FB detection device 146 detects the level of the feedback voltage VFB, and detects that the switching duty ratio of the switching element 102 is close to the maximum value. When the Vin detection device 148 detects an increase in the input voltage Vin, a signal for turning off the switching element 102 is input from the AND circuit 144 to the OR circuit. The OR circuit inputs a reset pulse for turning off the switching element 102 to the flip-flop 106. As a result, the switching element 102 can be turned off without waiting for the feedback voltage VFB to decrease.

According to such a configuration, the switching element 102 can be turned off regardless of the responsiveness of the error modulator 108, and the occurrence of overshoot is suppressed.

By grasping the switching duty ratio of the switching element 102 by the VFB detection device 146, even if an instantaneous increase in the input voltage Vin is detected when the switching duty ratio is in a steady state (for example, about 40%), no malfunction occurs. Normal control can be maintained. If the switching duty ratio is controlled to the lowest value (for example, 0%) due to malfunction, the output voltage Vo is rated to the lower limit side (for example, 5V ± 10%) depending on the load of the electronic device connected to the switching regulator 100. ) May fall to a voltage lower than (for example, 3 V).

The maximum value of the switching duty ratio described above varies depending on the relationship between the input voltage Vin and the output voltage Vo. The switching duty ratio in the stable state is determined by the ratio (Vo / Vin) between the input voltage Vin and the output voltage Vo. For example, when the input voltage Vin is 12V and the output voltage Vo is 5V, the switching duty ratio is about 40%. Further, when the input voltage Vin is 36V and the output voltage is 5V, the maximum value of the assumed switching duty ratio is different because it is about 15%. Depending on the value of the switching duty ratio in the steady state, a value of 1% can be assumed. Further, although the threshold value for operating the VFB detection circuit is different from the maximum value, the threshold value is preferably 50% or more of the maximum value.

The relationship between the control and the input voltage Vin and the output voltage Vo will be described with reference to FIG.

FIG. 2A shows the input voltage Vin.

FIG. 2B shows the feedback voltage VFB of the error amplification circuit 109.

FIG. 2C shows the output voltage Vsl of the slope compensation circuit 116.

FIG. 2D shows the switching duty ratio SW of the switching pulse signal input to the switching element 102. A high state indicates that the switching element 102 is on, and a low state indicates that the switching element 102 is off.

FIG. 2E shows the output voltage Vo.

FIG. 2F shows the period T. A period T1 indicates a period during which the input voltage Vin is decreasing. A period T2 indicates a period during which the control for suppressing overshoot is functioning after the input voltage Vin increases. A period T3 indicates a period during which control by the feedback voltage VFB is functioning.

In the period T1, the input voltage Vin is a target value of the output voltage Vo, for example, a voltage lower than 5V, for example 4V. Therefore, the monitor voltage Vfbi is lower than the reference voltage Vref, and the voltage VFB output from the error amplifier 109 is in a high state. For this reason, the VFB voltage detection device senses that the duty ratio of the switching pulse signal SW of the switching element 102 has reached a maximum value, for example, 100% from the value of the feedback voltage VFB, and is turned on. At this time, since the Vin detection device 148 does not detect the rising of the input voltage Vin, the AND circuit 144 does not operate because it is in the OFF state. In the PWM modulator 108, when the slope voltage is lower than the feedback voltage VFB, the switching pulse signal SW is set so as to turn on the switching element 102. Therefore, the feedback voltage VFB is higher than the slope voltage Vsl output from the slope compensation circuit 116, and the switching element 102 continues to be kept on (in this case, high).

As a result, in the period T1, the output voltage Vo continues to maintain substantially the same value as the input voltage Vin.

In the period T2, the input voltage Vin rises rapidly. For this reason, the Vin detection circuit 148 detects the rising of the input voltage Vin and is turned on. Since both the VFB detection circuit 146 and the Vin detection circuit 148 are turned on, a reset pulse for turning off the switching element 102 is input from the AND circuit 144 to the OR circuit 142. The OR circuit 142 inputs a reset pulse for turning off the switching element 102 to the reset terminal of the comparator 106. Therefore, the switching element 102 is turned off, energy is not supplied to the capacitor 130, and overshoot when the input voltage Vin rises rapidly is suppressed.

In the period T3, the control by the monitor voltage Vfbi starts to function, and thus the error amplifying device 109 functions by the reference voltage Vref and the monitor voltage Vfbi.

In the period T3 shown in FIG. 2, when the input voltage Vin is instantaneously generated, the Vin detection device 148 is turned on. However, since the feedback voltage VFB is in a steady state, malfunction is prevented. When the above-described control for turning off the switching element 102 is performed when such a voltage change occurs, the output voltage Vo is significantly reduced. However, if the switching duty ratio is in a steady state, for example, 40%, it is difficult to be affected by a momentary drop or increase in the input voltage Vin, so that malfunction in such a case can be prevented.

FIG. 3 shows an example of the VFB detection device 146. The VFB detection device 146 includes a power supply V2, a constant current source CC2, resistors R2, R4, and R6, and transistors Q2, Q4, Q6, and Q8.

The voltage of the power supply V2 is set to 3V, for example. The voltage is divided by the resistors R2 and R4, for example, R2: R4 = 1: 4, and 2.4 V, for example, is applied to the base of the transistor Q6. A voltage that is reduced by, for example, 0.6 V, for example, 1.8 V, which is Vf of the transistor Q6, is applied to the base of the transistor Q2.

In a steady state, the feedback voltage VFB maintains a substantially constant voltage value, for example, 1V. Since the voltage applied to the emitter of the transistor Q02, for example, 1V is lower than the voltage applied to the base, for example, 1.8V, the transistor Q2 is turned off. Therefore, no current flows through the transistor Q4, and no current flows through the transistor Q8 constituting the current mirror circuit. At this time, the output voltage V4 of the VFB detection circuit 146 is the same voltage as the power supply V2, that is, 3V.

In a situation where the switching duty ratio of the switching element 102 is almost the maximum value, for example, 100%, the feedback voltage VFB rises and becomes a base voltage of the transistor Q2, that is, a voltage value higher than 2.4V. Turns on. When the transistor Q2 is turned on, the transistor Q4 is also turned on. At this time, a current also flows through the transistor Q8 constituting the current mirror circuit. As a result, a current flows through the resistor R6, and the output voltage V4 of the VFB detection circuit 146 becomes, for example, 0.7V. If the threshold of the output voltage V4 of the VFB detection circuit 146 is set to ½ of the voltage V2, that is, 1.5V, the output voltage V4 is lower than this threshold at this time. A close value can be detected.

FIG. 4 shows an example of the Vin detection device 148. The Vin detection device 148 includes a power supply V2, resistors R12, R14, and R16, transistors Q12, Q14, and Q16, and a capacitor C12.

In the steady state, since the input voltage Vin is kept constant, the capacitor C12 is charged through the resistor R12. At this time, since there is no potential difference between the base and the emitter of the transistor Q12, the transistor Q12 is off and no current flows. At this time, no current flows through the transistors Q14 and Q16 constituting the current mirror circuit, and the output voltage V14 of the Vin detection circuit 148 shows the same voltage as the voltage V12, for example, 3V.

Even when the input voltage Vin drops, the capacitor C12 is still charged, and the base potential of the transistor Q12 does not fall below the emitter potential. Therefore, no current flows through the transistor Q12, and the output voltage V14 from the Vin detection circuit 148 shows the same voltage as the voltage V12, that is, 3 V, as described above.

When the input voltage Vin increases, the voltage applied to the capacitor C12 increases. In order to charge the capacitor C12, a current flows through the resistor R12. At this time, since the base voltage of the transistor Q12 is lower than the emitter voltage, the transistor Q12 is turned on and current flows. As a result, a current also flows through the transistors Q14 and Q16 constituting the current mirror circuit. The output voltage V14 of the Vin detection circuit 148 is lower than the voltage V12 by the voltage applied to the resistor R16. For this reason, when the output voltage V14 falls below a threshold, for example, 1.5V, an increase in the input voltage Vin can be detected.

The time during which the input voltage Vin is detected is determined by the time for charging the capacitor C12. For this reason, adjustment is possible by changing the capacitance of the capacitor C12 and the resistance values of the resistors R12 to R16. The threshold value for detecting the rising edge of the input voltage Vin can be adjusted by changing the value of the current flowing through the resistor R16 by the current mirror circuit constituted by the transistors Q14 and Q16.

(Second Embodiment)
FIG. 5 shows a step-down switching regulator according to a second embodiment of the present invention. The switching regulator 500 includes a switching element 502, a driver 504, a flip-flop 506, a PWM modulator 508, an error amplifier 509, a soft start circuit 512, a reference voltage Vref, a slope compensation circuit 516, an oscillator 518, resistors 520, RB1, RB2, and a capacitor. 522, 530, a power source 524, a reactor 526, a diode 528, and a control device 540. The control device 540 includes an OR circuit 542, an AND circuit 544, a VFB detection device 545, and a Vin detection device 548. The difference from the first embodiment is that the feedback loop of the control device 540 is connected to the soft start circuit 512. After the control device 540 controls to prevent overshoot, the soft start circuit 512 can be restarted.

The first control device 510 includes a PWM modulator 508 and an error amplifier 509. The second control device 540 includes an AND circuit 544, a VFB detection device 546 that detects that the feedback voltage VFB is equal to or less than a threshold value, and a Vin detection device 548 that detects an increase in the input voltage Vin. The output voltage detection circuit 534 includes resistors RB1 and RB2. The smoothing circuit 532 includes a reactor 526 and a capacitor 530.

First, when the input voltage Vin is applied from the power supply 524, the error amplifier 509 performs differential amplification using the lower one of the reference voltage Vref and the soft start voltage VSS of the soft start circuit 512 as a voltage on the inverting input side. An example of the soft start circuit 512 will be described with reference to the soft start circuit 712 shown in FIG. At start-up, since the reset pulse VP is applied to the transistor Q20 of the soft start circuit 512, the charge of the capacitor C20 is reset, and the soft start voltage VSS of the soft start circuit 512 becomes the ground level. Therefore, differential amplification is performed by using the soft start voltage VSS of the soft start circuit 512 lower than the reference voltage Vref as a voltage on the inverting input side of the error amplification circuit 509.

When the input voltage Vin is applied, charging starts from the constant current source CC to the capacitor C20 of the soft start circuit 512. The voltage VSS supplied from the soft start circuit 512 gradually increases accordingly, and finally reaches the reference voltage Vref. As the soft start voltage VSS of the soft start circuit 512 increases, the switching duty ratio applied to the switching element 512 also gradually increases. This prevents a current from rapidly flowing into the capacitor 530 immediately after startup. By gradually accumulating the electric charge of the capacitor 530, the output voltage Vo of the switching regulator 502 is also gradually increased and the overshoot at the start-up is suppressed.

After the soft start voltage VSS of the soft start circuit 512 reaches the reference voltage Vref, the monitor voltage Vfbi whose output voltage is divided by the resistors RB1 and RB2 is input to the error amplifier 509 and compared with the reference voltage Vref. . When the monitor voltage Vfbi is lower than the reference voltage Vref, a reset pulse corresponding to the feedback voltage VFB output from the error converter 509 in the PWM modulator 508 is input to the flip-flop 506. In response to the reset pulse, the flip-flop 506 turns on the switching element 502 to charge the capacitor 530 through the reactor 526.

Since the output voltage Vo increases gradually as the charge amount increases, the monitor voltage Vfbi also increases gradually. When the monitor voltage Vfbi exceeds the reference voltage Vref, the feedback voltage VFB decreases, and a constant voltage is maintained by performing control for turning off the switching element 502.

Here, when the input voltage Vin drops below the target output voltage value Vo, the monitor voltage Vfbi falls below the reference voltage Vref, so the feedback voltage VFB becomes high. For this reason, the switching duty ratio of the switching element 502 is almost the maximum value, for example, 100%.

When the input voltage Vin rapidly recovers to a normal voltage value in the above state, the above-described overshoot occurs. However, the switching regulator 500 can be controlled by the control device 540 to prevent the occurrence of the overshoot.

The VFB detection device 546 is a device that detects the feedback voltage VFB. By detecting an increase in the feedback voltage VFB, it is possible to detect that the switching duty ratio of the switching element 502 is the maximum value (for example, 100%) or a state close thereto.

The Vin detection device 548 is a device that detects the input voltage Vin. It is possible to detect the rising edge of the input voltage Vin.

First, when the FB detection device 546 detects the level of the feedback voltage VFB, detects that the switching duty ratio of the switching element 502 is close to the maximum value, and the Vin detection device 548 detects an increase in the input voltage Vin. A signal for turning off the switching element 502 is input from the AND circuit 544 to the OR circuit. The OR circuit gives priority to a reset pulse for turning off the switching element 502 and inputs it to the flip-flop 506. As a result, the switching element 502 is turned off, the current flowing through the reactance 526 is cut off, and the occurrence of overshoot is suppressed.

The AND circuit 544 sends a signal for turning off the element 502 by the switching to the soft start circuit 512. As will be described later in detail, the output voltage Vo is raised by the soft start circuit 512 after the switching element 502 is turned off for a certain time, for example, 0.01 to 100 msec.

According to such a configuration, the switching element 502 can be turned off regardless of the response of the error modulator 508, and the occurrence of overshoot is suppressed. It is possible to suppress an overshoot that occurs with an increase in the output voltage Vo such that the output voltage Vo that has been lowered by turning off the switching element 502 recovers, for example, from 0V to a set voltage value, for example, 5V. It is also conceivable to selectively select the control by the soft start circuit 512, the reference voltage Vref or another means according to the level of the lowered output voltage Vo.

The reason why the switching duty ratio of the switching element 502 is grasped by the VFB detection device 546 is that when the control for turning off the switching element 502 is activated due to malfunction, the lower limit side of the electronic device (not shown) connected to the connection 500 is connected to the switching regulator. The voltage is reduced to a voltage (for example, 2V) lower than a rating (for example, 4V), and the electronic device is prevented from being in an inconvenient state. According to this configuration, even when a momentary increase in the input voltage Vin is detected when the switching duty ratio is in a steady state (for example, when the switching duty is about 50%), normal control is maintained without malfunction. Is possible.

The relationship between the control and the input voltage Vin, the output voltage Vo, etc. will be described with reference to FIG.

FIG. 6 is a timing chart showing the relationship among the output voltage Vo, the error amplifier output VFB, the slope voltage Vsl, and the switching duty ratio SW.

FIG. 6A shows the input voltage Vin.

FIG. 6B shows the voltage VFB of the error amplifier circuit 509.

FIG. 6C shows the output of the slope compensation circuit 516.

FIG. 6D shows the switching duty ratio SW. A high state indicates that the switching element 502 is on, and a low state indicates that the switching element 502 is off.

FIG. 6F shows the period T. T1 is a period during which the input voltage Vin is decreasing. T2 is a period during which the control for suppressing the overshoot is functioning after the input voltage Vin increases. T3 is a period during which the control by the feedback voltage VFB is functioning.

In the period T1, the input voltage Vin is, for example, 4V, which is a voltage lower than 5V, for example, as the target value of the output voltage Vo. Therefore, the feedback voltage Vfbi is lower than the reference voltage Vref, and the voltage VFB output from the error amplifier 509 is in a high state. For this reason, the VFB voltage detecting device 546 detects that the switching duty ratio of the switching element 502 has reached a maximum value, for example, 100%, from the value of the feedback voltage VFB, and is turned on. At this time, since the Vin detection device 548 does not detect the rising of the input voltage Vin and is in an OFF state, the AND circuit 544 does not operate. The PWM modulator 508 sets the switching duty ratio so that the switching element 502 is turned on when the slope voltage is lower than the feedback voltage VFB. Therefore, the feedback voltage VFB is higher than the slope voltage Vsl output from the slope compensation circuit 516, and the switching element 502 continues to be kept on (in this case, high).

As a result, in the period T1, the output voltage Vo continues to maintain substantially the same value as the input voltage Vin.

In the period T2, the input voltage Vin rises rapidly. For this reason, the Vin detection circuit 548 detects the rising of the input voltage Vin and is turned on. Since both the VFB detection circuit 546 and the Vin detection circuit 548 are turned on, a reset pulse for turning off the switching element 502 is input from the AND circuit 544 to the OR circuit 542. In the OR circuit 542, a reset pulse for turning off the switching element 502 is input to the comparator 506. For this reason, after starting the control, the switching element 502 is turned off in the period T2, and the output voltage Vo starts to decrease. The control for turning off the switching element 502 is maintained for a period T2 by a timer or the like. When the period T2 is sufficiently long, the output voltage Vo can be set to the same voltage value as that at the time of startup, for example, to 0V.

In the period T3, control by the soft start circuit 512 is performed. Since the reset pulse VP is input to the soft start circuit 512, the charge of the capacitor C20 in the soft start circuit is reset, and the soft start voltage VSS is also at the ground level. Then, charge is supplied from the constant current source CC to the capacitor C20. Since the soft start voltage VSS gradually increases as the capacitor C20 is charged, it is possible to prevent a current from flowing rapidly through the reactor 526 as in the start-up.

In the period T4, the start by the soft start circuit 512 is completed, and a period in a steady state is shown. The monitor voltage Vfbi is fed back to maintain a constant voltage. As described above, when the input voltage Vin changes instantaneously, the Vin detector 548 is turned on. However, since the feedback voltage VFB has a value that makes the switching duty ratio Vo / Vin (for example, 40%), the VFB detection circuit 546 is turned off. For this reason, as described above, the control device 540 is not activated by an instantaneous change in the input voltage Vin, and malfunction can be prevented.

As described above, the switching regulator according to the present invention can suppress overshoot due to fluctuations in the input voltage. In addition, in a steady state in which the switching regulator is operating stably, malfunctions can be prevented even if the input voltage fluctuates, making it possible to operate electronic devices connected to this stably. Become.

Since the present invention can supply a stable voltage even when the input voltage fluctuates, its industrial applicability is extremely high.

100, 500, 700 Switching regulator 102, 502, 702 Switching element 104, 504, 704 Driver 106, 506, 706 Flip-flop 108, 508, 708 PWM modulator 109, 509, 709 Error amplifier 110, 510, 710 First Control device 112,512,712 Soft start circuit 114,124,514,524,714,724 Reference power supply 116,516,716 Slope compensation circuit 118,518,718 Oscillator 120,520,720, RB1, RB2 Resistor 122,130 , 522, 530, 722, 730 Capacitors 126, 526, 726 Reactors 128, 528, 728 Diodes 132, 532, 732 Smoothing circuits 134, 534, 734 Output voltage detection circuits 140, 5 0 second controller 142,542 OR circuit 144,544 the AND circuit 146,546 VFB detector 148,548 Vin detector

Claims (9)

A switching element that converts an input voltage into a pulse voltage, a smoothing unit that generates an output voltage by depleting the pulse voltage, a first detection unit that detects the output voltage, and a first that detects the output voltage Detection means; first control means for controlling the switching element by the output voltage detected by the first detection means; and second detection for detecting a duty ratio of a switching pulse signal for driving the switching element. And a second control means comprising a third detection means for detecting the magnitude of the input voltage, and the switching element is driven by the output signals of the first control means and the second control means. Switching regulator. 2. The switching regulator according to claim 1, wherein the second detection unit detects an arbitrary value in which a duty ratio of the switching pulse signal is 50% or more of a maximum value. The switching regulator according to claim 1, wherein the first control means is controlled by a soft start circuit. The switching regulator according to claim 1, wherein the second detection unit detects an output voltage of the first detection unit and detects a duty ratio of the switching pulse signal. The switching regulator according to claim 1, wherein the second control means outputs a logical product signal of the output signal of the second detection means and the output signal of the third detection means. The switching regulator according to claim 1, wherein the switching element is driven by a logical sum signal of an output signal of the first control means and an output signal of the second control means. The switching regulator according to claim 1, wherein the first control unit includes an error amplifier and a PWM modulator to which an output voltage of the error amplifier is input. The switching regulator according to claim 7, wherein an output voltage of the error amplifier is input to the second detection unit. The logical sum signal is input to a reset terminal of a flip-flop, a clock signal is input to a set terminal of the flip-flop, and a switching pulse signal for driving the switching element is generated by an output signal of the flip-flop. 6. The switching regulator according to 6.

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