201007849 九、發明說明： 【發明所屬之技術領域】 本發明是關於一種製作金氧半導體電晶體的方法，尤指 一種利用選擇性磊晶成長來製作應變矽金氧半導體電晶體 之方法。 【先前技術】 習知的金氧半導體(Metal Oxide Semiconductor，MOS)電 晶體通常包含有一半導體基底、一源極區、一汲極區、一 通道位於源極區和及極區之間、以及一閘極位於通道的上 方。其中，閘極係包含一閘極介電層位於通道上、一閘極 導電層位於閘極介電層上，以及一侧壁子位於閘極導電層 的側壁。一般而言，MOS電晶體在一固定的電場下，流經 通道的驅動電流量會和通道中的載子遷移率成正比。因 此，如何在現有的製程設備中，提升載子遷移率以增加 MOS電晶體之開關速度已成為目前半導體技術領域中之 一大課題。201007849 IX. INSTRUCTIONS: TECHNICAL FIELD The present invention relates to a method of fabricating a MOS transistor, and more particularly to a method of fabricating a strain 矽 MOS transistor using selective epitaxial growth. [Prior Art] A conventional Metal Oxide Semiconductor (MOS) transistor generally includes a semiconductor substrate, a source region, a drain region, a channel between the source region and the polar region, and a The gate is located above the channel. Wherein, the gate electrode comprises a gate dielectric layer on the channel, a gate conductive layer on the gate dielectric layer, and a sidewall spacer on the sidewall of the gate conductive layer. In general, the amount of drive current flowing through a channel of a MOS transistor under a fixed electric field is proportional to the carrier mobility in the channel. Therefore, how to increase the carrier mobility to increase the switching speed of the MOS transistor in the existing process equipment has become a major issue in the field of semiconductor technology.
矽鍺源汲極製程是利用在側壁子形成之後，於鄰接於各 側壁子的半導體基底中分別蟲晶生成—緒化#晶層。其 係利用鍺化矽層的晶格常數與矽不同的特性，使矽磊晶在 石夕基底中產生結構上應變而形成應㈣。由於破錯層的晶 格常數(lattice constant)比矽大，這使得矽的帶結構(MM 6 201007849 structure)發生改變’而造成載子移動性增加，因此可增加 MOS電晶體的開關速度以提高積體電路效能與速度。 需注意的是，習知在利用選擇性蟲晶成長製程來形成蟲 晶層的時候，所長出的磊晶層通常會沿著側壁子的側壁表 面成長而緊貼於側壁子表面。此生長方式在大部分情況下 會對電晶體的通道區域產生應力衰減，而導致所謂的導通 電流衰減(Ion degradation)現象，使整個元件運作不佳。因 此，如何改良目前以選擇性磊晶成長方式來製作應變矽電 晶體即為一重要課題。 【發明内容】 因此本發明之主要目的係提供一種製作金氧半導體電 晶體的方法，以改善上述習知之問題。 本發明提供-種製作金氧半導體電晶體的方法。首先提 供-半導體基底，且半導縣底上财。接著形成 -側壁子於閘極側壁’並形成二凹槽於側壁子兩側之半導 體基底巾。隨後進行―祕刻製程，利_酸等侧溶液 來薄化側壁子，最後再進行—選擇性遙減長以形成蠢晶 層於凹槽中。 另外，本發明提供一種金氧半導體電晶體結構，其包含 201007849 有··一半導體基底*且半導體基底上設有一閘極；一側壁· 子設於該閘極侧壁；以及兩個六角型磊晶層分別位於側壁 子兩侧的半導體基底中。 本發明主要在進行預清洗步驟及選擇性磊晶成長前就 先利用一濕蝕刻製程來薄化部分的側壁子，因此之後沿著 基底晶格結構所長出的磊晶層便不會緊貼著側壁子的側壁 ^ 來成長，而會在成長時與側壁子的側壁產生約50埃至150 〇 埃的間距。根據本發明之較佳實施例，本發明最終會在側 壁子兩側的凹槽中分別形成一約略六角形（hexagonal)的遙 晶層，且藉由蟲晶層與側壁子之間所產生的間隔，本發明 可改善習知製作應變矽電晶體時容易因磊晶層過於貼近側 壁子而造成導通電流衰減的現象。 【實施方式】 ❹ 請參照第1圖至第5圖，第1圖至第5圖為本發明第一 實施例製作一 PMOS電晶體的方法示意圖。如第1圖所示， 首先提供一半導體基底10，例如一矽晶圓（wafer)或一矽覆 絕緣(SOI)基底等，半導體基底10上設有一閘極結構12， 且閘極結構12所在之主動區域(active region)外圍的半導 體基底10内環繞有一淺溝隔離(STI)22。其中，閘極結構 12包含有一閘極介電層14、一位於閘極介電層14上之閘 極16以及一位於閘極16頂部的頂保護層18。閘極介電層 201007849 14可由矽氧化合物或氮氧化合物等絕緣材料所構成，閘極 16是由多晶石夕、金屬石夕化物、金屬等導電材料所構成，而 頂保護層18則是由氮化矽等介電材料所構成。 然後形成一偏位側壁子20於閘極結構12侧壁表面，偏 位側壁子20例如是由氮化矽所構成的，並利用閘極結構 12及偏位側壁子20當作遮罩進行一輕摻雜離子佈植，將P 赢 型摻質植入偏位側壁子20兩側的半導體基底10中，以於 閘極結構12相對兩側分別形成一輕摻雜汲極(LDD)24。隨 後以化學氣相沈積(CVD)再形成一由氮化矽所構成的遮蓋 層36於半導體基底10、偏位側壁子20及閘極結構12表 面。 如第2圖所示，進行一蝕刻製程，以於閘極結構12相 對兩侧的半導體基底10中分別形成一凹槽（recess)26，並 〇 同時去除半導體基底10表面及閘極結構12上的部分遮蓋 層36。在本實施例中，部分遮蓋層36於凹槽26形成後仍 殘留在偏位側壁子20表面，但不侷限於此方法，本發明又 可在蝕刻出凹槽26的時候同時去除遮蓋層36，此皆屬本 發明所涵蓋的範圍。 隨後如第3圖所示，進行一濕蝕刻製程，去除剩餘的遮 蓋層36及偏位側壁子20。根據本較佳實施例，此濕蝕刻 201007849 製程主要是以麟酸(phosphoric acid)做為餘刻溶液，對遮慕 層36及偏位側壁子20進行一大約15秒至30秒的滿蝕刻 製程’以去除遮蓋層36並薄化部分的偏位側壁子2〇，進 而使得薄化後的偏位側壁子20相對於凹槽26向内縮往閘 極結構12，亦即薄化後的偏位側壁子20不鄰接於凹槽26 之侧壁。 Q 接著進行一預清洗(pre-clean)步驟’利用稀釋氫氟酸水 溶液(diluted hydrofluoric acid)或一含有硫酸、過氧化氫、 與去離子水的SPM混合溶液等清洗液來去除凹槽26表面 的原生氧化物或其他不純物質。然後如第4圖所示，進行 一選擇性磊晶成長製程，以於凹槽26中形成一由矽化鍺所 構成的磊晶層28。 _ 值得注意的是，由於本發明在預清洗步驟前就先利用〜 濕蝕刻製程來薄化部分的偏位側壁子20，因此之後於凹槽 26内沿著基底晶格結構所長出的磊晶層28便不會緊貼著 偏位侧壁子20的側壁來成長’反而在成長時會與偏位側璧 子20側壁產生約50埃至15〇埃的間距。根據本發明之 較佳實施例’本發明最終會在偏位側壁子20兩側的凹糟 26中分別形成一約略六角形(hexag〇nal)的磊晶層28。轉由 磊晶層28與偏位側壁子20之間所產生的間隔，本發明可 , 有欵改善習知製作應變矽電晶體時容易因磊晶層過於貼逆 201007849 側壁子而造成導通電流衰減的現象β 接著如第5圖所示，本發明可在磊晶層28形成後依據 製程需求’選擇性在偏位側壁子2G周圍形成—由氧化物及 氮化物所構成主側壁子32，然後再選擇性進行一重摻雜離 子佈植，將P型摻質植入主侧壁子32兩側的半導體基底 10中，以形成一源極/汲極區域34,源極/汲極區域34亦可 ❹在選擇性磊晶成長製程中以同時摻雜(in-situ dope)形成。之 後可再依照製程需求進行一;6夕化金屬（salicide)製程，例如 可先飛鑛或沈積一由銘、鈦、鎳、麵 '把、鉬等所構成的 金屬層（圖未示）在為晶層28上，然後藉由至少一次的快速 升溫退火(rapid thermal anneal, RTP)製程使金屬層與磊晶 層28反應以形成一矽化金屬層（圖未示）。至此即完成本發 明第一實施例的PMOS電晶體。 Ο 另需注意的是’上述製程主要以濕蝕刻製程來薄化偏位 側壁子，但不侷限於這個製作順序，本發明又可選擇在偏 位側壁子形成後，先在偏位側壁子周圍形成主側壁子，接 著利用閘極結構與各側壁子當作蝕刻遮罩形成凹槽，然後 再以濕蝕刻製程薄化或去除主側壁子。換句話說，本發明 可在閘極結構形成後直接在閘極結構侧壁形成偏位側壁子 與主側壁子，然後在主側壁子兩側的半導體基底中蝕刻出 用來形成磊晶層的凹槽。隨後利用磷酸來薄化部分的主側 11 201007849 壁子，並進行一預清洗步驟來去除凹槽表面的殘餘物，最 後再進行一選擇性磊晶成長，以於被薄化之主側壁子兩側 的半導體基底中形成磊晶層。 ❹ ❹ 請參考第6圖至第12圖，第6圖至第12圖為本發明第 二實施例製作一 CM0S電晶體之製程示意圖，其中為彰顯 本發明的特徵並簡化說明，第6圖至第12圖僅顯示出一 PMOS電晶體區與一 NM〇Sf晶體區。如第6圖所示，首 先提供—半導體基底6G，例如―料底或—絕緣層上覆石夕 (SOI)基底等’而半導體基底6〇包含有複數個電晶 數個_電晶體區64、並利用如淺溝隔離 ()等絕緣物加以隔離。淺溝隔離66可由蝕刻半導體 基底6〇之後再填入二氧化石夕所構成。 別^置外於ρ半導體基底60另包含有複數個閘極結構68，分 別设置於pm〇S雷晶贈Ρ 、 c士 2與丽08電晶體區料。其中， =结構68均包含有1極介電層 極介 電層70上之閘極72以及一认 闲極^丨 74。閘極介電層7°可由錢化合:或氮護層 料所構成，閘極72是由多曰 °專絕緣材 材料所構成，而頂保護層7:、：化物、金屬等導電 成。 則疋由亂化石夕等介電材料所構 12 201007849 然後形成一由氮化矽所構成的偏位侧壁子76於PMOS 電晶體區62與NM0S電晶體區64的閘極結構68側壁。 接著形成一圖案化遮罩（圖未示）並覆蓋NMOS電晶體區 64，並利用此圖案化遮罩進行一輕摻雜離子佈植，將P型 摻質植入PMOS電晶體區62之偏位側壁子76兩側的半導 體基底60中，以形成一輕摻雜汲極78。 ©如第7圖所示，先去除NMOS電晶體區64的圖案化遮 罩，然後覆蓋一由氮化碎所構成的遮蓋層（caplayer)80在 PMOS電晶體區62與NMOS電晶體區64的半導體基底60 與閘極結構68表面。接著去除PMOS電晶體區62的部分 遮蓋層80，並使剩餘的的遮蓋層80覆蓋於PMOS電晶體 區62的偏位側壁子76表面，之後利用剩餘在NMOS電晶 體區64的遮蓋層80當作遮罩進行一蝕刻製程，例如一非 等向性乾蝕刻製程，以於PMOS電晶體區62之遮蓋層80 ❿ 兩側的半導體基底60中分別形成一凹槽（recess)82。此外， 亦可省略上述圖案化遮罩（圖未示），而直接以覆蓋在NMOS 電晶體區64的遮蓋層80當作遮罩進行一輕摻雜離子佈植 與凹槽82的蝕刻製程。 接著如第8圖所示，進行一濕蝕刻製程，去除PMOS電 晶體區62的遮蓋層80及部分偏位側壁子76。如同先前所 述之第一實施例，本發明在進行此濕蝕刻製程時主要是以 13 201007849 磷酸(phosphoric acid)做為钱刻溶液’對遮蓋層8〇及偏位側 壁子76進行一大約15秒至30秒的濕#刻製程，以去除遮 蓋層80並薄化部分的偏位側壁子76 ’使得薄化後的偏位 侧壁子76不鄰接於凹槽82之側壁。 接著進行一預清洗(pre-dean)步驟’利用稀釋氫氟酸水 溶液(diluted hydrofluoric acid)或一含有碰^、過氧化氫、 φ 與去離子水的SPM混合溶液等清洗液來去除凹槽82表面 的原生氧化物或其他不純物質。然後如第9圖所示，進行 一選擇性磊晶成長製程，以於凹槽82中形成一由矽錯(SiGe) 所構成的磊晶層84。 如第10圖所示’進行另一触刻製程’例如利用碟酸等 蝕刻溶液來去除NM0S電晶體區64的遮蓋層8〇。 ® 然後如第11圖所示，先覆蓋一圖案化遮罩88在j>M〇s 電晶體區62，利用圖案化遮罩88與NM0S電晶體區的 偏位側壁子86當作遮罩進行一離子佈植，將]s[型推質植入 偏位侧壁子80兩側的半導體基底60中以形成一輕換 極90。 但不侷限於上述作法，本發明又可在去除遮蓋層、 時候同時去除PM0S電晶體區62及NM0S電晶體區6的The bismuth source bungee process is formed by the worm-forming crystal layer in the semiconductor substrate adjacent to each of the sidewalls after the sidewall spacers are formed. The lattice constants of the bismuth telluride layer are different from those of the bismuth layer, so that the bismuth epitaxial crystals are structurally strained in the stellite substrate to form (4). Since the lattice constant of the fault-breaking layer is larger than that of the crucible, which changes the band structure of the crucible (MM 6 201007849 structure) and causes the mobility of the carrier to increase, the switching speed of the MOS transistor can be increased to increase Integrated circuit performance and speed. It should be noted that when a selective insect crystal growth process is used to form a worm layer, the epitaxial layer grown generally grows along the sidewall surface of the sidewall and adheres to the sidewall surface. This growth mode causes stress decay in the channel region of the transistor in most cases, resulting in so-called Ion degradation, which causes the entire device to operate poorly. Therefore, how to improve the current strained germanium crystal by selective epitaxial growth is an important issue. SUMMARY OF THE INVENTION It is therefore a primary object of the present invention to provide a method of fabricating a MOS transistor to improve the above-mentioned problems. The present invention provides a method of fabricating a MOS transistor. First, the semiconductor substrate is provided, and the semi-conducting county is at the bottom. Next, a sidewall is formed on the sidewall of the gate and a semiconductor substrate is formed which is recessed on both sides of the sidewall. Subsequently, a "secret engraving process", a side solution of a sulphuric acid or the like is used to thin the sidewalls, and finally, a selective remote reduction is performed to form a stray layer in the recess. In addition, the present invention provides a metal oxide semiconductor transistor structure comprising 201007849 semiconductor substrate* and a gate on the semiconductor substrate; a sidewall disposed on the sidewall of the gate; and two hexagonal beams The crystal layers are respectively located in the semiconductor substrate on both sides of the sidewall. The present invention mainly utilizes a wet etching process to thin a portion of the sidewalls before performing the pre-cleaning step and selective epitaxial growth, so that the epitaxial layer grown along the lattice structure of the substrate does not closely adhere to The sidewalls of the sidewalls grow to grow, and when grown, create a spacing of about 50 angstroms to 150 angstroms from the sidewalls of the sidewalls. According to a preferred embodiment of the present invention, the present invention finally forms an approximately hexagonal crystal layer in the grooves on both sides of the side wall, and is formed between the crystal layer and the side wall. At the interval, the present invention can improve the phenomenon that the conduction current is easily attenuated due to the fact that the epitaxial layer is too close to the sidewall when the strained germanium transistor is fabricated. [Embodiment] Referring to Figs. 1 to 5, Figs. 1 to 5 are schematic views showing a method of fabricating a PMOS transistor according to a first embodiment of the present invention. As shown in FIG. 1, a semiconductor substrate 10 such as a wafer or a SOI substrate is provided first, and a gate structure 12 is disposed on the semiconductor substrate 10, and the gate structure 12 is disposed. A shallow trench isolation (STI) 22 is surrounded by the semiconductor substrate 10 at the periphery of the active region. The gate structure 12 includes a gate dielectric layer 14, a gate 16 on the gate dielectric layer 14, and a top protection layer 18 on the top of the gate 16. The gate dielectric layer 201007849 14 may be composed of an insulating material such as a silicon oxide compound or a nitrogen oxide compound, and the gate electrode 16 is made of a conductive material such as polycrystalline stone, metal ceramsite, or metal, and the top protective layer 18 is It is composed of a dielectric material such as tantalum nitride. Then, a biasing sidewall 20 is formed on the sidewall surface of the gate structure 12, and the biasing sidewall 20 is formed, for example, of tantalum nitride, and the gate structure 12 and the deflecting sidewall 20 are used as a mask. The lightly doped ion implants are implanted into the semiconductor substrate 10 on both sides of the bias sidewalls 20 to form a lightly doped drain (LDD) 24 on opposite sides of the gate structure 12. A mask layer 36 of tantalum nitride is then formed by chemical vapor deposition (CVD) on the surface of the semiconductor substrate 10, the offset sidewalls 20, and the gate structure 12. As shown in FIG. 2, an etching process is performed to form a recess 26 in the semiconductor substrate 10 on opposite sides of the gate structure 12, and simultaneously remove the surface of the semiconductor substrate 10 and the gate structure 12. Part of the cover layer 36. In this embodiment, the partial cover layer 36 remains on the surface of the offset sidewall 20 after the recess 26 is formed. However, the present invention is not limited to this method, and the present invention can simultaneously remove the cover layer 36 while etching the recess 26. This is within the scope of the present invention. Subsequently, as shown in Fig. 3, a wet etching process is performed to remove the remaining mask layer 36 and the offset sidewalls 20. According to the preferred embodiment, the wet etching 201007849 process mainly uses a phosphoric acid as a residual solution, and the encapsulating layer 36 and the offset sidewall 20 are subjected to a full etching process for about 15 seconds to 30 seconds. 'To remove the mask layer 36 and thin the partial sidewalls 2〇, so that the thinned sidewall spacers 20 are inwardly retracted toward the gate structure 12 with respect to the recess 26, that is, after thinning The sidewall spacers 20 are not adjacent to the sidewalls of the recesses 26. Q is followed by a pre-cleaning step of removing the surface of the recess 26 by using a diluted hydrofluoric acid or a cleaning solution containing sulfuric acid, hydrogen peroxide, and SPM mixed with deionized water. Primary oxide or other impure substance. Then, as shown in Fig. 4, a selective epitaxial growth process is performed to form an epitaxial layer 28 of germanium germanium in the recess 26. _ It is worth noting that since the present invention utilizes a ~wet etching process to thin a portion of the offset sidewalls 20 prior to the pre-cleaning step, the epitaxial grains grown along the underlying lattice structure in the recess 26 are then formed. The layer 28 does not grow close to the sidewall of the deflecting sidewall 20 and instead grows to a distance of about 50 angstroms to 15 angstroms from the sidewall of the deflecting side tweezer 20 when grown. In accordance with a preferred embodiment of the present invention, the present invention ultimately forms an approximately hexagonal epitaxial layer 28 in the recess 26 on either side of the offset sidewall 20, respectively. The spacing between the epitaxial layer 28 and the biased sidewalls 20 is changed. The present invention can improve the conduction current decay due to the fact that the epitaxial layer is too close to the 201007849 sidewall when the strained germanium is fabricated. Phenomenon β. Next, as shown in FIG. 5, the present invention can be formed after the epitaxial layer 28 is formed according to the process requirement 'selectively around the offset sidewall 2G—the main sidewall 32 composed of oxides and nitrides, and then Optionally, a heavily doped ion implantation is performed, and a P-type dopant is implanted into the semiconductor substrate 10 on both sides of the main sidewall 32 to form a source/drain region 34, and the source/drain region 34 is also It can be formed by in-situ dope in a selective epitaxial growth process. Then, according to the process requirements, a 6-salicide process can be used. For example, a metal layer (not shown) composed of Ming, titanium, nickel, surface, and molybdenum can be deposited first. As a layer 28, the metal layer is then reacted with the epitaxial layer 28 by at least one rapid thermal anneal (RTP) process to form a deuterated metal layer (not shown). Thus, the PMOS transistor of the first embodiment of the present invention is completed. Ο It should be noted that the above process mainly uses a wet etching process to thin the eccentric sidewalls, but is not limited to this fabrication sequence. The invention may alternatively select the eccentric sidewalls after the eccentric sidewalls are formed. A main sidewall is formed, and then a trench is formed by using the gate structure and each sidewall as an etch mask, and then the main sidewall is thinned or removed by a wet etching process. In other words, the present invention can form the offset sidewall and the main sidewall directly on the sidewall of the gate structure after the gate structure is formed, and then etch the semiconductor layer on both sides of the main sidewall to form an epitaxial layer. Groove. Phosphoric acid is then used to thin the main side 11 201007849 wall, and a pre-cleaning step is performed to remove the residue on the surface of the groove, and finally a selective epitaxial growth is performed to thin the main sidewall An epitaxial layer is formed in the semiconductor substrate on the side. ❹ ❹ Please refer to FIG. 6 to FIG. 12 , FIG. 6 to FIG. 12 are schematic diagrams showing a process for fabricating a CMOS transistor according to a second embodiment of the present invention, in order to demonstrate the features of the present invention and simplify the description, FIG. 6 to Figure 12 shows only a PMOS transistor region and a NM 〇Sf crystal region. As shown in FIG. 6, first, a semiconductor substrate 6G is provided, for example, a "base or an insulating layer overlying shovel (SOI) substrate, etc." and the semiconductor substrate 6 〇 includes a plurality of electro-crystals - a plurality of electro-crystalline regions 64. And use insulation such as shallow trench isolation () to isolate. The shallow trench isolation 66 can be formed by etching the semiconductor substrate 6 and then filling in the dioxide. The λ semiconductor substrate 60 further includes a plurality of gate structures 68, which are respectively disposed on the pm〇S thunder crystals, cs 2 and 丽08 transistors. Wherein, the structure 68 includes a gate 72 on the 1-pole dielectric layer 70 and a dummy electrode 74. The gate dielectric layer 7° can be composed of a money combination: or a nitrogen sheathing material, and the gate 72 is composed of a plurality of special insulating material, and the top protective layer 7:, a compound, a metal, and the like are electrically formed. Then, a dielectric material such as a chaotic stone is used. 12 201007849 A side wall 76 of a biased sidewall spacer 76 made of tantalum nitride is formed on the sidewalls of the gate structure 68 of the PMOS transistor region 62 and the NMOS transistor region 64. Then, a patterned mask (not shown) is formed and covers the NMOS transistor region 64, and a lightly doped ion implantation is performed by using the patterned mask to implant the P-type dopant into the PMOS transistor region 62. The semiconductor substrate 60 on both sides of the sidewall spacer 76 is formed to form a lightly doped drain 78. As shown in FIG. 7, the patterned mask of the NMOS transistor region 64 is removed first, and then a caplayer 80 composed of nitride is covered in the PMOS transistor region 62 and the NMOS transistor region 64. The semiconductor substrate 60 and the surface of the gate structure 68. The partial mask layer 80 of the PMOS transistor region 62 is then removed, and the remaining mask layer 80 is overlaid on the surface of the offset sidewall spacer 76 of the PMOS transistor region 62, after which the mask layer 80 remaining in the NMOS transistor region 64 is utilized. The mask is subjected to an etching process, such as an anisotropic dry etching process, to form a recess 82 in each of the semiconductor substrates 60 on both sides of the mask layer 80 of the PMOS transistor region 62. In addition, the above-described patterned mask (not shown) may be omitted, and the light-doping ion implantation and the recess 82 may be directly etched by using the mask layer 80 covering the NMOS transistor region 64 as a mask. Next, as shown in Fig. 8, a wet etching process is performed to remove the mask layer 80 and the partially offset sidewall spacer 76 of the PMOS transistor region 62. As in the first embodiment described above, the present invention performs a wet etching process mainly by using 13 201007849 phosphoric acid as a solvent solution to perform a coating on the cover layer 8 偏 and the offset sidewall spacer 76. A wet to etch process of seconds to 30 seconds is performed to remove the cover layer 80 and thin the portion of the offset sidewalls 76' such that the thinned sidewall spacers 76 do not abut the sidewalls of the recess 82. Next, a pre-dean step is performed to remove the groove 82 by using a diluted hydrofluoric acid or a cleaning solution containing a mixture of hydrogen peroxide, hydrogen peroxide, φ and deionized water. Native oxide or other impure substance on the surface. Then, as shown in Fig. 9, a selective epitaxial growth process is performed to form an epitaxial layer 84 composed of false (SiGe) in the recess 82. As shown in Fig. 10, 'another etch process is performed', for example, by using an etching solution such as a dish acid to remove the mask layer 8 of the NMOS transistor region 64. ® then, as shown in Fig. 11, first covering a patterned mask 88 in the j>M〇s transistor region 62, using the patterned mask 88 and the offset sidewalls 86 of the NM0S transistor region as masks. An ion implant is implanted into the semiconductor substrate 60 on both sides of the offset sidewall spacer 80 to form a light-switching pole 90. However, the present invention is not limited to the above, and the invention can simultaneously remove the PMOS transistor region 62 and the NMOS transistor region 6 while removing the mask layer.
A ^ J 201007849 偏位侧壁子76，然後再分別形成另一偏位側壁子86在 PMOS電晶體區62及NMOS電晶體區64的閘極結構68 侧壁。接著可如第11圖所示般形成圖案化遮罩88覆蓋 PMOS電晶體區62並進行N型離子佈植，以於NMOS電 晶體區64的偏位側壁子86兩側形成輕掺雜j：及極9〇，此作 法也屬本發明所涵蓋的範圍。 參 如第12圖所示，先去除圖案化遮罩88，再接著形成一 由氧化物及氣化物所構成的主側壁子(main spacer)92在 PMOS電晶體區62與NMOS電晶體區64的偏位側壁子 76、86周圍。然後形成一圖案化遮罩（圖未示）並覆蓋NM〇s 電晶體區64 ’再進行一離子佈植’將p型摻質植入pM〇s 電晶體區62主侧壁子92兩側的半導體基底60中，以形成 一源極/汲極區域94。接著去除NMOS電晶體區64的圖案 化遮罩，形成另一圖案化遮罩（圖未示）在PM〇S電晶體區 ❹ 62,並進行另一離子佈植製程，將N型摻質植aNm〇s電 晶體區64主側壁子92兩侧的半導體基底60中，以形成一 源極/ >及極區域9 6。 之後可再依照製程需求進行一矽化金屬（salicide)製程 例如可先濺鑛或沈積一由始、鈦、鎳、始、把、銷等所構 成的金屬層（圖未示）在PM0S電晶體區62的磊晶層84上 以及NMOS電晶體區64的源極/沒極區域96上，然後進" 15 201007849 至少一次的快速升溫退火(rapid thermal anneal，RTP)製 程，使金屬層與磊晶層84及矽基底反應以形成一石夕化金屬 層（圖未示）。至此即完成本發明第二實施例製作一 CM〇s 電晶體的方法。 以上所述僅為本發明之較佳實施例，凡依本發明申請 專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範 【圖式簡單說明】 PMOS電晶體 第1圖至第5圖為本發明第一實施例製作一 的方法示意圖。 為本發明第二實施例製作，。S電 ❹ 10 14 18 22 26 30 【主要元件符號說明 半導體基底 閘極介電層 頂保護層 淺溝隔離 凹槽 間距 源極/汲極區域 12 閘極結構 16 閘極 20 偏位侧壁子 24輕摻雜汲極 28 蟲晶層 32 主側璧子 36 遮蓋層 34 201007849 60 半導體基底 62 PMOS電晶體區 64 NMOS電晶體區 66 淺溝隔離 68 閘極結構 70 閘極介電層 72 閘極 74 頂保護層 76 偏位側壁子 78 輕換雜沒極 80 遮蓋層 82 凹槽 84 蠢晶層 86 偏位側壁子 88 圖案化遮罩 90 輕摻雜沒極 92 主側壁子 94 源極/沒極區域 96 源極/汲極區域 ❿ 17A ^ J 201007849 biases the sidewall spacers 76 and then forms the sidewalls of the gate structure 68 of the other PMOS transistor region 62 and the NMOS transistor region 64, respectively. A patterned mask 88 can then be formed to cover the PMOS transistor region 62 and N-type ion implantation as shown in FIG. 11 to form lightly doped j on both sides of the offset sidewalls 86 of the NMOS transistor region 64: And the practice is also within the scope of the present invention. As shown in FIG. 12, the patterned mask 88 is removed first, followed by a main spacer 92 composed of oxides and vapors in the PMOS transistor region 62 and the NMOS transistor region 64. The periphery of the side walls 76, 86 is offset. Then, a patterned mask (not shown) is formed and covers the NM〇s transistor region 64' and then an ion implantation is performed. The p-type dopant is implanted into the pM〇s transistor region 62 on both sides of the main sidewall 92. The semiconductor substrate 60 is formed to form a source/drain region 94. Then, the patterned mask of the NMOS transistor region 64 is removed, another patterned mask (not shown) is formed in the PM〇S transistor region ❹ 62, and another ion implantation process is performed to implant the N-type dopant. The aNm〇s transistor region 64 is in the semiconductor substrate 60 on both sides of the main sidewall 92 to form a source/gt; and a pole region 96. After that, a salicide process can be carried out according to the process requirements, for example, a metal layer (not shown) composed of a first, titanium, nickel, a start, a pin, a pin, etc. can be first sputtered or deposited in the PM0S transistor region. On the epitaxial layer 84 of 62 and on the source/no-polar region 96 of the NMOS transistor region 64, then at least one rapid thermal anneal (RTP) process is performed to make the metal layer and the epitaxial layer Layer 84 and the ruthenium substrate react to form a ruthenium metal layer (not shown). Thus, the method of fabricating a CM〇s transistor of the second embodiment of the present invention is completed. The above is only the preferred embodiment of the present invention, and all the equivalent changes and modifications made by the scope of the present invention should be covered by the present invention. [Illustrated by a simple description] PMOS transistor 1st to the first 5 is a schematic view showing a method of fabricating a first embodiment of the present invention. Made for the second embodiment of the present invention. S ❹ 10 14 18 22 26 30 [Main component symbol description Semiconductor substrate gate dielectric layer top protection layer shallow trench isolation groove pitch source/drain region 12 gate structure 16 gate 20 eccentric sidewall spacer 24 Lightly doped bungee layer 28 worm layer 32 main side tweezer 36 cover layer 34 201007849 60 semiconductor substrate 62 PMOS transistor region 64 NMOS transistor region 66 shallow trench isolation 68 gate structure 70 gate dielectric layer 72 gate 74 Top protective layer 76 Offset sidewalls 78 Light-changing poles 80 Covering layer 82 Grooves 84 Staggered layer 86 Offset sidewalls 88 Patterned masks 90 Lightly doped gates 92 Main sidewalls 94 Source / immersion Area 96 Source/Bungee Area❿ 17