201007753 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種記憶體模組，尤其是一種具有内部電源 的動態隨機存取記憶體作為NAND快閃記憶體的資料快取及暫 存的記憶體模組。 【先前技術】 記憶體分為非揮發性記憶體（Non-Volatile Memory)以及揮 ❹ 發性記憶體（Volatile Memory)。兩者的差別在於儲存於非揮發 性記憶體内的資料不會因為電源的消失而隨著消失，而揮發性 記憶體係指一種當電源關閉後，儲存於内部的資料會消失的記201007753 IX. Description of the Invention: [Technical Field] The present invention relates to a memory module, and more particularly to a dynamic random access memory with internal power supply as data cache and temporary storage of NAND flash memory. Memory module. [Prior Art] The memory is classified into a non-volatile memory (Non-Volatile Memory) and a volatile memory (Volatile Memory). The difference between the two is that the data stored in the non-volatile memory does not disappear with the disappearance of the power supply, and the volatile memory system refers to a memory that disappears after the power is turned off.
I 憶體。 _ 隨機存取記憶體（Random Access Memory，RAM)為揮發性 記憶體，存取速度快，但電源消失後儲存於記憶體内的資料也 會消失。隨機存取記憶體分為靜態隨機存取記憶體（Statie Random Access Memory，SRAM)以及動態隨機存取記憶體 β (Dynamic Random Access Memory，DRAM)。其中靜態隨機存 取記憶體存取速度較快，因此常用在需要高速讀寫的應用，而 動態隨機存取記憶體單位體積的容量較高，因此成本較低。 最早期的非揮發性記憶體係指唯讀記憶體（Read Only Memory，ROM)，是一種只能讀取資料的記憶體，當資料寫入 唯讀記憶體之後無法再更改。可程式化唯讀記憶體 (Programmable Read Only Memory)的内部具有許多錄絲，以供 使用者燒斷寫入所需的程式或資料。可抹除可程式化唯讀記憶 體（Erasable Programmable Read Only Memory，EPROM)為可重 201007753 覆使用的非揮發性記憶體’利用高電壓將資料寫入，需要抹除 (Erase)時則將透明窗内的線路曝光在紫外線下，完成抹除的動 作。電子可抹除可程式化唯讀記憶體（Electrically ErasableI recall. _ Random Access Memory (RAM) is a volatile memory with fast access speed, but the data stored in the memory will disappear after the power is lost. The random access memory is classified into a static random access memory (SRAM) and a dynamic random access memory (DRAM). Among them, the static random access memory has a faster access speed, so it is commonly used in applications requiring high-speed reading and writing, and the dynamic random access memory has a higher capacity per unit volume, so the cost is lower. The earliest non-volatile memory system refers to Read Only Memory (ROM), a memory that can only read data. It cannot be changed after the data is written into the read-only memory. The Programmable Read Only Memory has a lot of internal recordings for the user to burn the programs or data required for writing. Erasable Programmable Read Only Memory (EPROM) is a non-volatile memory that can be used in 201007753. It uses high voltage to write data. If it needs to be erased (Erase), it will be transparent. The line inside the window is exposed to ultraviolet light to complete the erasing action. Electronically erasable programmable read-only memory (Electrically Erasable
Programmable Read Only Memory ’ EEPROM)與可抹除可程式化 唯讀記憶體類似’差別在於電子可抹除可程式化唯讀記憶體以 高壓取代紫外線執行抹除的動作。 目前的非揮發性記憶體則是以快閃記憶體（Flash Memory) 為主流，快閃記憶體是一種以區塊（B1〇ck)為單位執行抹除 # (Erase)動作的記憶體，抹除區塊寫入大量資料比早期電子可抹 除可程式化唯讀記憶體以位元組（Byte)為單位更加快速。快閃 記憶體分為NOR快閃記憶體以及NAND快閃記憶體。NOR快 閃記憶體的抹除寫入時間較慢，但具有完整的定址與資料匯流 < 排，允許隨機存取記憶體的任何區域，因此適合取代早期的唯 讀§己憶體’例如電腦的基本輸入/輸出系統（Basic Input/Output System，BIOS)。相對的，NAND快閃記憶體的抹除寫入時間 較快，但不具有定址匯流排的架構’因此必須以區塊的方式進 Ο 行讀取，加上可抹除次數遠大於NOR快閃記憶體，因此適合 作為儲存裝置之用’例如智慧媒體（Smart Media，SM)、安全數 位卡（Secure Digital，SD)、多媒體卡（MultiMedia Card，MMC)。 NAND快閃記憶體是由複數個區塊所組成，每個區塊又由 複數個大小相同的資料頁（Page)組成，換言之，區塊的容量大 於資料頁的容量。NAND快閃記憶體的特點為抹除時必須以區 塊為單位，而讀取或寫入時則以資料頁為單位。 隨著半導體製程的進步，NAND快閃記憶體每一資料頁的 大小越來越大。目前一般檔案管理系統需透過一快閃解譯層 201007753 (Flash Translation Layer，FTL)存取快閃記憶體，快閃解譯層負 責將一般檔案管理系統要求的邏輯位址與快閃記憶體的實體 位址作一轉換，由於快閃記憶體寫入是以資料頁為單位，抹除 是以區塊為單位，若抹除的區塊内包含有用資料的資料頁時， 必須先將有用資料搬走才能執行區塊抹除的動作，因此當寫入 很多小容量的資料時，容易造成快閃解譯層轉換位址的效率降 低。另外，若寫入的資料量不足一個資料頁的容量卻仍必須以 資料頁為單位寫入時，會造成實際寫入的與系統要求寫入的資 〇 料大小不同，浪費記憶體空間，即所謂的寫入放大（WriteProgrammable Read Only Memory 'EEPROM) is similar to erasable programmable read-only memory. The difference is that electronically erasable programmable read-only memory replaces ultraviolet light with high voltage to perform erase operations. The current non-volatile memory is dominated by flash memory (Flash Memory), which is a memory that erases the # (Erase) action in blocks (B1〇ck). In addition to block writing large amounts of data, it is faster than the early electronic erasable programmable read-only memory in Bytes. Flash memory is divided into NOR flash memory and NAND flash memory. NOR flash memory has a slower erase write time, but has a complete address and data sink & row, allowing random access to any area of the memory, so it is suitable to replace the early read-only § memory such as computer Basic Input/Output System (BIOS). In contrast, the NAND flash memory has a faster erase write time, but does not have the architecture of the address bus. Therefore, it must be read in blocks, plus the erasable number is much larger than the NOR flash. Memory is therefore suitable for storage devices such as Smart Media (SM), Secure Digital (SD), and MultiMedia Card (MMC). The NAND flash memory is composed of a plurality of blocks, each of which is composed of a plurality of pages of the same size, in other words, the capacity of the block is larger than the capacity of the data page. NAND flash memory is characterized by the block area when erasing, and the data page when reading or writing. With the advancement of semiconductor processes, the size of each data page of NAND flash memory is getting larger and larger. At present, the general file management system needs to access the flash memory through a flash translation layer 201007753 (Flash Translation Layer, FTL), and the flash interpretation layer is responsible for the logical address required by the general file management system and the flash memory. The physical address is converted. Since the flash memory is written in units of data pages, the erasure is in units of blocks. If the erased block contains data pages of useful data, the useful data must be used first. The removal of the block can be performed in order to perform the block erase operation, so when writing a lot of small-capacity data, it is easy to cause the efficiency of the flash interpretation layer to convert the address. In addition, if the amount of data written is less than the capacity of one data page, but it must still be written in units of data pages, the actual write size is different from the size of the data required to be written by the system, and the memory space is wasted. So-called write amplification (Write
Amplification);反之，要執行抹除時又要將區塊内有用資料搬 走，但快閃記憶體的區塊抹除次數有一定限制，造成快閃記憶 * 體的壽命降低。 ψ 請參閲第1圖，係繪示習知技術中以動態隨機存取記憶體 102作為NAND快閃記憶體104快取（Cache)之記憶體模組 100。當一外部電子裝置106如電腦或手機，與記憶體模組100 電性連接時，是由外部電子裝置106提供一電源108給動態隨 ❹ 機存取記憶體102,且外部電子裝置106透過一介面110存取 記憶體模組100，故當記憶體模組100與外部電子裝置106未 電性連接時，雖NAND快閃記憶體104内的資料仍存在，但由 於缺乏電源108的供給，造成動態隨機存取記憶體102内的資 料亦隨之消失。 因此需要對上述問題提出一種解決方法。 【發明内容】 本發明之一目的在於提供一種記憶體模組，以供一外部電 201007753 » 子裝置存取，該記憶體模組包括一 NAND快閃記憶體、一動態 隨機存取記憶體單元以及一記憶體控制器。動態隨機存取記憶 體單元電性連接NAND快閃記憶體，具有一動態隨機存取記憶 體，以及一内部電源係電性連接動態隨機存取記憶體，當記憶 體模組與外部電子裝置的電性連接關閉時，内部電源主動提供 電源給動態隨機存取記憶體，使動態隨機存取記憶體内儲存的 資料仍可獲得保留。記憶體控制器用於控制NAND快閃記憶體 及動態隨機存取記憶體單元兩者的至少其中之一。 _ 本發明之另一目的在於提供一種記憶體模組，以供一外部 電子裝置存取，該記憶體模組包括一資料傳輸介面、一動態隨 機存取記憶體單元、一 NAND快閃記憶體以及一記憶體控制 器。動態隨機存取記憶體單元經由資料傳輸介面連接外部電子 裝置並暫存或快取在外部電子裝置與記憶體模組之間傳送的 資料。NAND快閃記憶體係供外部電子裝置存取。記憶體控制 器具有一流量控制單元用於控制NAND快閃記憶體及動態隨機 存取記憶體單元之間傳送的特定資料量大小。 籲 本發明之又一目的在於提供一種記憶體模組的執行方 法，以供一外部電子裝置存取，且該記憶體模組具有一動態隨 機存取記憶體單元、一 NAND快閃記憶體及一記憶體控制器， 該方法包括下列步驟：藉由動態隨機存取記憶體單元之快取及 暫存功能’使外部電子裝置存取NAND快閃記憶體；以及利用 記憶體控制器控制NAND快閃記憶體及動態隨機存取記憶體單 元之間傳送的特定資料量大小β 本發明之又一目的在於提供一種記憶體模組的執行方 法，以供一外部電子裝置存取，且該記憶體模組具有一動態隨 201007753 機存取記憶體、一 NAND快閃記憶體及一記憶體控制器，該方 法包括下列步驟：當記憶體模組與外部電子裝置的一外部電源 的電性連接關閉時，主動提供一内部電源電性連接動態隨機存 取記憶體，使動態隨機存取記憶體單元内儲存的資料仍可保 留，即將動態隨機存取記憶體當作一非揮發性動態隨機存取記 憶體使用；以及當内部電源與動態隨機存取記憶體的電性連接 關閉時，則將動態隨機存取記憶體當作一揮發性動態隨機存取 記憶體使用。 〇 本發明之記憶體模組中的動態隨機存取記憶體單元具有 内部電源，當記憶體模組未與外部電子裝置電性連接時，由内 部電源提供電源給動態隨機存取記憶體，使儲存於動態隨機存 取記憶體内的資料不會消失。再者，當外部電子裝置將資料寫 入記憶體模組之NAND快閃記憶體時，記憶體控制器會控制動 態隨機存取記憶體的資料會先累積到一定程度時，再寫入 NAND快閃記憶體，減少NAND快閃記憶體抹除及寫入動作的 次數，因此延長NAND快閃記憶體的使用壽命。 9 【實施方式】 請參閱第2圖，係繪示依據本發明之一較佳實施例的記憶 體模組200的示意圖，且該記憶體模組200可供一外部電子裝 置206進行資料存取，該外部電子裝置206可為如電腦、手機、 個人數位助理（Personal Digital Assistant，PDA)等等。記憶體模 組200包括一基板212、一資料傳輸介面210、一 NAND快閃 記憶體204、一動態隨機存取記憶體單元201以及一記憶體控 制器220。其中NAND快閃記憶體204、動態隨機存取記憶體 201007753 單元201以及記憶體控制器220可設置於基板212上。 該記憶體模組200係經由該資料傳輸介面210電性連接外 部電子裝置206，除了用於中介動態隨機存取記憶體單元202 與外部電子裝置206之間的資料傳輸外，亦利用外部電子裝置 206之一電源208提供一外部電源給動態隨機存取記憶體單元 201。 該動態隨機存取記憶體單元2 01電性連接N AND快閃記憶 體204,且具有一動態隨機存取記憶體202以及一内部電源203 Φ 與動態隨機存取記憶體202電性連接，所以當記憶體模組200 與外部電子裝置206之間的電性連接關閉如記憶體模組200自 外部電子裝置206上卸除而導致外部電源的供應中斷時，内部 電源203可主動提供電源給動態隨機存取記憶體202，使動態 隨機存取記憶體202内儲存的資料仍可獲得保留。在本實施例 中，内部電源203可為一電池，且當記憶體模組200電性連接 外部電子裝置206時，電池透過外部電子裝置206所提供的一 電源208充電。 φ 記憶體控制器220用於控制NAND快閃記憶體204及動態 隨機存取記憶體單元201兩者的至少其中之一，其主要包括一 流量控制單元222，用於依據動態隨機存取記憶體202内暫存 的資料量是否已累積到一預設的資料量大小來決定NAND快閃 記憶體204及動態隨機存取記憶體單元201之間傳送的特定資 料量大小（待後詳述），其中流量控制單元222可為一硬體或軟 體。舉例而言，當外部電子裝置206欲經由該資料傳輸介面210 將資料寫入該記憶體模組200之NAND快閃記憶體204中時， 利用記憶體控制器220之流量控制單元222的控制，先將寫入 201007753 的資料暫存於動態隨機存取記憶體202内，並判斷動態隨機存 取記憶體202内暫存的資料量是否已累積到一預設的資料量大 小如資料量累積至相當於NAND快閃記憶體204之一資料頁的 資料容量大小時，才將暫存資料一次寫入NAND快閃記憶體 204中，藉此可控制NAND快閃記憶體204與動態隨機存取記 憶體單元201之間傳送的特定資料量大小，故無需每次有一點 資料就立即寫入NAND快閃記憶體204中。如NAND快閃記憶 體204之中一個資料頁的大小為4096個位元組（4K Bytes)時， Ο 外部電子裝置206要寫入NAND快閃記憶體204的資料大小在 未到達4096個位元組的預設資料量之前，皆會先在動態隨機 存取記憶體202内暫存直至累積到相當於4096個位元組的預 設資料量時，再一次寫入NAND快閃記憶體204中，亦即以動 態隨機存取記憶體202作為NAND快閃記憶體204的快取及暫 存記憶體。 第3圖係繪示本發明之一實施例的記憶體模組的執行方法 之步驟流程圖。首先如狀態S10，即當一外部電子裝置與記憶 _ 體模組電性連接後記憶體模組的初始狀態，其中由外部電子裝 置提供外部電源給動態隨機存取記憶體（亦可同時對記憶體模 組的電池充電或否）。狀態S20，當外部電子裝置欲讀取NAND 快閃記憶體内的資料時，會先將NAND快閃記憶體内的資料傳 送至動態隨機存取記憶體，再進入狀態S30，即動態隨機存取 記憶體内的資料透過資料傳輸介面傳送至外部電子裝置。若讀 取的資料龐大，則在狀態S20及S30中循環，直到NAND快閃 記憶體内被要求的所有資料經由動態隨機存取記憶體、資料傳 輸介面傳送至外部電子裝置為止，因此該NAND快閃記憶體是 201007753 將動態隨機存取記憶體當作一資料的快取記憶體來使用。當外 部電子裝置關機後，如狀態S40所示，則由内部電源（即電池） 主動提供電源予動態隨機存取記憶體，將動態隨機存取記憶體 作為一非揮發性動態隨機存取記憶體使用；反之當電池電量不 足，則將動態隨機存取記憶體視為一揮發性動態隨機存取記憶 體使用。 在另一情況下，當外部電子裝置欲將資料寫入NAND快閃 記憶體中時，利用記憶體控制器之流量控制單元的控制，則先 © 將寫入的資料暫存於動態隨機存取記憶體中，再將資料寫入 NAND快閃記憶體中。若寫入的資料量龐大，則在狀態S70及 S60中循環，外部電子裝置透過介面將資料傳送至動態隨機存 取記憶體，再利用記憶體控制器之流量控制單元將動態隨機存 取記憶體内暫存的寫入資料量累積到一預設的資料量大小後 如相當於NAND快閃記憶體一個資料頁的資料容量大小，再一 次寫入NAND快閃記憶體内。從狀態S10欲寫入資料至NAND 快閃記憶體時，亦是如上所述，在狀態S70及S60中循環，直 〇 至資料寫入完成為止。因此，該NAND快閃記憶體亦是將動態 隨機存取記憶體當作一資料的暫存記憶體來使用。 本發明之記憶體模組中的動態隨機存取記憶體單元具有 内部電源，當記憶體模組未與外部電子裝置電性連接時，由内 部電源提供電源給動態隨機存取記憶體，使儲存於動態隨機存 取記憶體内的資料不會消失。再者，當外部電子裝置將資料寫 入記憶體模組之NAND快閃記憶體時，動態隨機存取記憶體的 資料會先累積到一定程度時，再寫入NAND快閃記憶體，減少 NAND快閃記憶體抹除及寫入動作的次數，因此延長NAND快 12 201007753 閃記憶體的使用壽命。 综上所述，本發明符合發明專利要件，爰依法提出專利申 請。惟以上所述者僅為本發明之較佳實施例，舉凡熟悉此項技 藝之人士，在爰依本發明精神架構下所做之等效修飾或變化， 皆應包含於以下之申請專利範圍内。 【圖式簡單說明】 第1圖係繪示習知技術中以動態隨機存取記憶體作為 〇 NAND快閃記憶體快取之記憶體模組； 第2圖係繪示依據本發明之一較佳實施例的記憶體模組的 不意圖，以及 第3圖係繪示本發明之一實施例的記憶體模組的執行方法 之步驟流程圖。 【主要元件符號說明】 100 ' 200 記憶體模組 102 、 202 動態隨機存取記憶體 104 、 204 NAND快閃記憶體 106 ' 206 外部電子裝置 108 ' 208 電源 110 、 210 資料傳輸介面 201 動態隨機存取記憶體單元 203 内部電源 212 基板 220 記憶體控制器 13 201007753 222 流量控制單元 S10-S70 狀態Amplification); conversely, when the erase is performed, the useful data in the block is removed, but the number of block erases of the flash memory is limited, resulting in a decrease in the life of the flash memory. ψ Referring to FIG. 1 , a memory module 100 in which the DRAM 102 is used as the NAND flash memory Cache is used in the prior art. When an external electronic device 106, such as a computer or a mobile phone, is electrically connected to the memory module 100, the external electronic device 106 provides a power source 108 to the dynamic memory device 102, and the external electronic device 106 transmits the memory 102. The interface 110 accesses the memory module 100. Therefore, when the memory module 100 and the external electronic device 106 are not electrically connected, although the data in the NAND flash memory 104 still exists, the supply of the power source 108 is lacking. The data in the DRAM 102 also disappears. Therefore, it is necessary to propose a solution to the above problems. SUMMARY OF THE INVENTION An object of the present invention is to provide a memory module for accessing an external device 201007753 » sub-device, the memory module including a NAND flash memory, a dynamic random access memory unit And a memory controller. The DRAM memory unit is electrically connected to the NAND flash memory, has a dynamic random access memory, and an internal power supply is electrically connected to the dynamic random access memory, when the memory module and the external electronic device When the electrical connection is closed, the internal power supply actively supplies power to the dynamic random access memory, so that the data stored in the dynamic random access memory can still be retained. The memory controller is for controlling at least one of the NAND flash memory and the dynamic random access memory unit. Another object of the present invention is to provide a memory module for access by an external electronic device, the memory module including a data transmission interface, a dynamic random access memory unit, and a NAND flash memory. And a memory controller. The DRAM memory unit connects the external electronic device via the data transmission interface and temporarily stores or caches the data transmitted between the external electronic device and the memory module. The NAND flash memory system is accessible to external electronic devices. The memory controller has a flow control unit for controlling the amount of specific data transferred between the NAND flash memory and the DRAM unit. Another object of the present invention is to provide a method for executing a memory module for access by an external electronic device, and the memory module has a dynamic random access memory unit, a NAND flash memory, and A memory controller, the method comprising the steps of: enabling an external electronic device to access a NAND flash memory by a cache and temporary storage function of a dynamic random access memory cell; and controlling the NAND fast by using a memory controller A specific amount of data transferred between the flash memory and the dynamic random access memory unit. A further object of the present invention is to provide a method for executing a memory module for access by an external electronic device, and the memory The module has a dynamic memory access memory, a NAND flash memory, and a memory controller. The method includes the following steps: when the memory module is electrically connected to an external power source of the external electronic device. Actively providing an internal power source electrically connected to the dynamic random access memory, so that the data stored in the dynamic random access memory unit can still be retained. The dynamic random access memory is used as a non-volatile dynamic random access memory; and when the internal connection between the internal power supply and the dynamic random access memory is turned off, the dynamic random access memory is regarded as a Volatile DRAM memory usage. The dynamic random access memory unit in the memory module of the present invention has an internal power supply. When the memory module is not electrically connected to an external electronic device, the internal power source supplies power to the dynamic random access memory. Data stored in dynamic random access memory does not disappear. Moreover, when the external electronic device writes the data into the NAND flash memory of the memory module, the memory controller controls the data of the dynamic random access memory to first accumulate to a certain extent, and then writes to the NAND fast. Flash memory reduces the number of NAND flash erase and write operations, thus extending the life of NAND flash memory. [Embodiment] Please refer to FIG. 2, which is a schematic diagram of a memory module 200 according to a preferred embodiment of the present invention, and the memory module 200 can be used for data access by an external electronic device 206. The external electronic device 206 can be, for example, a computer, a mobile phone, a Personal Digital Assistant (PDA), or the like. The memory model set 200 includes a substrate 212, a data transfer interface 210, a NAND flash memory 204, a dynamic random access memory unit 201, and a memory controller 220. The NAND flash memory 204, the dynamic random access memory 201007753 unit 201, and the memory controller 220 may be disposed on the substrate 212. The memory module 200 is electrically connected to the external electronic device 206 via the data transmission interface 210. In addition to mediating data transmission between the DRAM memory unit 202 and the external electronic device 206, the external electronic device is also utilized. One of the power supplies 208 provides an external power source to the dynamic random access memory unit 201. The dynamic random access memory unit 211 is electrically connected to the N AND flash memory 204, and has a dynamic random access memory 202 and an internal power supply 203 Φ electrically connected to the dynamic random access memory 202. When the electrical connection between the memory module 200 and the external electronic device 206 is turned off, and the memory module 200 is removed from the external electronic device 206, the internal power supply 203 can actively provide power to the dynamics. The random access memory 202 allows the data stored in the dynamic random access memory 202 to remain retained. In this embodiment, the internal power source 203 can be a battery, and when the memory module 200 is electrically connected to the external electronic device 206, the battery is charged by a power source 208 provided by the external electronic device 206. The φ memory controller 220 is configured to control at least one of the NAND flash memory 204 and the dynamic random access memory unit 201, and mainly includes a flow control unit 222 for using the dynamic random access memory. Whether the amount of data temporarily stored in 202 has accumulated to a predetermined amount of data determines the amount of specific data transferred between the NAND flash memory 204 and the DRAM unit 201 (to be detailed later). The flow control unit 222 can be a hardware or a soft body. For example, when the external electronic device 206 wants to write data into the NAND flash memory 204 of the memory module 200 via the data transmission interface 210, the control of the flow control unit 222 of the memory controller 220 is used. The data written in 201007753 is temporarily stored in the dynamic random access memory 202, and it is determined whether the amount of data temporarily stored in the dynamic random access memory 202 has accumulated to a predetermined amount of data. When the data capacity of one of the data pages of the NAND flash memory 204 is equivalent, the temporary data is once written into the NAND flash memory 204, thereby controlling the NAND flash memory 204 and the dynamic random access memory. The amount of specific data transferred between the volume units 201 is such that it does not need to be written into the NAND flash memory 204 immediately with a little bit of data. For example, when the size of a data page in the NAND flash memory 204 is 4096 bytes (4K Bytes), the data size of the external electronic device 206 to be written into the NAND flash memory 204 does not reach 4096 bits. Before the preset data amount of the group, the data is temporarily stored in the DRAM 202 until the preset amount of data corresponding to 4096 bytes is accumulated, and then written into the NAND flash memory 204 again. That is, the dynamic random access memory 202 is used as the cache and temporary memory of the NAND flash memory 204. Figure 3 is a flow chart showing the steps of a method for executing a memory module in accordance with an embodiment of the present invention. First, if the state is S10, that is, when an external electronic device is electrically connected to the memory module, the initial state of the memory module is provided, wherein the external electronic device provides external power to the dynamic random access memory (also can simultaneously remember The battery of the body module is charged or not). In the state S20, when the external electronic device wants to read the data in the NAND flash memory, the data in the NAND flash memory is first transferred to the dynamic random access memory, and then enters the state S30, that is, the dynamic random access. The data in the memory is transmitted to the external electronic device through the data transmission interface. If the read data is large, it circulates in states S20 and S30 until all the data requested in the NAND flash memory is transmitted to the external electronic device via the dynamic random access memory and the data transmission interface, so the NAND is fast. Flash memory is 201007753. Use dynamic random access memory as a data cache. After the external electronic device is turned off, as shown in state S40, the internal power source (ie, the battery) actively supplies power to the dynamic random access memory, and the dynamic random access memory is used as a non-volatile dynamic random access memory. Use; otherwise, when the battery is low, the DRAM is treated as a volatile DRAM. In another case, when the external electronic device wants to write the data into the NAND flash memory, the control of the flow control unit of the memory controller is used to temporarily store the written data in the dynamic random access. In the memory, the data is written into the NAND flash memory. If the amount of data written is large, it circulates in states S70 and S60, and the external electronic device transmits the data to the dynamic random access memory through the interface, and then uses the flow control unit of the memory controller to move the dynamic random access memory. The amount of data temporarily stored in the temporary storage is accumulated to a predetermined amount of data, and is equivalent to the data capacity of a data page of the NAND flash memory, and is once again written into the NAND flash memory. When the data is to be written from the state S10 to the NAND flash memory, as described above, the loops are repeated in the states S70 and S60 until the data writing is completed. Therefore, the NAND flash memory is also used as a temporary memory of a data random access memory. The dynamic random access memory unit in the memory module of the present invention has an internal power supply. When the memory module is not electrically connected to the external electronic device, the internal power source supplies power to the dynamic random access memory for storage. Data in dynamic random access memory does not disappear. Moreover, when the external electronic device writes the data into the NAND flash memory of the memory module, the data of the dynamic random access memory first accumulates to a certain extent, and then writes to the NAND flash memory to reduce the NAND. The number of flash erase and write operations, thus extending the lifetime of NAND flash memory. In summary, the present invention complies with the requirements of the invention patent, and proposes a patent application according to law. The above is only the preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art in accordance with the spirit of the present invention are included in the following claims. . BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing a memory module in which a dynamic random access memory is used as a NAND flash memory cache in the prior art; FIG. 2 is a diagram showing a comparison according to the present invention. The non-intention of the memory module of the preferred embodiment, and FIG. 3 is a flow chart showing the steps of the method for executing the memory module according to an embodiment of the present invention. [Main component symbol description] 100 '200 memory module 102, 202 dynamic random access memory 104, 204 NAND flash memory 106' 206 external electronic device 108' 208 power supply 110, 210 data transmission interface 201 dynamic random storage Memory unit 203 internal power supply 212 substrate 220 memory controller 13 201007753 222 flow control unit S10-S70 status