201005877 nji^-^uu〇-0020 27923twf.doc/n 九、發明說明： 【發明所屬之技術領域】 本發明是有關於-種積體電路的結構及其 法’且特別是«於-_連_結構及其製造方法。 【先前技術】 隨著半導體製造技術的持續進步，元件線寬得以 縮小。而線寬義小财助於高速、^力能、高元件2 度、低功率雜及低成本之極大型賴電路晶 二 生產製造。 人里 由於半導體元件之微型化及積集度的增加，使得有限 的晶片表面無法容納日益增加的内連線 (interconnection)。為了解決此項問題，多重金屬内連線 結構便被提出，而成為積體電路製造技術不得不採用的方 式。一般積體電路所使用的多重金屬内連線結構由金屬導 線與介層窗或接觸窗構成。内連線結構配置在多層介電層 之中，由形成在介層窗開口或接觸窗開口中的鎢插塞連接 各層平面的金屬導線或半導體元件。 以一個介層窗鎢插塞為例，圖1A至圖1B為繪示習知 的一種金屬内連線結構之刮面圖。參照圖1A，基底1〇〇 上已形成有金屬導線120以及覆蓋金屬導線120的介電層 140。之後，藉由圖案化方法在介電層14〇中形成開口，並 在開口内形成鎢插塞150。接著，於介電層14〇上沈積阻 障材料層與金屬材料層，並於金屬材料層上形成圖案化光 5 201005877 nsu-zwis-0020 27923twf.doc/n p且層广以圖案化光阻層170為罩幕，姓刻金屬材料層 與阻障材料層’以形成金屬導線⑽與 幻。 之後，請參照圖1B，以氡雷黎t 乂乳冤漿灰化（ashing)移除圖 帛化光_ 17G。—般而言，在進行勤m程之後，會進 打清洗製程，以去除表面殘留的微粒或雜質，避免對後續 製程造成不良影響。但是，若微影製程發生錯誤對準 (m1S_alignment)或其他原目，導致圖案並未對準鶴插塞 ❹ 150的上方時（如圖1A所示），就會在後續清洗製程中發 生鶴腐躺問題。詳言之，由於金屬導線16〇與阻障層162 無法將鶴減150完全覆蓋’被裸露出來的鋪塞15〇會 與用於清洗製程的溶劑發生反應，導致嫣插塞15〇流失而 形成孔洞158 ’如圖1B所示。由於遭到腐㈣鶴插塞15〇 /、上下層金屬‘線120、16〇的接觸面積減小，使得迴路的 阻值增加’會造成電路元件功能異常。甚者，整個鶴插塞 150都被淘空而形成斷路，導致電路元件失效。 _除了微影製程發生錯誤對準時會引起鎢插塞腐蝕，當 几件的線寬縮小時，導線層有時並不會完全對準其下方的 鎢插塞’財縮小設計面積，㈣鎢插塞雜將無可避免， 而解決上述問題的必要性也就大大提升。 【發明内容】 本發明提供一種内連線的製造方法，可以避免導體層 被腐姓。 本發明另提供一種内連線結構，能有效保護位於阻障 6 201005877 χυυ-·〇-0020 27923twf.doc/n 層下方的插塞。 本發明提出-種内連線的製造方法。先提供基底，再 於基底上形成具有開口之第一介電層。接著，於開口中形 成導體層，並使導體層的頂面高度低於第—介電層的頂面 向度。之後，於第一介電層及導體層上形成第一阻障層， 再於第-阻障層上形成金屬層。接著，圖案化金屬層^ —阻障層。201005877 nji^-^uu〇-0020 27923twf.doc/n IX. Description of the invention: [Technical field of invention] The present invention relates to the structure of an integrated circuit and its method 'and in particular «于-_连_ Structure and its manufacturing method. [Prior Art] As the semiconductor manufacturing technology continues to advance, the component line width is reduced. The line width and small wealth help the production of high-speed, high-power, high-component 2 degrees, low-power hybrid and low-cost. Due to the miniaturization and accumulation of semiconductor components, the limited wafer surface cannot accommodate an increasing number of interconnects. In order to solve this problem, a multi-metal interconnect structure has been proposed, which has become a method that the integrated circuit manufacturing technology has to adopt. The multi-metal interconnect structure used in a general integrated circuit is composed of a metal wire and a via or a contact window. The interconnect structure is disposed in the multilayer dielectric layer, and the metal wires or semiconductor elements of the respective layers are connected by tungsten plugs formed in the via openings or contact openings. Taking a via tungsten plug as an example, Figs. 1A to 1B are plan views showing a conventional metal interconnect structure. Referring to Fig. 1A, a metal wire 120 and a dielectric layer 140 covering the metal wire 120 have been formed on the substrate 1''. Thereafter, an opening is formed in the dielectric layer 14A by a patterning method, and a tungsten plug 150 is formed in the opening. Then, a barrier material layer and a metal material layer are deposited on the dielectric layer 14 and a patterned light is formed on the metal material layer. The layer is patterned to form a photoresist layer. 170 is a mask, and the layer of metal material and the layer of barrier material are engraved to form metal wires (10) and illusion. After that, please refer to Figure 1B, and remove the _ 17g from the ashing 氡 ash ash ashing. In general, after the process, the cleaning process will be carried out to remove any residual particles or impurities on the surface to avoid adverse effects on subsequent processes. However, if the lithography process misaligns (m1S_alignment) or other originals, causing the pattern not to be aligned above the crane plug 150 (as shown in Figure 1A), it will occur in the subsequent cleaning process. Lying problem. In detail, since the metal wire 16〇 and the barrier layer 162 cannot completely cover the crane 150, the exposed 15 〇 will react with the solvent used for the cleaning process, resulting in the loss of the plug 15 Hole 158' is shown in Figure 1B. Due to the corrosion of the (four) crane plug 15 〇 /, the upper and lower metal 'line 120, 16 〇 contact area is reduced, so that the resistance of the loop increases' will cause the circuit components to function abnormally. Moreover, the entire crane plug 150 was washed out to form an open circuit, resulting in failure of circuit components. _In addition to the misalignment of the lithography process, the tungsten plug will be corroded. When the line width of several pieces is reduced, the wire layer sometimes does not completely align with the tungsten plug below it. It will be inevitable that the need to solve the above problems will be greatly enhanced. SUMMARY OF THE INVENTION The present invention provides a method of manufacturing an interconnect, which can prevent a conductor layer from being rotted. The present invention further provides an interconnect structure capable of effectively protecting a plug located below the barrier layer of the 2010-2010 877 χυυ-·〇-0020 27923 twf.doc/n layer. The present invention proposes a method of manufacturing an interconnect. A substrate is first provided, and a first dielectric layer having an opening is formed on the substrate. Next, a conductor layer is formed in the opening such that the top surface height of the conductor layer is lower than the top surface of the first dielectric layer. Thereafter, a first barrier layer is formed on the first dielectric layer and the conductor layer, and a metal layer is formed on the first barrier layer. Next, the metal layer is patterned to form a barrier layer.
、在本發明之一實施例中，上述於開口中形成導體層的 方，包括先於第一介電層上形成填滿開口的導體材料層， 接著移除開口以外之導體材料層，之後再移除開口中部 的導體材料層。 在本發明之一實施例中，上述移除導體材料層的方法 包括化學機械研磨。 在本發明之一實施例中，上述形成第一阻降層的方法 包括沈積-餘刻-沈積法。 在本發明之-實施例中，上述之基底上已形成有金屬 導線或半導體元件。 在本發明之另—實施例中，上述之開口暴露出金屬導 線或半導體元件。 在本發明之-實施例中，内連線的製造方法更包括在 圖案化該金屬層與該第-叫⑽之後，於基底上形成第二 ’I電層’以及於第二介電層中形成插塞。 在本發明之-實施例中，内連線的製造方法更包括在 形成導體狀前，於開口之表面形成第二阻障層。 7 201005877 πϋυ-^,υυ〇-0020 27923twf.doc/n 在本發明之一實施例_，上述之導體層的頂面與介電 層的頂面高度差異範圍介於20奈米至6〇奈米之間。 在本發明之一實施例中，上述之導體層的材料包括 鎢。 在本發明之一實施例中，上述之第一阻障層的材料包 括鈦以及氮化欽。 本發明另提出一種内連線結構，其包括介電層、導體 鲁層、第一阻障層以及金屬層。介電層配置於基底上，且此 介電層具有開口。導體層位於介電層的開口中，且導體層 的頂面高度低於介電層的頂面高度。第一阻障層配置於^ 電層與導體層上。而金屬層配置於第一阻障層上。 在本發明之一實施例中，上述之基底上配置有金 線或半導體元件。 在本發明之一實施例中，上述之開口暴露出金屬導 或半導體元件。 ' 在本發明之一實施例中，上述之導體層的頂面與介電 Φ 層的頂面高度差異範圍介於20奈米至6〇奈来之間。 在本發明之一實施例中，上述之内連線結構更包括第 二阻障層，配置於介電層與導體層之間。 在本發明之一實施例中，上述之導體層的材料包括 鶴。 在本發明之一實施例中，上述之第一阻障層的材料包 括鈦以及氮化鈦。 本發明之内連線結構及其製造方法藉由使第一阻障 8 201005877 xu ι_/-^,υυ〇-0020 27923twf.doc/n 層作為導體層上的密封結構設計，達到保護導 果，因此可以避免導體層在後續製程中被腐蝕。 為讓本發明之上述特徵和優點能更明顯易懂，下文 舉較佳實施例，並配合所附圖式，作詳細說明如下。 【實施方式】 以下實施例是以介層窗插塞為例來說明本發明之内連 _ 線結構，但並不以此為限，而本發明亦可以應用於各式内 連線。圖2為本發明之一實施例的内連線結構之剖面示音 圖。如圖2所示’此内連線結構包括基底200、金屬 220 '介電層240、導體層250、阻障層256、阻障層262、 金屬導線260、介電層280以及導體層290。 基底200例如是半導體基底，如n型;ε夕基底、p型石夕 基底、三五族半導體基底等。在一實施例中，基底2〇〇上 已形成導電區（未續'不）或·~~般热知的半導體元件（未徐· 示）。金屬導線220配置在基底200上。金屬導線220的材 ❹ 料例如是鋁合金、銅合金或鋁銅合金。介電層240配置在 基底200上’並覆蓋金屬導線220。介電層240的材料例 如是氧化石夕(SiO)、氮化矽(SiN)、氮氧化矽(si〇N)、填;e夕坡 璃(PSG)、棚填石夕玻璃(BPSG)、無摻雜;ε夕玻璃(USG)、襄摻 雜矽玻璃(FSG)或介電常數低於4的低介電常數（low_k) 介電材料。金屬導線260配置於介電層240上。金屬導線 260的材料例如是合金、銅合金或紹銅合金。介電層28〇 配置於介電層240上，並覆蓋金屬導線260。介電層280 201005877 i.xj Ly~x^\j\j O-0020 27923twf.doc/n 的材料例如是氧切_、氮切（SiN)、氮氧化石夕 (SiON)、财玻璃(pSG)、爛财玻璃(Bp、 r常叫浏她於切低介 金屬::=°上 在開口 242的表面配置有阻陸a 攻。阻障層256的材料例如是鈦以及氮化鈦n t介電^0的開口 242中。此外，導體層25〇U ::低於”電層240的頂面高度。導體層25〇的材料例如 疋鵠。 阻5 262配置在導體層25〇之上以及金屬導線細 :。在此說明的是，由於導體層25()的頂面 t二?面高度，因此部分阻障層262錄導體層二 偽的;丨毛層240中’而部分阻障層262位於介電層24〇 ^金屬導線260之間。阻障層262在介電層2曰 ❹ ，的範圍介於20奈米至6〇奈米之間，而在介電= 的範圍則介於3G奈米至觸奈米二。阻 介鈦以及氮化鈦。在—實施例中，在 線2』的人射財置導體層携’以作為連接金屬導 線6〇的介層窗插塞。導體層290材料例如是鶴。 =別說明的是，本實施例中的導體層25〇為一個介 連接金屬導線220與更上一層的金屬導線 、巧與導體層謂上方的部分阻障層262例^ U填滿介電層240中的開口 242。由於配置在導體芦 201005877 …u 0020 27923twf.doc/n 250上方的阻障層262具有較厚的厚度，因此阻障層262 可以作為介；ts插塞的密封結構，而有效防止導體層25〇 在清洗製程中腐蝕流失。 在另一實施例中，介電層240的開口 242也可以是配 i於半導體元件的上方（未繪示於圖中）。也就是說，形 成在開口 242中的導體層25〇是作為接觸窗插塞，而電性 連接基底200表面的半導體元件與上層的金屬導線26〇。 鲁 以上說明了本發明之内連線結構，接下來將說明此内 連線結構的製造方法。圖3為本發明之一實施例的内連線 製造方法之流程示意圖。而圖4A至圖4E本發明之一實施 例的内連線製造方法之剖面示意圖。 首先，參照圖3步驟302以及圖4A，提供基底4〇〇。 基底400例如是半導體基底，如N型矽基底、p型矽基底、 二五族半導體基底等。基底4〇〇上例如是已形成有導電區 (未繪示）或一般熟知的半導體元件（未繪示）。在一實施例 中，基底400的表面已形成有金屬導線42〇(如圖4A所示)。 © 之後’參照圖3步驟304以及圖4A，在基底400表 面上形成介電層440,且介電層440覆蓋金屬導線420。介 電層440的材料例如氧化矽(si〇)、氮化矽(siN)、氮氧化矽 (SiON)、磷矽玻璃(PSG)、硼磷矽玻璃(BPSG)、無摻雜矽 玻璃(USG)、氟摻雜矽玻璃(FSG)或介電常數低於4的低介 電常數（l〇w-k)介電材料。介電層440的製作方式例如是 常壓化學氣相沈積（atmospheric CVD )、低壓化學氣相沈 積（low pressure CVD )、電漿化學氣相沈積 11 201005877 -^νν/υ-0020 27923twf.doc/n (plasma-enhanced CVD ’ PECVD)或高密度電聚化學氣 相沈積法（high density plasma CVD )等。接著，以圖案化 方法在介電層440中形成開口 452，如圖4A所示。開口 452則例如是暴露出金屬導線420，以作為介層窗開口。 特別說明的是，在另一實施例中，介電層440中的開 口 452也可以是形成於半導體元件的上方而暴露出基底 400上的半導體元件（未繪示於圖中），以作為接觸窗開 口之用。 _ 請參照圖4B，在一實施例中，可選擇性地在開口 452 表面上形成阻障層456,以提供一個導電性、物理附著性 較為良好的接觸界面，並防止後續形成的導體金屬擴散進 入周圍的介電質或半導體。此阻障層456的材料包括鈦、 鈦化氮或鈦鎢合金，而製造方法則包括例如直流電漿濺鍍 (DC plasma sputtering deposition)、氮化（nitridati〇n) 以及反應性錢鐘（reactive sputtering deposition )等方法。 之後，於基底400上形成一層導體材料層。導體材料 & 層例如疋覆盖介電層440並填滿開口 452。此導體材料層 的材料例如是鎢，而形成鶴導體材料層的方法則例如是化 學氣相沈積，其中更包括交替使用不同的化學氣相沈積方 法’例如矽還原（silicon reduction)、氫還原（hydr〇gen reduction)或石夕曱烧還原（siiane reducti〇n)，以得到較佳 的間隙填充（gap filling)能力來確實填滿開口 452，避免 產生孔洞（void)。剛完成的導體材料層在介電層44〇上 的厚度範圍約在300奈米至750奈米之間。 12 201005877 njj^-^uu〇-0020 27923twf.doc/n 接著’移除位在介電層440表面的導體材料層，並進 一步再移除一部份位在上述開口 452内的導體材料層，而 形成導體層450與位於導體層450上方的凹陷部454 (如 圖4B所示）。由餘留的導體材料層所形成的導體層45〇, 其頂面高度會低於介電層440的頂面高度，即為圖3中之 步驟306。凹陷部454的深度466約介於2〇nm至60nm之 間的範圍内。 上述移除導體材料層的方法例如化學機械研磨 (chemical mechanical polishing，CMP)或回蝕法（etch back)。在-實施例中’先以化學機械研磨移除上層毯狀 覆蓋（blanket)的導體材料層，使得剩 ?導體材料層頂面高度與介電層440頂面等:或= 而。接著進行過度研磨（ove卜polish) 體材料層而留下介電f，以形成凹陷部454以及 450。而上述另一種移除導體材料層的方法是回钱法。回餘 法是以乾侧（diy etching)的方式，不使關案化方法， =接_移除基材表_材料。回赌首先由上而下移 :導體材料層以域出介鶴44G表面，接著再進行過度 ^ ：rtch)移除開口 452中的部分導體材料層，以 ==二4道進行過細步驟時需控制操作條件， 體材料而儘量留下介電質。過度钮刻步 偷的标作時間或其他操作參數可以調控凹陷部伙的深度 接著，參照圖3步驟308以及圖4C，在基底400上 13In an embodiment of the invention, the forming the conductor layer in the opening comprises forming a layer of the conductor material filling the opening before the first dielectric layer, and then removing the layer of the conductor material other than the opening, and then The layer of conductor material in the middle of the opening is removed. In one embodiment of the invention, the above method of removing a layer of conductor material comprises chemical mechanical polishing. In one embodiment of the invention, the above method of forming the first resistive layer comprises a deposition-residual-deposition method. In the embodiment of the invention, a metal wire or a semiconductor element has been formed on the substrate. In still other embodiments of the invention, the openings expose metal wires or semiconductor components. In an embodiment of the invention, the method of fabricating the interconnect further includes forming a second 'I electrical layer' on the substrate and patterning the second layer in the second dielectric layer after patterning the metal layer and the first (10) Form a plug. In an embodiment of the invention, the method of fabricating the interconnect further includes forming a second barrier layer on the surface of the opening prior to forming the conductor. 7 201005877 πϋυ-^, υυ〇-0020 27923 twf.doc/n In an embodiment of the invention, the top surface of the conductor layer and the top surface of the dielectric layer have a height difference ranging from 20 nm to 6 〇 Between meters. In an embodiment of the invention, the material of the conductor layer comprises tungsten. In an embodiment of the invention, the material of the first barrier layer comprises titanium and nitride. The present invention further provides an interconnect structure comprising a dielectric layer, a conductor layer, a first barrier layer, and a metal layer. The dielectric layer is disposed on the substrate, and the dielectric layer has an opening. The conductor layer is located in the opening of the dielectric layer, and the top surface height of the conductor layer is lower than the top surface height of the dielectric layer. The first barrier layer is disposed on the electro-chemical layer and the conductor layer. The metal layer is disposed on the first barrier layer. In an embodiment of the invention, the substrate is provided with a gold wire or a semiconductor element. In one embodiment of the invention, the opening exposes a metal conductive or semiconductor component. In an embodiment of the invention, the top surface of the conductor layer and the top surface of the dielectric Φ layer have a height difference ranging from 20 nm to 6 nm. In an embodiment of the invention, the interconnect structure further includes a second barrier layer disposed between the dielectric layer and the conductor layer. In an embodiment of the invention, the material of the conductor layer comprises a crane. In an embodiment of the invention, the material of the first barrier layer comprises titanium and titanium nitride. The interconnect structure of the present invention and the manufacturing method thereof are designed by using the first barrier 8 201005877 xu ι_/-^, υυ〇-0020 27923 twf.doc/n layer as a sealing structure on the conductor layer to achieve the protection guide. Therefore, it is possible to prevent the conductor layer from being corroded in subsequent processes. The above described features and advantages of the present invention will be more apparent from the following description of the appended claims. [Embodiment] The following embodiments illustrate the interconnection structure of the present invention by taking a via plug as an example, but the invention is not limited thereto, and the present invention can also be applied to various interconnects. Figure 2 is a cross-sectional view of an interconnect structure of an embodiment of the present invention. As shown in FIG. 2, the interconnect structure includes a substrate 200, a metal 220' dielectric layer 240, a conductor layer 250, a barrier layer 256, a barrier layer 262, a metal trace 260, a dielectric layer 280, and a conductor layer 290. The substrate 200 is, for example, a semiconductor substrate such as an n-type; an ε-base, a p-type shi, a tri-five semiconductor substrate, or the like. In one embodiment, a conductive region (not continued) or a well-known semiconductor device (not shown) has been formed on the substrate 2. The metal wire 220 is disposed on the substrate 200. The material of the metal wire 220 is, for example, an aluminum alloy, a copper alloy or an aluminum copper alloy. The dielectric layer 240 is disposed on the substrate 200 and covers the metal wires 220. The material of the dielectric layer 240 is, for example, oxidized stone (SiO), tantalum nitride (SiN), bismuth oxynitride (si〇N), filled; e-slope glass (PSG), shed stone-filled glass (BPSG), Undoped; 夕 玻璃 glass (USG), ytterbium-doped yttrium glass (FSG) or a low dielectric constant (low_k) dielectric material with a dielectric constant below 4. The metal wire 260 is disposed on the dielectric layer 240. The material of the metal wire 260 is, for example, an alloy, a copper alloy or a copper alloy. The dielectric layer 28 is disposed on the dielectric layer 240 and covers the metal wires 260. Dielectric layer 280 201005877 i.xj Ly~x^\j\j O-0020 27923twf.doc/n The materials are, for example, oxygen cut, nitrogen cut (SiN), nitrogen oxynitride (SiON), and fiscal glass (pSG) B, r often called Liu on the cut low dielectric metal:: = ° on the surface of the opening 242 is equipped with a barrier a attack. The material of the barrier layer 256 is, for example, titanium and titanium nitride nt In addition, the conductor layer 25 〇 U :: is lower than the top surface height of the "electric layer 240. The material of the conductor layer 25 疋鹄 is, for example, 疋鹄. The resistor 5 262 is disposed on the conductor layer 25 以及 and The metal wire is fine: It is explained here that, due to the top surface t of the conductor layer 25(), the partial barrier layer 262 records the conductor layer as a dummy; in the bristle layer 240, the partial barrier layer 262 is located between the dielectric layer 24 and the metal wire 260. The barrier layer 262 is in the dielectric layer 2, ranging from 20 nm to 6 nm, and in the range of dielectric = From 3G nanometer to nanometer nanometer. Resisting titanium and titanium nitride. In the embodiment, the person on the line 2's is carrying the conductor layer to carry the interlayer window plug which is connected to the metal wire 6〇. Conductor layer 290 material such as It is a crane. = It should be noted that the conductor layer 25 in the present embodiment is filled with a metal wire 220 and a metal wire of a higher layer, and a portion of the barrier layer above the conductor layer is filled. The opening 242 in the dielectric layer 240. Since the barrier layer 262 disposed above the conductor reed 201005877 ... u 0020 27923 twf.doc / n 250 has a thick thickness, the barrier layer 262 can serve as a dielectric seal; The structure effectively prevents the conductor layer 25 from being etched away during the cleaning process. In another embodiment, the opening 242 of the dielectric layer 240 may also be disposed above the semiconductor device (not shown). That is, the conductor layer 25A formed in the opening 242 serves as a contact window plug, and electrically connects the semiconductor element on the surface of the substrate 200 with the upper metal wire 26A. The above describes the interconnect structure of the present invention, Next, a manufacturing method of the interconnect structure will be described. Fig. 3 is a schematic flow chart of a method for manufacturing an interconnect according to an embodiment of the present invention, and Fig. 4A to Fig. 4E are an interconnect manufacturing method according to an embodiment of the present invention. Schematic diagram First, a substrate 4 is provided with reference to step 302 of Fig. 3 and Fig. 4A. The substrate 400 is, for example, a semiconductor substrate such as an N-type germanium substrate, a p-type germanium substrate, a bi-five semiconductor substrate, etc. The substrate 4 is, for example, A conductive region (not shown) or a generally well-known semiconductor device (not shown) has been formed. In one embodiment, the surface of the substrate 400 has been formed with a metal wire 42 (shown in Figure 4A). Referring to step 304 of FIG. 3 and FIG. 4A, a dielectric layer 440 is formed on the surface of the substrate 400, and the dielectric layer 440 covers the metal wires 420. The material of the dielectric layer 440 is, for example, cerium oxide (si〇), cerium nitride (siN), cerium oxynitride (SiON), phosphoric bismuth glass (PSG), borophosphoquinone glass (BPSG), undoped bismuth glass (USG) ), fluorine-doped bismuth glass (FSG) or a low dielectric constant (l〇wk) dielectric material having a dielectric constant of less than 4. The dielectric layer 440 is formed by, for example, atmospheric CVD, low pressure CVD, and plasma chemical vapor deposition. 11 201005877 -^νν/υ-0020 27923twf.doc/ n (plasma-enhanced CVD 'PECVD) or high density plasma photochemical deposition (high density plasma CVD). Next, an opening 452 is formed in the dielectric layer 440 by a patterning method as shown in Fig. 4A. The opening 452 is, for example, exposed to the metal wire 420 to serve as a via opening. In particular, in another embodiment, the opening 452 in the dielectric layer 440 may also be a semiconductor element (not shown) formed on the substrate 400 over the semiconductor device to serve as a contact. Window opening. Referring to FIG. 4B, in an embodiment, a barrier layer 456 may be selectively formed on the surface of the opening 452 to provide a conductive, physically adherent contact interface and prevent subsequent diffusion of the conductive metal. Enter the surrounding dielectric or semiconductor. The material of the barrier layer 456 includes titanium, titanium nitride or titanium tungsten alloy, and the manufacturing method includes, for example, DC plasma sputtering deposition, nitridation, and reactive sputtering. Deposition) and other methods. Thereafter, a layer of conductive material is formed on the substrate 400. A conductor material & layer such as germanium covers the dielectric layer 440 and fills the opening 452. The material of the conductor material layer is, for example, tungsten, and the method for forming the layer of the conductor material is, for example, chemical vapor deposition, which further includes alternately using different chemical vapor deposition methods such as silicon reduction and hydrogen reduction. Hydr〇gen reduction or siiane reducti〇n to obtain a better gap filling ability to indeed fill the opening 452 to avoid voids. The thickness of the just completed conductor material layer on the dielectric layer 44 is in the range of about 300 nm to 750 nm. 12 201005877 njj^-^uu〇-0020 27923twf.doc/n then 'removing the layer of conductor material on the surface of the dielectric layer 440 and further removing a portion of the layer of conductor material located in the opening 452, The conductor layer 450 is formed with a recess 454 (shown in FIG. 4B) above the conductor layer 450. The conductor layer 45A formed by the remaining conductor material layer has a top surface height lower than the top surface height of the dielectric layer 440, which is step 306 in FIG. The depth 466 of the recess 454 is approximately in the range of between 2 〇 nm and 60 nm. The above method of removing the conductor material layer is, for example, chemical mechanical polishing (CMP) or etch back. In the embodiment, the layer of the conductor layer of the upper blanket is removed by chemical mechanical polishing such that the top surface of the conductor material layer is at the top surface of the dielectric layer 440 or the like: or =. A layer of bulk material is then over-polished to leave a dielectric f to form recesses 454 and 450. The other method of removing the conductor material layer is the money return method. The back-recovery method is a diy etching method, which does not make the method of closing, and the material is removed. The gambling is firstly moved from top to bottom: the conductor material layer is out of the surface of the crane 44G, and then the excess conductor layer is removed by removing the portion of the conductor material in the opening 452, and the fine step is performed by == two. Control the operating conditions, leaving the dielectric as much as possible. Excessive button stepping time or other operational parameters can adjust the depth of the depressed portion. Next, referring to step 308 of FIG. 3 and FIG. 4C, on the substrate 400.
201005877 iiJi^-^uu〇-0020 27923twf.doc/n 46上。阻障層462例如是覆蓋介電層44。以及 層450，亦即阻障層462會填入導體層450上方的凹 =454，^ 462在第―介電層44〇上的厚度_約 2 3〇nm至1 〇〇腹之間的範圍内。阻障層462可用以改 體表面對其他材料的附著力或導電= 擴散進入周圍的介電質或半導體。上述阻障 :2的材料例如是鈦、氮化鈦或鈦鶴合金。而形成阻障 ς。H方法則例如是物理氣相沈積法或化學氣相沈積 ά Λ施例中’阻障層462是由鈦層與氮化鈦層所組 合層，其製造松是先㈣直流電漿麟形成底部 再城域崎的表面形就化鈦層或以反應性 爲又鈦層表面j[接沈積氮化鈦層❿形成之。在形成阻障 ^ 462的過程中，還可以選擇性地使用沈積-侧_沈積法 Cdepositi〇n_etchback_dep〇siti〇n，岭etch d印）來增進阻 ，材料的階梯覆蓋能力。也就是說’使用氬離子減射餘刻 ，、阻2材料沈積交互操作的方式，以消除沈積過程中形成 的懸犬(〇Verhang )’並具有較好的階梯覆蓋（step coverage ) 能力，而可以使阻障層462確實填充於凹陷部454中，並 維持表面平坦，而不需額外的平坦化處理。 之後，參照圖3步驟310以及圖4D，在阻障層462 上形成金屬層（未繪示）。金屬層的材料例如是鋁、銅、鋁 ，，金或銘；ε夕銅合金等。上述金屬層的製作方法例如是化 +氣相沈積或物理氣相沈積（phySicai vap〇r deposition， D )專。其中’物理氣相沈積則例如是蒸鍍（evap〇rati〇n) 201005877 λ— ------0020 27923twf.doc/n 或錢鍍（sputtering)。 立接著’參照圖3步驟312以及圖4D，對金屬層與阻 障層462同進行圖案化，而形成金屬導線柳與阻障層 462a。此圖案化過程例如在金屬層上形成圖案化光阻層 47〇,接著以化光阻層_為罩幕進行_製程來移除 部f金屬層與阻障層462。此外，在形成圖案化光阻層47〇 之前，可選擇性地於金屬層表面形成底部抗反射塗佈層， ❹ 以利於控制微影製程之進行。 在一貝施例中，若圖案化過程發生錯誤對準，會導致 $屬導線460的配置並未完全覆蓋於導體層45〇之上，參 舨圖4D。由於蝕刻製程可以控制蝕刻停止於介電層4牝 表面，所以位在導體層视上之部分阻障層4伽仍得以保 留’使導體層450不會被暴露出來，而達到密封（seal) 導體層450之功效。 5月參照圖4E ’在圖案化製程後’移除在金屬導線460 上的圖案化光阻層携。移除圖案化光阻層47〇的方法例 # ㈣制氧錄灰化伽。歸，進行清洗餘，以去除 表面殘留的微粒或雜質。清洗製程所使用的溶劑可以是酸 陡或鹼性，於此技術領域具有通常知識者可視其需求而調 整。在進行清洗製程時，因為導體層450上方的阻障層462a 有較厚的厚度’導體層450並沒有被裸露出來，而且阻 障層462a的材料並不會與清洗用的溶劑發生反應，故可以 避免導體層450被腐蝕的問題。 而在—實施例中，參照圖4E，形成金屬導線46〇之 15 201005877 …“一…0020 27923twf.doc/n 後，更可以在基底400上形成介電層48〇。接 案化方法於介電層中戦介層_ 口(树; 窗開口例如是暴露出金屬導線働。當上述圖案化的^ 參 =中，需控制良好_刻選擇“不至於破壞或餘穿阻 =462a稞露的部分。值得一提的是，在進行圖案化的過 ，中，即使是發生錯誤對準的情況而使得介層窗開口 凡全形成在金屬導線460上，由於導體層45〇上方形 厚度較厚雜_ 462a，因齡層窗開口並不會暴露 體層450。經過去光阻處理後，再接著進行濕式清洗製程， 此時所使用的清洗溶劑亦不會接觸導體層彻，而可以此 保護導體層450免於腐餘。之後，在介電層的介層窗 開口中形成導體層49G ’以作為插塞。導體層働的材 例如是鎢。 此外在上述貫施例中是以形成内連線結構中的金屬 插塞為例來進行說明’然本發明並稀於此。本發明之結 構及方法還可以應驗在開σ巾填人導體層、並於導體^ 上形成阻障層的任何製程，熟知本領域之技術人員當可依 據前^實施例而知其應用及變化，故於此不再贅述。 綜上所述，本發明之内連線結構及其製造方法，藉由 阻障層作為導體層上的密封結構設計，達到保護導體層的 效果。此内連線結構及其製造方法可以使導體材料不會在 金屬⑽或介層蝴後的清潔步财被雜，避免微電子 元件性能異常或失效。 此外’本發明之内連線製造方法只需要略微調整習知 16 201005877 X„-0020 27923twf.doc/n 製程，即可完成所設計之内連線結構，製程變更簡便，而 且不需導入額外的設備。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何所屬技術領域中具有通常知識者，在不 脫離本發明之精神和範圍内，當可作些許之更動與潤飾， 因此本發明之保護範圍當視後附之申請專利範圍所界定者 為準。 β 【圖式簡單說明】 圖1Α至1Β是習知之一種内連線結構的示意圖。 圖2是依照本發明之一實施例之一種内連線結構的 意圖。 μ 圖3疋依照本發明之一實施例之一種内連線的製造方 法的流程示意圖。 圖4Α至4Ε是依照本發明之一實施例之一種内遠 製造方法的剖面示意圖。 【主要元件符號說明】 100、200、400 :基底 120、160、220、260、420、460 :金屬導線 140、240、280、440、480 :介電層 150 :鎢插塞 158 :孔洞 162、256、262、456、462、462a :阻障層 17 27923twf.doc/n 201005877 •l ·!«； JL·^-“ V V W_0020 170、470 :圖案化光阻層 250、290、450、490 :導體層 266、466 :深度 268、468 :厚度 302-310 ··步驟 452 :開口 454 :凹陷部201005877 iiJi^-^uu〇-0020 27923twf.doc/n 46. The barrier layer 462 is, for example, a cover dielectric layer 44. And the layer 450, that is, the barrier layer 462 is filled in the recess 454 above the conductor layer 450, the thickness of the 462 on the first dielectric layer 44 _ is about 2 3 〇 nm to 1 between the belly Inside. The barrier layer 462 can be used to modify the adhesion of the surface to other materials or to conduct electricity = diffuse into the surrounding dielectric or semiconductor. The material of the above barrier: 2 is, for example, titanium, titanium nitride or titanium crane alloy. And form a barrier. The H method is, for example, a physical vapor deposition method or a chemical vapor deposition method. In the embodiment, the barrier layer 462 is a layer composed of a titanium layer and a titanium nitride layer, and the fabrication of the layer is first (four) DC plasma pulverization forms the bottom. The surface shape of the metropolitan area is formed by the titanium layer or by the surface of the titanium layer. In the process of forming the barrier ^ 462, it is also possible to selectively use the deposition-side_deposition method Cdepositi〇n_etchback_dep〇siti〇n, to improve the step coverage of the material. That is to say, 'the use of argon ion reduction after the moment, the resistance 2 material deposition interaction mode to eliminate the formation of the cantilever (〇Verhang) in the deposition process and has better step coverage ability, and The barrier layer 462 can be surely filled in the recess 454 and the surface is maintained flat without additional planarization. Thereafter, referring to step 310 of FIG. 3 and FIG. 4D, a metal layer (not shown) is formed on the barrier layer 462. The material of the metal layer is, for example, aluminum, copper, aluminum, gold or inscription; The above metal layer is produced by, for example, chemical vapor deposition or physical vapor deposition (physicai vap〇r deposition, D). Among them, physical vapor deposition is, for example, vapor deposition (evap〇rati〇n) 201005877 λ-------0020 27923twf.doc/n or sputtering. Referring to Fig. 3, step 312 and Fig. 4D, the metal layer and the barrier layer 462 are patterned together to form a metal wire and a barrier layer 462a. This patterning process, for example, forms a patterned photoresist layer 47 on the metal layer, and then the photoresist layer _ is used as a mask to remove the portion f metal layer and the barrier layer 462. In addition, a bottom anti-reflective coating layer may be selectively formed on the surface of the metal layer before the formation of the patterned photoresist layer 47, to facilitate control of the lithography process. In a case study, if the patterning process is misaligned, the configuration of the $-wire 460 does not completely cover the conductor layer 45A, see Figure 4D. Since the etching process can control the etching to stop on the surface of the dielectric layer 4, a portion of the barrier layer 4 located in the conductor layer is still retained, so that the conductor layer 450 is not exposed, and a sealed conductor is reached. The effect of layer 450. In May, the patterned photoresist layer on the metal wires 460 is removed after the patterning process with reference to Figure 4E'. Example of removing the patterned photoresist layer 47A # (4) Oxygen recording ashing. Return, carry out the cleaning to remove particles or impurities remaining on the surface. The solvent used in the cleaning process may be acid steep or alkaline, and the person skilled in the art can adjust it according to his needs. When the cleaning process is performed, since the barrier layer 462a over the conductor layer 450 has a thick thickness, the conductor layer 450 is not exposed, and the material of the barrier layer 462a does not react with the solvent for cleaning. The problem that the conductor layer 450 is corroded can be avoided. In the embodiment, referring to FIG. 4E, after the metal wire 46 is formed, 15 201005877 ... "a ... 0020 27923 twf. doc / n, a dielectric layer 48 更 can be formed on the substrate 400. In the electrical layer, the interlayer _ mouth (tree; window opening, for example, exposes the metal wire 働. When the above-mentioned patterned ^ parameter =, it needs to be well controlled _ select "not to destroy or residual resistance = 462a exposed In addition, it is worth mentioning that, in the case of patterning, even if the misalignment occurs, the opening of the via window is completely formed on the metal wire 460, because the conductor layer 45 is thicker on the square. Miscellaneous _ 462a, the age layer window opening does not expose the body layer 450. After the photoresist treatment, the wet cleaning process is followed, and the cleaning solvent used at this time does not contact the conductor layer, and can be protected. The conductor layer 450 is protected from corrosion. Thereafter, the conductor layer 49G' is formed as a plug in the via opening of the dielectric layer. The material of the conductor layer is, for example, tungsten. Further, in the above embodiment, the formation is performed. Metal plugs in the wiring structure are taken as an example It is to be understood that the present invention is not limited thereto. The structure and method of the present invention can also be applied to any process in which a conductor layer is filled and a barrier layer is formed on the conductor, and those skilled in the art can rely on it. The application and the changes are known in the foregoing embodiments, and thus will not be described herein. In summary, the interconnect structure of the present invention and the manufacturing method thereof are designed by using a barrier layer as a sealing structure on a conductor layer. The effect of protecting the conductor layer. The interconnect structure and the manufacturing method thereof can make the conductor material not be cleaned after the metal (10) or the layer is cleaned, and the performance of the microelectronic component is prevented from being abnormal or invalid. The interconnect manufacturing method only needs to slightly adjust the conventional 16 201005877 X„-0020 27923twf.doc/n process to complete the designed interconnect structure, the process change is simple, and no additional equipment needs to be imported. The above has been disclosed in the preferred embodiments, and it is not intended to limit the invention, and any one of ordinary skill in the art can be made without departing from the spirit and scope of the invention. The scope of protection of the present invention is defined by the scope of the appended claims. β [Simple Description of the Drawings] Figures 1A to 1B are schematic diagrams of a conventional interconnect structure. An intent of an interconnect structure in accordance with an embodiment of the present invention. FIG. 3 is a flow diagram of a method of fabricating an interconnect according to an embodiment of the present invention. FIGS. 4A through 4B are diagrams in accordance with one embodiment of the present invention. A schematic cross-sectional view of an internal manufacturing method. [Main component symbol description] 100, 200, 400: substrate 120, 160, 220, 260, 420, 460: metal wires 140, 240, 280, 440, 480: dielectric Layer 150: tungsten plug 158: hole 162, 256, 262, 456, 462, 462a: barrier layer 17 27923twf.doc/n 201005877 • l ·!«; JL·^-"VV W_0020 170, 470: patterning Photoresist layer 250, 290, 450, 490: conductor layer 266, 466: depth 268, 468: thickness 302-310 · step 452: opening 454: recess
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