201005312 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種晶片測試機，特別是有關於一 種每一晶片插座具有獨立機構，可分別進行晶片取放與下 壓的晶片測試機。 【先前技術】 電子元件於製造完成後需要經過測試，藉以檢測該 電子元件是否能夠達到預期之功能。當電子元件為影像感 測電子元件時，例如：金屬氧化影像感測元件（CMOS image sensor )、電荷搞合元件（Charge Coupled Device; CCD)等，該等影像感測電子元件之晶片具有感 光區，晶片測試機必須具備一測試光源，藉以提供感光區 測試所需的光線種類及強度。一般在進行影像感測電子元 件（image sensor 1C)的最終測試(final test)時，係將測 試所需的光源直接裝設在晶片測試機下方，然後以晶片取 放裝置將影像感測電子元件移至測試位置，接著該晶片取 放裝置下壓，使得影像感測電子元件的接點與相對應的探 針緊密接觸，藉以進行測試。 然而上述之測試機並不適用於系統層級測試 (System Level Test)，第一 A圖顯示習知用於系統層級測 6 201005312 試的晶片測試機100之侧視示意圖。該晶片測試機1〇〇 包含至少一晶片插座（IC socket)110以及一晶片取放裝置 120。該晶片插座11〇設置於一模擬主機板6〇上，所謂 的系統層級測試就是將影像感測電子元件之晶片5〇容置 於晶片插座110中，由該模擬主機板60進行全功能測 試。下壓裝置70設置於相對應的晶片插座11()的上方， 用以提供下壓力量使得晶片50的接點51與相對應的探 ❹ 針（Ρ〇9〇 Pins) 130緊密接觸’藉以進行測試。另外下 壓裝置70具有一測試光源75,用以提供測試所需的光線 至晶片50的感光區52。 第一 B圖至第一 D圖顯示習知系統層級測試的步驟 示忍圖。系統層級測試的步驟如下：首先，如第一 B圖所 示’jl由晶片取放裝置12〇將晶片5〇移至晶片插座11〇; 9接著’如第一 C圖所示，藉由下壓裝置70使得晶片50 的接點與相對應的探針13Q緊密接觸，同時藉由設置於該 下壓裝置70之測試光源75提供測試所需的光線，藉以 進行測試；然後’如第一 D圖所示，待測試完成後，下 墨裂置70向上移動，藉由a 錯由日日片取放裝置120將晶片50 移出晶片插座110，最後再重滿 瓦行里復别4的步驟，由晶片取放 裝置120將另一晶片50至晶片栖 日日巧插座110進行測試。 7 201005312 前述之晶片測試機雖可達成系統層級測試的目的， 然而其效率較低’如第一 A圖所示’當晶片測試機1 〇〇 具有複數之晶片插座110時，由於晶片50係由同一個晶 片取放裝置120進行傳送動作，當晶片5〇的測試時間與 晶片取放裝置120傳送動作所需的時間搭配不佳時，晶片 插座110常會閒置等待晶片取放裝置120將測試完成的 Φ 晶片50移走’或等待晶片取放裝置120將待測之晶片50 放置於晶片插座110,晶片插座的閒置時間導致晶片 測試機100之效率降低。 | 鑑於上述習知技術所存在的缺點，有必要提出一種 晶片測試機，每一晶片插座具有獨立機構，可分別進行晶 片取放與下壓’晶片插座不會因為等待晶片取放裝置而閒 • 置。 【發明内容】 本發明的目的在於提供一種晶片測試機，每一晶片 插座具有獨立機構，可分別進行晶片取放與下壓，晶片插 座不會因為等待晶片取放裝置而閒置，藉以提昇測試的效 率。 8 201005312 根據上述的目的’本發明揭露一種晶片測試機，包 含：至少一晶片插座以及至少一晶片取放裝置。該晶片取 放裝置具有一取放機構及一下壓機構，該下壓機構具有一 測試光源。根據本案一實施例’晶片插座的數量與該晶片 取放裝置的數量相同，複數之晶片插座不會因為等待晶片 取放裝置而閒置。 φ 本發明的功效在於提供一種晶片測試機，藉由本發 明之晶片測試機’每一晶片插座具有獨立機構，可分別進 行晶片取放與下壓，晶片插座不會因為等待晶片取放裝置 而閒置，因此測試的效率可得以提昇。 【實施方式】 本發明的一些實施例將詳細描述如下。然而，除了 如下描述外’本發明還可以廣泛地在其他的實施例施行， 且本發明的範圍並不受實施例之限定，其以之後的專利範 圍為準。再者’為提供更清楚的描述及更易理解本發明， 圖式内各部分並沒有依照其相對尺寸繪圖，某些尺寸與其 他相關尺度相比已經被誇張；不相關之細節部分也未完全 繪出，以求圖式的簡潔。 第二A圖顯示根據本發明一較佳實施例之晶片測試 201005312 機的剖面示意圖。該晶片測試機200 ’包含：複數之晶片 插座210以及複數之晶片取放裝置220。該晶片插座210 係設置於一模擬主機板60上，藉由該模擬主機板60對 影像感測電子元件之晶片50 ’進行系統層級測試。晶片 取放裝置220具有一取放機構228及一下壓機構224’ 下壓機構224具有一測試光源225。晶片取放裝置220 係用以將待測之晶片50放置於晶片插座210 ’或將測試 φ 完成的晶片50移走；下壓機構224則係進行一下壓動 作，該下壓機構224與晶片插座210形成一密閉空間’ 藉以隔絕外界光線’再以測試光源225對晶片50進行/則 試。 根據本實施例，晶片插座210的數量與晶片取放裝 置220的數量相同’由於每一晶片插座210具有相對應 ❹ 之晶片取放裝置220,可分別進行晶片50的取放與下壓’ 因此複數之晶片插座21 〇不會因為等待晶片取放裝置 220而閒置，因此測試的效率可得以提昇。本實施例中’ 測試光源225係設置於下壓機構224,用以提供測試影像 感測電子元件之晶片50所需的光線’但並不以此為限’ 測試光源225也可以設置於晶片測試機200的其他位 置，或者不具有測試光源225 ’用來進行非影像感測電子 201005312 元件之晶片50的測試。 第二B圖顯示第二A圖的放大剖面示意圖。晶片插 座210設置於該晶片測試機200之一平台，該晶片插座 210可容納一晶片50’進行晶片50的測試。晶片插座210 具有複數之探針（p〇g〇 pjns) 230以及一固定機構211， 複數之探針230係對應於晶片50之複數之訊號接點51 ❹ 設置於晶片插座210内，藉由探針230與晶片50晶片之 訊號接點51接觸，以便進行晶片50的測試；固定機構 211係用以固定該晶片50。 取放機構228設置於該晶片插座210的上方，用以 取放晶片50 ’取放機構228具有一軟式吸頭221以及一 釋放機構222,軟式吸頭221係藉由真空吸取該晶片50, ❶ 進行晶片50的取放，該釋放機構222可解除該固定機構 211。 本實施例中’取放機構228之釋放機構222包含一 導引銷223’固定機構211包含至少一滑塊212以及一彈 簧213，該彈簧213設置於該滑塊212之一端，用以將 該滑塊212朝晶片50之方向推頂，使得該滑塊212可推 11 201005312 頂晶片50之侧邊，藉以固定該晶片50;滑塊212包含一 定位孔214，當導引銷223插入該定位孔214時，該滑 塊212可朝外移動，而解除固定機構211對晶片50的夾 持。 根據本實施例，滑塊212係設置於晶片50的兩侧， 但並不以此為限，滑塊212也可以設置於晶片50的四 φ 周，藉由推頂晶片50之侧邊而固定該晶片50。 第二C圖顯示第二A圖中，晶片50進行系統層級 測試的剖面示意圖。其中，晶片50係一影像感測電子元 件，晶片50的上表面具有感光區52，晶片50的下表面 具有複數之訊號接點51。以晶片測試機200，進行晶片 50的測試步驟說明如下： • 首先，藉由取放機構228的真空吸力，將晶片50移 至晶片插座210之上方；其次，將導引銷223插入該定 位孔214，使得滑塊212朝外移動，而露出容納晶片50 的空間；接著，取放機構228向下移動，將晶片50置入 容納晶片50的空間，此時，晶片50的訊號接點51與對 應之探針230產生接觸；接著，晶片取放裝置220取消 真空吸力並向上移動，導引銷223脫離定位孔214,此時 12 201005312 滑塊212藉由彈簧213之推頂，使得該滑塊212推頂晶 片50之侧邊’藉以固定晶片5〇 ;最後，設置於下壓機構 224之測試光源225移至晶片50之感光區52的上方， 且進行一下壓動作，使得下壓機構224與晶片插座210 形成一密閉空間，藉以隔絕外界光線，並由測試光源225 提供測試所需的光線，藉由該模擬主機板60對影像感測 電子元件之晶片50進行系統層級測試，根據本案一實施 〇 例，晶片插座210的數量與該晶片取放裝置220的數量 相同’複數之晶片插座210不會因為等待晶片取放裝置而 閒置。。 藉由本發明之晶片測試機，晶片插座不會因為等待 晶片取放裝置而間置，因此測試的效率可得以提羿° Φ 上述之實施例僅係為說明本發明之技術思想及特 點，其目的在使熟悉此技藝之人士能了解本發明之内容並 據以實施，當不能以之限定本發明之專利範圍’即凡其他 未脫離本發明所揭示精神所完成之各種等效改變或修飾 都涵蓋在本發明所揭露的範圍内，均應包含在下述之中請 專利範圍内。 13 201005312 【圖式簡單說明】 第一 A圖顯示習知用於系統層級測試的晶片測試機 之侧視示意圖。 第一 B圖至第一 D圖顯示習知系統層級測試的步驟 示意圖。 第二A圖顯示根據本發明一較佳實施例之晶片測試 機的剖面示意圖。 第二B圖顯示第二A圖的放大剖面示意圖。 第二C圖顯示第二A圖中，晶片進行系統層級測試 的剖面示意圖。 【主要元件符號說明】 50 晶片 51 接點 52 感光區 60 模擬主機板 70 下壓裝置 75 測試光源 100 晶片測試機 110 晶片插座 120 晶片取放裝置 121 軟式吸頭 201005312 130 探針 200 晶片測試機 210 晶片插座 211 固定機構 212 滑塊 213 彈簧 214 定位孔 參 220 晶片取放裝置 221 軟式吸頭 222 釋放機構 223 導引銷 224 下壓機構 225 測試光源 228 取放機構 β 230 探針BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer testing machine, and more particularly to a wafer testing machine having an independent mechanism for each wafer socket for separately performing wafer pick-and-place and press-down. [Prior Art] After the electronic component is manufactured, it needs to be tested to detect whether the electronic component can achieve the intended function. When the electronic component is an image sensing electronic component, for example, a CMOS image sensor, a charge coupled device (CCD), or the like, the wafer of the image sensing electronic component has a photosensitive region. The wafer tester must have a test light source to provide the type and intensity of light required for the photosensitive zone test. Generally, when performing a final test of an image sensor 1C, the light source required for the test is directly mounted under the wafer tester, and then the image sensing electronic component is mounted by the wafer pick and place device. The test is moved to the test position, and then the wafer pick-and-place device is pressed down so that the contacts of the image sensing electronic components are in close contact with the corresponding probes for testing. However, the above test machine is not suitable for System Level Test, and the first A chart shows a side view of a conventional wafer tester 100 for system level test 6 201005312. The wafer tester 1A includes at least one wafer socket 110 and a wafer pick and place device 120. The chip socket 11 is disposed on an analog motherboard 6. The so-called system level test is to place the chip 5 of the image sensing electronic component in the chip socket 110, and the analog motherboard 60 performs full-featured testing. The pressing device 70 is disposed above the corresponding wafer socket 11 () for providing a downward pressure so that the contact 51 of the wafer 50 is in close contact with the corresponding probe pin 130. test. In addition, the pressing device 70 has a test light source 75 for providing the light required for testing to the photosensitive region 52 of the wafer 50. The first B to the first D diagrams show the steps of the conventional system level test. The steps of the system level test are as follows: First, as shown in FIG. B, 'jl is transferred from the wafer pick-and-place device 12 to the wafer socket 11〇; 9 then 'as shown in the first C, by The pressing device 70 causes the contacts of the wafer 50 to be in close contact with the corresponding probes 13Q, while providing the light required for the test by the test light source 75 disposed on the pressing device 70, thereby performing the test; As shown in the figure, after the test is completed, the lower ink slit 70 is moved upward, and the wafer 50 is removed from the wafer socket 110 by the Japanese wafer pick-and-place device 120, and finally the step of repeating the tile 4 is repeated. Another wafer 50 is tested by the wafer pick and place device 120 to the wafer carrier. 7 201005312 The aforementioned wafer tester can achieve the purpose of system level test, but its efficiency is low 'as shown in Figure AA'. When the wafer tester 1 has a plurality of wafer sockets 110, since the wafer 50 is The same wafer pick-and-place device 120 performs the transfer operation. When the test time of the wafer 5 is not well matched with the time required for the transfer operation of the wafer pick-and-place device 120, the wafer socket 110 is often idle waiting for the wafer pick-and-place device 120 to complete the test. Φ Wafer 50 is removed' or waiting for wafer pick and place device 120 to place wafer 50 to be tested on wafer socket 110. The idle time of the wafer socket causes the efficiency of wafer tester 100 to decrease. In view of the shortcomings of the above-mentioned prior art, it is necessary to propose a wafer testing machine, each of which has an independent mechanism for separately performing wafer pick-and-place and pressing. The wafer socket is not freed by waiting for the wafer pick-and-place device. Set. SUMMARY OF THE INVENTION An object of the present invention is to provide a wafer testing machine, each of which has an independent mechanism for separately performing wafer pick-and-place and pressing, and the wafer socket is not idle because of waiting for the wafer pick-and-place device, thereby improving the test. effectiveness. 8 201005312 In accordance with the above purposes, the present invention discloses a wafer testing machine comprising: at least one wafer socket and at least one wafer pick-and-place device. The wafer pick-and-place device has a pick-and-place mechanism and a lower pressing mechanism, the press-down mechanism having a test light source. According to an embodiment of the present invention, the number of wafer sockets is the same as the number of wafer pick-and-place devices, and the plurality of wafer sockets are not left idle for waiting for the wafer pick-and-place device. φ The effect of the present invention is to provide a wafer testing machine. With the wafer testing machine of the present invention, each wafer socket has an independent mechanism for performing wafer pick-and-place and press-down, and the wafer socket is not left idle for waiting for the wafer pick-and-place device. Therefore, the efficiency of the test can be improved. [Embodiment] Some embodiments of the present invention will be described in detail below. However, the present invention may be widely practiced in other embodiments except as described below, and the scope of the present invention is not limited by the embodiments, which are subject to the scope of the following patents. Further, in order to provide a clearer description and to more easily understand the present invention, the various parts of the drawings are not drawn according to their relative dimensions, and some dimensions have been exaggerated compared to other related scales; the irrelevant details are not fully drawn. Out, in order to make the schema simple. Figure 2A shows a cross-sectional view of a wafer test 201005312 machine in accordance with a preferred embodiment of the present invention. The wafer tester 200' includes a plurality of wafer sockets 210 and a plurality of wafer pick-and-place devices 220. The chip socket 210 is disposed on an analog motherboard 60. The analog motherboard 60 performs system level testing on the wafer 50' of the image sensing electronic component. The wafer pick and place device 220 has a pick and place mechanism 228 and a lower pressing mechanism 224'. The pressing mechanism 224 has a test light source 225. The wafer pick-and-place device 220 is used to place the wafer 50 to be tested on the wafer socket 210' or to remove the wafer 50 whose test φ is completed; the pressing mechanism 224 performs a pressing operation, the pressing mechanism 224 and the wafer socket 210 forms a confined space 'to isolate ambient light' and then performs/tests the wafer 50 with the test source 225. According to the present embodiment, the number of the wafer sockets 210 is the same as the number of the wafer pick-and-place devices 220. Since each of the wafer sockets 210 has a corresponding wafer pick-and-place device 220, the wafer 50 can be picked up and lowered, respectively. The plurality of wafer sockets 21 are not left idle for waiting for the wafer pick-and-place device 220, so the efficiency of the test can be improved. In this embodiment, the test light source 225 is disposed in the pressing mechanism 224 for providing the light required for testing the wafer 50 of the image sensing electronic component, but is not limited thereto. The test light source 225 can also be disposed on the wafer test. Other locations of machine 200, or without test light source 225', are used to test wafer 50 of non-image sensing electronics 201005312 components. The second B diagram shows an enlarged cross-sectional view of the second A diagram. The wafer socket 210 is disposed on a platform of the wafer testing machine 200, and the wafer socket 210 can accommodate a wafer 50' for testing the wafer 50. The wafer socket 210 has a plurality of probes (p〇g〇pjns) 230 and a fixing mechanism 211. The plurality of probes 230 are disposed in the wafer socket 210 corresponding to the plurality of signal contacts 51 of the wafer 50. The pin 230 is in contact with the signal contact 51 of the wafer 50 wafer for testing of the wafer 50; the securing mechanism 211 is used to secure the wafer 50. The pick-and-place mechanism 228 is disposed above the wafer socket 210 for picking up and dropping the wafer 50. The pick-and-place mechanism 228 has a soft tip 221 and a release mechanism 222. The soft tip 221 sucks the wafer 50 by vacuum. The pick-and-place operation of the wafer 50 is performed, and the release mechanism 222 can release the fixing mechanism 211. In the present embodiment, the release mechanism 222 of the pick-and-place mechanism 228 includes a guide pin 223 ′. The fixing mechanism 211 includes at least one slider 212 and a spring 213 disposed at one end of the slider 212 for The slider 212 is pushed toward the wafer 50 such that the slider 212 can push the side of the top wafer 50 of the 201005312, thereby fixing the wafer 50; the slider 212 includes a positioning hole 214, and the guide pin 223 is inserted into the positioning. At the time of the hole 214, the slider 212 can be moved outward to release the clamping of the wafer 50 by the fixing mechanism 211. According to the embodiment, the sliders 212 are disposed on both sides of the wafer 50, but not limited thereto. The sliders 212 may also be disposed on the four φ circumferences of the wafer 50, and are fixed by pushing the sides of the wafer 50. The wafer 50. The second C diagram shows a cross-sectional view of the wafer 50 undergoing a system level test in the second A diagram. The wafer 50 is an image sensing electronic component. The upper surface of the wafer 50 has a photosensitive region 52. The lower surface of the wafer 50 has a plurality of signal contacts 51. In the wafer testing machine 200, the test steps of the wafer 50 are as follows: • First, the wafer 50 is moved above the wafer socket 210 by the vacuum suction of the pick-and-place mechanism 228; secondly, the guiding pin 223 is inserted into the positioning hole. 214, the slider 212 is moved outward to expose the space for accommodating the wafer 50; then, the pick-and-place mechanism 228 is moved downward to place the wafer 50 into the space for accommodating the wafer 50. At this time, the signal contact 51 of the wafer 50 is The corresponding probe 230 generates a contact; then, the wafer pick-and-place device 220 cancels the vacuum suction and moves upward, and the guide pin 223 is disengaged from the positioning hole 214. At this time, the 12201005312 slider 212 is pushed up by the spring 213, so that the slider The side edge of the ejector wafer 50 is 'fixed to the wafer 5'; finally, the test light source 225 disposed on the pressing mechanism 224 is moved over the photosensitive region 52 of the wafer 50, and a pressing operation is performed to cause the pressing mechanism 224 to The wafer socket 210 forms a sealed space for isolating external light, and the test light source 225 is provided with the light required for testing. The analog motherboard 60 performs a system for the wafer 50 of the image sensing electronic component. Level testing, according to embodiments the present case a square embodiment, the number of wafers to the wafer outlet 210 of the same number of pick and place device 220 'a plurality of receptacle 210 will not wait for the wafer pick and place apparatus idle wafer. . With the wafer testing machine of the present invention, the wafer socket is not interposed for waiting for the wafer pick-and-place device, so the efficiency of the test can be improved. Φ The above embodiments are merely for explaining the technical idea and features of the present invention, and the purpose thereof The scope of the present invention is to be understood by those skilled in the art, and the invention is not to be construed as limited by the scope of the invention. Within the scope of the present invention, it should be included in the scope of the following patent. 13 201005312 [Simplified Schematic] Figure 1A shows a side view of a conventional wafer tester for system level testing. The first B to the first D diagrams show schematic diagrams of the steps of the conventional system level test. Figure 2A is a cross-sectional view showing a wafer tester in accordance with a preferred embodiment of the present invention. The second B diagram shows an enlarged cross-sectional view of the second A diagram. Figure 2C shows a cross-sectional view of the wafer undergoing a system level test in Figure 2A. [Main component symbol description] 50 wafer 51 contact 52 photosensitive region 60 analog motherboard 70 pressing device 75 test light source 100 wafer tester 110 wafer socket 120 wafer pick and place device 121 soft tip 201005312 130 probe 200 wafer test machine 210 Wafer socket 211 fixing mechanism 212 slider 213 spring 214 positioning hole reference 220 wafer pick and place device 221 soft tip 222 release mechanism 223 guide pin 224 pressing mechanism 225 test light source 228 pick and place mechanism β 230 probe