201001681 ucuzuuy 27632twf.doc/n 九、發明說明： 【發明所屬之技術領域】 體封裝結構及其方法，且特 (image sensor chip)封裝結 本發明是有關於一種半導 別是有關於一種影像感測晶片 構及其方法。 【先前技術】 近年來由於多媒體的萚包旅 繁，相饼” m Γ 姆展，數位影像使用愈趨頻201001681 ucuzuuy 27632twf.doc/n IX. Description of the invention: [Technical field of invention] Body package structure and method thereof, and image sensor chip package The present invention relates to a semi-conductor related to an image sense Measuring the wafer structure and its method. [Prior Art] In recent years, due to the multimedia bag travel, the "cake" "m Γ um exhibition, the use of digital images has become more frequent
ί裝置的需求也愈來愈多。現今許 二數位衫像產σ口’包括電腦網路攝影機（web ca臆a)， 2照相機,(digitauamera)，甚至光學掃描器（賺ner) 及衫像電轉，皆是藉由影像感測器〇magese歸）來願 取影像。影像感測器包括電㈣合元件影像感測晶片 (CCD lmage sensor chip)及互補式金氧半導體影像感測 晶片（CMOS image sensorchip)等，可以靈敏地接收影物 (scene)所發出之光線，並將此光線轉換為數位訊號。由 於這些影像感測晶片需要接收光源，因此其封裝方式與一 般電子產品有所不同。 傳統影像感測晶片所使用的封裝技術大部分是採用 塑膠無接腳承載器封裝（Plastic Leadless Chip Carrier, PLCC )技術或是陶瓷無接腳承載器封裝（Ceramic Leadless Chip Carrier, CLCC)技術。以陶瓷無接腳承載器封裝技術 為例，傳統的影像感測晶片封裝結構是由一陶瓷基座、一 影像感測晶片及一玻璃蓋板所構成。影像感測晶片配置於 陶瓷基座上，並透過打線接合（wire bonding)使影像感測 5 201001681 0802009 27632tWf.doc/n :片與：究基座電性連接。此外’破璃蓋板組裝至赚 陶咖形成—封閉空間來容納影像感測晶片， 用則^影像_晶片及導線，而光_可穿過玻璃蓋板 而到達影像感測晶片。 【發明内容】 本發明提供-種影像感測晶片封裝結構，以減少影像 感測晶片封裝結構之體積與厚度。 本發明提供-種影像感測晶片封裳方法，可減少影像 感測晶片封裝結構之體積與厚度。 一本發明提出一種影像感測晶片封裝結構，其包括一透 光基板、一晶片、一密封環及多個導電柱。透光基板且有 =固貫孔。這些貫孔貫穿透光基板。晶片具有—主動面、 一影像感測區（image sensitive area)及多個晶片塾，其中 與這些晶片墊位於主動面。—密:環配置:晶 c ί之間，其中這些密封環包圍影像感_與這 二曰曰片塾。多辦電柱分魏置於這些貫·， 透過這些W墊與這些導紐電性連接。翅導電2分 別配置於這些晶牌上，這料電凸塊相連接這些導電 柱。 一 在本發明之一實施例中，上述之導電凸塊的材質包括 金。 、 在本發明之一實施例中，影像感測晶片封裝結構更包 括一導通層。導通層覆蓋這些貫孔。 ° 在本發明之一實施例中，上述之導通層的材質包括欽 6 201001681The demand for ί devices is also growing. Today's two-digit digital shirts, such as gamma-ports, include web ca臆a, 2 cameras, (digitauamera), and even optical scanners (earning ner) and shirts, which are powered by image sensors. 〇magese return) to take images. The image sensor includes a CCD lmage sensor chip and a complementary CMOS image sensor chip, and can sensitively receive light emitted by a scene. Convert this light into a digital signal. Since these image sensing wafers need to receive a light source, they are packaged in a manner different from that of a general electronic product. Most of the packaging technologies used in conventional image sensing wafers are based on Plastic Leadless Chip Carrier (PLCC) technology or Ceramic Leadless Chip Carrier (CLCC) technology. Taking the ceramic pinless carrier packaging technology as an example, the conventional image sensing chip package structure is composed of a ceramic base, an image sensing wafer and a glass cover. The image sensing chip is disposed on the ceramic base and is image-sensed by wire bonding. The film is electrically connected to the base. In addition, the 'glass cover is assembled to make a ceramic coffee--enclosed space to accommodate the image sensing wafer, and the image_wafer and wire are used, and the light_ can pass through the glass cover to reach the image sensing wafer. SUMMARY OF THE INVENTION The present invention provides an image sensing chip package structure to reduce the volume and thickness of an image sensing chip package structure. The invention provides a method for image sensing wafer sealing, which can reduce the volume and thickness of the image sensing chip package structure. An image sensing chip package structure includes a light transmissive substrate, a wafer, a sealing ring and a plurality of conductive pillars. The light-transmissive substrate has a fixed through hole. These through holes penetrate the light transmissive substrate. The wafer has an active surface, an image sensitive area, and a plurality of wafer cassettes, wherein the wafer pads are located on the active side. - Density: Ring configuration: between crystal c ί, where these seal rings surround the image sense _ with this two 塾 塾. A plurality of electric poles are placed in these places, and these W pads are electrically connected to these guides. The finned conductors 2 are disposed on the crystal plates, and the electric bumps are connected to the conductive pillars. In one embodiment of the invention, the material of the conductive bump comprises gold. In an embodiment of the invention, the image sensing chip package structure further includes a conductive layer. A conductive layer covers the through holes. In an embodiment of the invention, the material of the conductive layer includes Qin 6 201001681
OmiOW 27632tWf.d〇c/n 鶴及銅 本發明提出—種影像❹㈣縣方法# :板導，主於這些貫孔内。形成-密封環於透 的下矛面而：提供一晶片及將晶片的主動面朝向透光 透光基板，透光 透光基板而分別連接上表面及下表dOmiOW 27632tWf.d〇c/n Crane and copper The invention proposes a kind of image ❹(四)县方法# : plate guide, which is mainly in these through holes. Forming a sealing ring on the underlying surface of the lens: providing a wafer and directing the active surface of the wafer toward the light transmissive transparent substrate, and transmitting the transparent substrate to the upper surface and the lower surface respectively
二影像感測區及多個晶片#，其中影像感 ζ，、坆二日曰片墊位於主動面。形成多個導電凸塊，這些 -電凸塊分別配置於這些晶片墊上，用以分別連接這些導 電柱。將晶片的主動面朝向透絲板的下表面而組裝至透 光，板時，晶片透過這些晶片墊與這些導電柱電性連接， 且密封環包圍影像感測區與這些晶片墊。 在本發明之一實施例中，上述之形成多個導電柱之 前，更包括形成一導通層於這些貫孔内、透光基板的上表 面與下表面、形成多個柱狀體於這些貫孔内，其中這些柱 狀體分別填滿這些貫孔以及透過導通層而濺鍍及電鍍形成 一導電柱。 在本發明之一實施例中，上述之形成導通層的方式包 括減鑛（sputtering)。 在本發明之一實施例中，上述之導通層的材質包括鈦 鎢（TiW)及銅。 ' 在本發明之一實施例中，上述之形成多個導電柱於這 些貫孔内的步驟為形成一光阻層於金屬層上。對光阻層進 201001681 27632twf.doc/n 行曝光與顯影以形成—圖案化光阻層。㈣ =罩幕’_圖案化光阻層之外的金屬層了 二 == = :導通層的多個一 絲，上述之形成-密封環於透光Two image sensing areas and a plurality of wafers #, wherein the image is sensed, and the second day of the film is placed on the active surface. A plurality of conductive bumps are formed, and the electrical bumps are respectively disposed on the wafer pads for respectively connecting the conductive pillars. The active surface of the wafer is assembled to the lower surface of the light guide plate to be transparent. When the plate is passed, the wafer is electrically connected to the conductive posts through the wafer pads, and the sealing ring surrounds the image sensing region and the wafer pads. In an embodiment of the present invention, before forming the plurality of conductive pillars, the method further includes forming a conductive layer in the through holes, forming upper and lower surfaces of the transparent substrate, and forming a plurality of columnar bodies in the through holes. The columnar body fills the through holes and is sputtered and plated through the conductive layer to form a conductive pillar. In one embodiment of the invention, the manner in which the conductive layer is formed includes sputtering. In an embodiment of the invention, the material of the conductive layer comprises titanium tungsten (TiW) and copper. In one embodiment of the invention, the step of forming a plurality of conductive pillars in the through holes is to form a photoresist layer on the metal layer. The photoresist layer is exposed and developed to form a patterned photoresist layer. (4) = mask _ _ patterned metal layer other than the photoresist layer 2 == = : a plurality of wires of the conduction layer, the above formed - seal ring in the light
V 步驟為形成—支擇層於透光基板的 =表面上。圖案化支撐層，以形成—密封環於下表面的外 在本發明之一實施例中，上述之支撐 環丁烯（Benzocyclobutene, BCB )。 匕 質包$發明之一實施例中’上述之這些導電柱的末端材 在本發明之-實施例中，上述之透光基板的材質為玻 哨。 在本發明之—實關巾，上叙金屬層為—複合層。 ^層的㈣包括-鈦鶴層及—銅層或—鈦鎢層及一金 層。 *基於上述，本發明將晶片透過其晶片墊或晶片墊上的 ^電凸塊與透光基板的導電柱電性連接，故可節省傳統打 ^接合所需要的m 、影像制；封裝結構之 二體體積與厚度。另外’本發縣透光基板和晶片直接接 一以$成日日片尺寸封裝（Chip Size Package，CSP)，更 可達縮小影像感測晶片封裝結構之整體體積與厚度。 為讓本發明之上述和其他目的、特徵和優點能更明顯 8 201001681 27632twf.doc/n 易懂，下文特舉實施例，並配合所附圖式作詳細說明如 【實施方式】 卜。 圖1疋本發明之一實施例之一種影像感測晶片封裂結 構的示意圖。請參考圖卜本實施例之影像感測晶片^ 結構1〇〇包括一透光基板110、一晶片120、一密封環13^ 及多個導電柱140。透光基板110例如為一厚度為真 米的玻璃基板。透光基板11〇具有一上表面u〇a、—下^ 〇 面11〇b及多個貫孔112,且這些貫孔112貫穿透光基板m 以連接上表面ll〇a與下表面UOb。在本實施中，這些I 孔的直徑例如為0.1〜0.2毫米。 二貝 晶片120具有一主動面122、一影像感測區124及多 個晶片墊126，其中影像感測區124與這些晶片墊126位 於主動面122。在本實施例中，晶片12〇可為互補式金= 半導體（CMOS)影像感測晶片或是電荷耦合元件（cc 影像感測晶片。 ） 密封環130配置於晶片120與透光基板11〇之間，且 U 包圍影像感測區124與這些晶片墊126。密封環與曰 片12〇及透光基板110形成一封閉空間，以保護晶片I]。 的影像感測區124。在本實施例中，密封環13〇的材料例 如為苯環丁烯（BCB)。 '' 這些導電柱140分別配置於這些貫孔112内，其中晶 片120透過這些晶片墊126與這些導電柱14〇電性連接。 在本實施例中，導電柱140的末端材料為金。 在本實施例中’影像感測晶片封裝結構1〇〇更包括多 9 201001681 va\jz.\jOy 27632twf.doc/n 個導電凸塊180。這些導電凸塊180分別配置於這些晶片 墊126上，且這些導電凸塊180分別連接這些導電柱140。 在本實施例中，導電凸塊180的材質為金，其厚度例如為 10〜20微米。此外’導電凸塊180與導電柱140的材質可 選擇相同’或者，導電凸塊180的材質可以選擇鮮料 (solder)(例如錫或錫錯），使得晶片12〇與透光基板 Π0之間具有良好的接合可靠度。 簡言之，本實施例之影像感測晶片封裝結構1〇〇，其 晶片120的這些晶片墊126上之導電凸塊18〇與透光基板 1+10之這些導電柱14〇電性連接，可節省傳統打線接合所 兩要的空間，且透光基板11〇和晶片12〇直接接合，形成 晶片尺寸封裝(CSP)，因此影像感測晶片封裝結構10〇之 體積與厚度能夠縮小。最終，影像感測晶片封裝結構1〇〇 二藉由這些導電柱140之相對較遠離晶片120的末端來連 接—可撓性電路板200。The V step is to form a selective layer on the surface of the light-transmissive substrate. Patterning the support layer to form a seal ring on the lower surface. In one embodiment of the invention, the above supports Benzocyclobutene (BCB). In one embodiment of the invention, the end material of the conductive pillars described above is in the embodiment of the invention, wherein the light transmissive substrate is made of a glass. In the present invention, the metal layer is a composite layer. The layer (4) includes a titanium layer and a copper layer or a titanium tungsten layer and a gold layer. * Based on the above, the present invention electrically connects the wafer through the pad of the wafer pad or the pad of the wafer and the conductive column of the transparent substrate, so that the m and image systems required for the conventional bonding can be saved; Body volume and thickness. In addition, the local light-transmissive substrate and wafer are directly connected to a chip size package (CSP), which can reduce the overall volume and thickness of the image sensing chip package structure. The above and other objects, features, and advantages of the present invention will become more apparent. 8 201001681 27632 twf.doc/n is easy to understand, and the following specific embodiments are described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic illustration of an image sensing wafer sealing structure in accordance with one embodiment of the present invention. The image sensing wafer structure 1 of the present embodiment includes a transparent substrate 110, a wafer 120, a sealing ring 13^, and a plurality of conductive pillars 140. The light-transmitting substrate 110 is, for example, a glass substrate having a thickness of true rice. The transparent substrate 11A has an upper surface u〇a, a lower surface 11b and a plurality of through holes 112, and the through holes 112 penetrate the transparent substrate m to connect the upper surface 11a and the lower surface UOb. In the present embodiment, the diameter of these I holes is, for example, 0.1 to 0.2 mm. The die 120 has an active surface 122, an image sensing region 124 and a plurality of wafer pads 126, wherein the image sensing regions 124 and the wafer pads 126 are located on the active surface 122. In this embodiment, the wafer 12A can be a complementary gold=semiconductor (CMOS) image sensing wafer or a charge coupled device (cc image sensing wafer). The sealing ring 130 is disposed on the wafer 120 and the transparent substrate 11 And U surrounds image sensing region 124 and these wafer pads 126. The sealing ring forms a closed space with the cymbal 12 〇 and the transparent substrate 110 to protect the wafer I]. Image sensing area 124. In the present embodiment, the material of the seal ring 13 is, for example, benzocyclobutene (BCB). The conductive pillars 140 are disposed in the through holes 112, and the wafers 120 are electrically connected to the conductive pillars 14 through the wafer pads 126. In this embodiment, the end material of the conductive post 140 is gold. In the present embodiment, the image sensing chip package structure 1 further includes a plurality of 9201001681 va\jz.\jOy 27632twf.doc/n conductive bumps 180. The conductive bumps 180 are respectively disposed on the wafer pads 126, and the conductive bumps 180 are respectively connected to the conductive pillars 140. In this embodiment, the conductive bump 180 is made of gold and has a thickness of, for example, 10 to 20 μm. In addition, the materials of the conductive bumps 180 and the conductive pillars 140 may be selected the same. Alternatively, the material of the conductive bumps 180 may be selected from a solder (for example, tin or tin) so that the wafer 12 is separated from the transparent substrate Π0. Has good joint reliability. In short, in the image sensing chip package structure of the embodiment, the conductive bumps 18 on the wafer pads 126 of the wafer 120 are electrically connected to the conductive pillars 14 of the transparent substrate 1+10. The space required for the conventional wire bonding can be saved, and the transparent substrate 11A and the wafer 12 are directly bonded to form a chip size package (CSP), so that the volume and thickness of the image sensing chip package structure 10 can be reduced. Finally, the image sensing chip package structure 2 is connected by the ends of the conductive pillars 140 relatively far from the wafer 120 - the flexible circuit board 200.
O 曰圖2至圖Η繪示本發明之一實施例之一種影像感測 ;2方法。請先參考圖2，依照本實施_影像感測 首先’提供-透綠板H0。絲基板110 及多個於上表面的-下表面ιι% ,4二貝孔112貫穿透光基板110而連接 上表面110a及下表面11%。 安 内、j考圖3，接著，形成導通層160於這些貫孔112 通展板11G的上表面⑽與下表面議，其中導 6G的方式可為崎，其材料可紐鎢及銅，而其厚 201001681 um^w 27632twf.doc/n 度例如分別為800〜1000埃及2000〜3000埃。 請參考圖4,接著，以真空印刷方式將環氧樹脂物㈣ ，入廷些貫孔112内且完全塞滿，形成多個柱狀體14〇,。 詳細而言，這些柱狀體M〇,分別配置於這些貫孔112内， 且這些柱狀體140,的兩端與形成於透光基板11〇的上表面 110a與下表面110b的導通層16〇實值上切齊。 請參考圖5，接著，在柱狀體⑽，完成後，透過導通 層160，於透光基板11〇的上表面u〇a與下表面11卯以 雜及電财式形成金制15G，其中金屬層⑽的材料 可為鈦鎢及金’而金屬層15〇的厚度例如分縣_〜麵 埃及1〜3微米。FIG. 2 to FIG. 2 illustrate an image sensing method according to an embodiment of the present invention; Referring first to Figure 2, in accordance with the present embodiment, image sensing first provides a transparent green plate H0. The silk substrate 110 and a plurality of lower surfaces of the upper surface and the lower surface of the upper surface 110a are connected to the upper surface 110a and the lower surface by 11%. An inner, j test 3, then, a conductive layer 160 is formed on the upper surface (10) of the through hole 112 through the upper surface (10) and the lower surface, wherein the way of guiding the 6G may be Saki, the material of which may be tungsten and copper, and Thick 201001681 um^w 27632twf.doc/n degrees are respectively 800~1000 Egypt 2000~3000 angstroms. Referring to FIG. 4, the epoxy resin (4) is then vacuum-printed into the through-holes 112 and completely filled to form a plurality of columnar bodies 14〇. Specifically, the columnar bodies M〇 are disposed in the through holes 112, and both ends of the columnar bodies 140 and the conduction layer 16 formed on the upper surface 110a and the lower surface 110b of the transparent substrate 11A are formed. The value is consolidated. Referring to FIG. 5, after the completion of the columnar body (10), through the conductive layer 160, a gold 15G is formed on the upper surface u〇a and the lower surface 11 of the transparent substrate 11 The material of the metal layer (10) may be titanium tungsten and gold 'and the thickness of the metal layer 15 例如 is, for example, divided into counties _ ~ face Egypt 1 to 3 microns.
接著，圖案化上述金屬層150。首先，請先同時 圖6與圖7，藉由形成一光阻層170於金屬層15〇上，並 對光阻層17G進行曝光與顯影以形成-圖案化光阻層 170。接著，請同時參考圖7與圖8，以圖案化光阻層口 為钱刻罩幕，侧®案化光阻層170,之外的金屬層15〇， 之後’移除圖案化光阻層17〇，。最後，請同時參考圖9與 圖10,移除導通層160的多個分別位於透光基板11〇的上 表面110a與下表面脑的部分。至此，由部份金屬層 150、導通層16〇以及柱狀體14〇，所組成的導電柱二 致形成。 八 請同時參考圖U與圖12，接著’形成一密封環 =透光基板110之下表面11%。在本實施例中，為了 密封知、130 ’首先，形成一支樓層130,於透光基板U〇的 201001681 27632twf.doc/n 下表面110b上’接著’圖案化支撐層13〇,，以一穷 ^!30於下表面11%的外圍。在本實施例中，支^ 的材料可為苯環丁烯（BCB)，其厚度例如為15〜25 微米。Next, the metal layer 150 is patterned. First, please simultaneously form a patterned photoresist layer 170 by forming a photoresist layer 170 on the metal layer 15 and simultaneously exposing and developing the photoresist layer 17G. Next, please refer to FIG. 7 and FIG. 8 at the same time, to pattern the photoresist layer as a mask, and to smear the photoresist layer 170, and then to remove the patterned photoresist layer. 17〇,. Finally, referring to FIG. 9 and FIG. 10 simultaneously, a plurality of portions of the conductive layer 160 which are respectively located on the upper surface 110a and the lower surface of the transparent substrate 11A are removed. Thus, a conductive pillar composed of a part of the metal layer 150, the conductive layer 16A, and the columnar body 14 is formed. 8. Please refer to FIG. U and FIG. 12 at the same time, and then 'form a sealing ring=11% of the lower surface of the transparent substrate 110. In the present embodiment, in order to seal, 130' firstly, a floor 130 is formed, and the support layer 13 is finally patterned on the lower surface 110b of the 201001681 27632twf.doc/n of the transparent substrate U〇. Poor ^! 30 on the outer surface 11% of the periphery. In this embodiment, the material of the support may be benzocyclobutene (BCB) having a thickness of, for example, 15 to 25 μm.
f考圖13,提供—晶片12()。在本實施例中，晶片 /、有—主動面122、—影像感測區124及多個晶片墊 =’其土影像感測區m與這些晶片塾⑶位於主動面 接著^成多個導電凸塊18〇，這些導電凸塊⑽分 Γ。置^這些晶片塾126上，用以分別連接這些導電柱 >圖14，最後，將晶片120的主動面122朝向透 厂二,m的下表面UGb並利用晶圓對晶圓接著（Wafer =aerBGndmg)方式來組裝，其中晶片12()透過這些晶 12^上的這些導電凸塊18〇與這些導電柱⑽電性連 接，且這些密封環130包圍影像感測區124與這些晶片墊 126至此，景>像感測晶片封裝結構100A大致完成。 ♦ 、’'τ、上所述，本發明將晶片透過晶片墊或晶片墊上的導 电凸塊與透光基板之貫制的導電柱紐賴，故可節省 所需要的空間，進而縮小影像感測晶片封裝 正體體積與厚度。同時，由於透光基板與晶片不需 、二^瓷基座上的線路，而是以導電柱進行訊號傳遞， 因此可簡化影像感測晶片封裝結構的電路佈局。 雖然本發明已以實施例揭露如上，然其並非用以限定 4·二月任何所屬技術領域中具有通常知識者，在不脫離 之精神和範圍内，當可作些許之更動與潤飾，故本 叙月之保魏HJ當視後附之申請專利範圍所界定者為準。 12 27632twf.doc/n 201001681 【圖式簡單說明】 圖1是本發明之一實施例之一種影像感測晶片封裝結 構的不意圖。 圖2至圖14繪示本發明之一實施例之一種影像感測 晶片封裝方法。 【主要元件符號說明】 100、100A :影像感測晶片封裝結構 110 :透光基板 110a :上表面 110b :下表面 112 :貫孔 120 :晶片 122 :主動面 124 :影像感測區 126 :晶片墊 130 :密封環 130’ ：支撐層 140’ ：柱狀體 140 :導電柱 150 :金屬層 160 :導通層 170 :光阻層 170’ ：圖案化光阻層 180 :導電凸塊 200 :可撓性電路板 13f. Figure 13, providing - wafer 12 (). In this embodiment, the wafer/, the active-surface 122, the image sensing region 124, and the plurality of wafer pads=the soil image sensing region m and the wafers (3) are located on the active surface and then formed into a plurality of conductive bumps. At block 18, these conductive bumps (10) are branched. The wafers 126 are disposed to connect the conductive pillars respectively. FIG. 14 , and finally, the active surface 122 of the wafer 120 is directed to the lower surface UGb of the substrate 2, m, and wafer-to-wafer is used (Wafer = The aerBGndmg) method is assembled, wherein the wafer 12() is electrically connected to the conductive pillars (10) through the conductive bumps 18 of the crystals, and the sealing rings 130 surround the image sensing regions 124 and the wafer pads 126. The landscaping image sensing package 100A is substantially completed. ♦, ''τ, as described above, the present invention transmits the wafer through the conductive bumps on the wafer pad or the wafer pad and the conductive pillars of the transparent substrate, thereby saving space required and reducing image perception. Measure the normal volume and thickness of the wafer package. At the same time, since the transparent substrate and the wafer do not need the wires on the ceramic pedestal, but the conductive columns are used for signal transmission, the circuit layout of the image sensing chip package structure can be simplified. Although the present invention has been disclosed in the above embodiments, it is not intended to limit the general knowledge of any of the technical fields of the present invention, and may be modified and retouched without departing from the spirit and scope. The term of the application for patents attached to Wei HJ is subject to the definition of the patent application scope. 12 27632twf.doc/n 201001681 [Simplified Schematic] FIG. 1 is a schematic diagram of an image sensing chip package structure according to an embodiment of the present invention. 2 to 14 illustrate an image sensing chip packaging method according to an embodiment of the present invention. [Main component symbol description] 100, 100A: image sensing chip package structure 110: transparent substrate 110a: upper surface 110b: lower surface 112: through hole 120: wafer 122: active surface 124: image sensing region 126: wafer pad 130: seal ring 130': support layer 140': columnar body 140: conductive pillar 150: metal layer 160: conductive layer 170: photoresist layer 170': patterned photoresist layer 180: conductive bump 200: flexible Circuit board 13