TW201001671A - Semiconductor device and semiconductor integrated circuit device - Google Patents
Semiconductor device and semiconductor integrated circuit device Download PDFInfo
- Publication number
- TW201001671A TW201001671A TW098109600A TW98109600A TW201001671A TW 201001671 A TW201001671 A TW 201001671A TW 098109600 A TW098109600 A TW 098109600A TW 98109600 A TW98109600 A TW 98109600A TW 201001671 A TW201001671 A TW 201001671A
- Authority
- TW
- Taiwan
- Prior art keywords
- power supply
- wiring
- internal circuit
- circuit
- potential
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 214
- 230000002093 peripheral effect Effects 0.000 claims abstract description 160
- 239000010410 layer Substances 0.000 claims description 16
- 230000009467 reduction Effects 0.000 claims description 16
- 230000003071 parasitic effect Effects 0.000 claims description 15
- 239000004020 conductor Substances 0.000 claims description 10
- 230000000694 effects Effects 0.000 claims description 10
- WYTGDNHDOZPMIW-RCBQFDQVSA-N alstonine Natural products C1=CC2=C3C=CC=CC3=NC2=C2N1C[C@H]1[C@H](C)OC=C(C(=O)OC)[C@H]1C2 WYTGDNHDOZPMIW-RCBQFDQVSA-N 0.000 claims description 9
- 239000003990 capacitor Substances 0.000 claims description 7
- 238000010586 diagram Methods 0.000 claims description 7
- 239000011229 interlayer Substances 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 7
- 230000005611 electricity Effects 0.000 claims description 6
- 230000004044 response Effects 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 229910052793 cadmium Inorganic materials 0.000 claims description 2
- 210000000707 wrist Anatomy 0.000 claims description 2
- 229910000859 α-Fe Inorganic materials 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 3
- 241000283690 Bos taurus Species 0.000 claims 2
- 230000008859 change Effects 0.000 claims 2
- 239000000126 substance Substances 0.000 claims 2
- 241000251468 Actinopterygii Species 0.000 claims 1
- 241000282320 Panthera leo Species 0.000 claims 1
- 239000013078 crystal Substances 0.000 claims 1
- 239000000839 emulsion Substances 0.000 claims 1
- 238000007689 inspection Methods 0.000 claims 1
- 235000012054 meals Nutrition 0.000 claims 1
- 239000002184 metal Substances 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 claims 1
- 238000012986 modification Methods 0.000 claims 1
- 230000004048 modification Effects 0.000 claims 1
- 150000004767 nitrides Chemical class 0.000 claims 1
- 239000000377 silicon dioxide Substances 0.000 claims 1
- 239000000779 smoke Substances 0.000 claims 1
- 239000002689 soil Substances 0.000 claims 1
- 238000006467 substitution reaction Methods 0.000 claims 1
- 239000012535 impurity Substances 0.000 description 3
- 241000287828 Gallus gallus Species 0.000 description 1
- 235000009827 Prunus armeniaca Nutrition 0.000 description 1
- 244000018633 Prunus armeniaca Species 0.000 description 1
- 238000012217 deletion Methods 0.000 description 1
- 230000037430 deletion Effects 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 244000144972 livestock Species 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 235000013372 meat Nutrition 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
201001671 六、發明說明： 【發明所屬之技術領域】 本發明涉及半導體裝置以及半導體積體電路裝置，尤其涉及 具有内部電路和週邊電源配線的半導體裝置以及半導體積^ ^路 裝置。 、 【先前技術】 目前，已知一種具備電阻電容(RC)濾波器和電路部的半導體 ^ 裝置，其中，所述RC濾波器由配線間電容和配線電阻形成，該配 線間電容被設置在形成於電介質層上作為最上位配線的電源配 線、和作為與電源配線分離形成的最上位配線層的接地配線之 間，，配線電阻由電源配線以及接地配線構成；所述電路部，使 用在隶上位配線下層的配線連接電路以及元件，經由導通孔 =電源配線與高電位電源魏連接，經由導通孔將接地 源魏連接，在解雜裝置中，通過由寄生阻以 及電谷構成的RC濾波器，降低電磁波干擾（meetR)Magnetic 令龄=EMI)雜戒’同時抑制晶圓面積的增大（例如參照專利 【專利文獻1】特開2006—196803號公報 而’在上述專利文獻1記載的結構中存在以下問題：在平 波器發中 = 接二電路部，因此存在無法使_ 部。 、刀存在無法得到足夠的EMI雜訊降低的電路 f外’在專利文獻i記載 一 ^ 效果的RC驗器。因此路部獨立地形成發揮最大 可連接的錄連接，顧m壯的料孔健似慮波器的 低。 雞對於各個電路部實現足夠的EMI雜訊降 201001671 【發明内容】 因此’本發明的目的在於，提供 積體電路裝置，具有最錄;置以及+導體 形。 倾观魏發揮EMI雜瓣低效果的配線圖 為了達成上述目的’本發明第1方 〜麵）具有：内部電路（1〇、1〇二=、繼置⑽、100a 雷敗Πη、1〜、ΐς 15〜18);配置在比該内部BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a semiconductor integrated circuit device, and more particularly to a semiconductor device having an internal circuit and peripheral power supply wiring, and a semiconductor integrated circuit device. [Prior Art] At present, a semiconductor device including a resistor-capacitor (RC) filter and a circuit portion is known, wherein the RC filter is formed by an inter-wiring capacitance and a wiring resistance, and the inter-wiring capacitance is set in formation. The wiring resistance is composed of a power supply wiring and a ground wiring between the power supply wiring which is the uppermost wiring on the dielectric layer and the ground wiring which is the uppermost wiring layer which is formed separately from the power supply wiring; and the circuit portion is used in the upper position. The wiring connection circuit and the component under the wiring are connected to the high-potential power supply via the via hole=power supply wiring, and the ground source Wei is connected via the via hole, and the RC filter composed of the parasitic resistance and the electric valley is used in the impurity removing device. In the structure described in the above Patent Document 1, the electromagnetic wave interference (meetR) is reduced in the structure of the above-mentioned Patent Document 1 (see, for example, JP-A-2006-196803). There is the following problem: In the flat waver, the second circuit part is connected, so there is no way to make the _ part. The EMI noise reduction circuit f is external to the RC detector in the patent document i. Therefore, the road portion is independently formed to play the maximum connectable recording connection, and the material of the hole is as low as the filter. Chicken achieves sufficient EMI noise reduction for each circuit unit 201001671 [Invention] Therefore, the object of the present invention is to provide an integrated circuit device having the most recorded and placed + conductor shape. In order to achieve the above object, the wiring diagram of the effect has an internal circuit (1〇, 1〇2=, relay (10), 100a, 1η, 1~, ΐς15~18); Than the interior
Pd1 ，、〜）罪外側、與外部連接用的電源端子墊（Pdv、 電===也:子ΐ (峋、_、剛連接、舰 電源电位以及接地電位的週邊電源配線（2()、观、 Π〇、1〇C、15〜18)和所述週邊電源配線（2〇^Μ 1 Π〇 〇 (2° ' ^ ' 20e) 给用配绫^給所返電源電位的内部電路電源電位供 S電位^用配線a(、32 ^2以^共f所述接地電位的内部電路接 二“一用配線（32'32a〜32e)，該半導體裝置（1〇〇、施 = 100d)的特徵在於，所述内部電路電源電位供給用配線⑶、 31a〜31e)和所述内部電路接地電位供給用配線（32、32a〜32 接近地配置以產生配線間電容（c、Ca〜Ce)，與所述内部電路 (10、10c、15〜18)的連接點（Yv、Yvl、Yv2、Yg、外卜 以及與所述週邊電源配線（20、2〇d、2〇e)的連接點（χν、χνΐ、 Xv2、Xg、Xg卜Xg2)分別僅為一個部位。 由此、，可以使與内部電路連接的電源配線發揮降低EMI雜訊 的作用，並且可以固疋向内部電路供給電流的路徑，並可靠 低EMI雜訊。 第2方式的特徵在於，在第1方式的半導體裝置（1〇〇、丨〇如 〜io〇d)中’所述内部電路電源電位供給用配線（31、31a〜3ie) 以及所述内部電路接地電位供給用配線（32、32a〜32e)是比所 述週邊電源配線(20、20d、20e)線寬度細、長度長的配線，通過配 線電阻（Rv、Rva〜Rve、Rg、Rga〜Rge)和所述配線間電容（c、 Ca〜Ce)構成RC遽波器。 4 201001671 度^揮RC驗器可祕通過該RC攄波器，可以最大限 lOOa^Ufi概在於，在第1或第2方式的半導體*置（1〇〇、 所、求內邱所述内部電路電源電位供給用配線（31)以及 的接ϋν、Y，位供給用配線（32)，在與所述内部電路（10) Υ、μ 以及與所述週邊電源配線（20)的連接點（Χν、Pd1,, ~) sin outside, power terminal pad for external connection (Pdv, electric === also: sub-ΐ (峋, _, just connected, ship power potential and ground potential peripheral power wiring (2 (), View, Π〇, 1〇C, 15~18) and the surrounding power supply wiring (2〇^Μ 1 Π〇〇 (2° ' ^ ' 20e) is used to supply the internal circuit power supply to the power supply potential The potential for the S potential is connected to the internal circuit of the ground potential by the wiring a (, 32^2), and the "one-use wiring (32'32a to 32e), the semiconductor device (1〇〇, 施=100d) The internal circuit power supply potential supply wirings (3) and 31a to 31e) and the internal circuit ground potential supply wirings (32, 32a to 32 are arranged close to each other to generate inter-wiring capacitance (c, Ca to Ce). Connection points with the internal circuits (10, 10c, 15 to 18) (Yv, Yvl, Yv2, Yg, outer and connection points with the peripheral power wiring (20, 2〇d, 2〇e) (χν, χνΐ, Xv2, Xg, Xg Bu Xg2) are only one part. This allows the power supply wiring connected to the internal circuit to reduce EMI noise. Further, it is possible to provide a path for supplying current to the internal circuit and to reliably reduce EMI noise. The second aspect is characterized in that the semiconductor device of the first aspect (1, for example, io 〇d) The internal circuit power supply potential supply wirings (31, 31a to 3ie) and the internal circuit ground potential supply wirings (32, 32a to 32e) are thinner than the peripheral power supply wirings (20, 20d, 20e). The wiring having a long length constitutes an RC chopper by wiring resistances (Rv, Rva, Rve, Rg, Rga to Rge) and the inter-wiring capacitance (c, Ca to Ce). 4 201001671 Degrees RC Detector is secret The RC chopper can be used for the semiconductor circuit of the first or second aspect, and the internal circuit power supply potential wiring (31) and the inner circuit power supply potential supply line (31). The connection ν, Y, the bit supply wiring (32), the connection point with the internal circuit (10) Υ, μ, and the peripheral power supply wiring (20) (Χν,
Xg)間’各自構成了並聯電路。 由此’可以幾乎不使供給的電源賴降低地實 現EMI雜訊的 降低。Each of Xg) constitutes a parallel circuit. Thus, it is possible to achieve a reduction in EMI noise with little reduction in the supplied power supply.
議第H式，徵在於，在第1或第2方式的半導體裝置（100、 二+)中’所述内部電路電源電位供給用配線（31a〜31e) 以J所，畴電路接地電位供給用配線㈤〜則，在與所述内 J 丄15 M)的連接點（Yv、Yg) *與所述週邊電源配 、、’ 、20e)的連接點（Xv、Xvl、Xv2、Xg、Xgl、Xg2) 之間，各自構成了 RC分佈常數電路。 由此，向内部電路供給的電力全部在經過迎^〗雜訊應對用的 電路被提供給⑽t路，雜訊麟之t路充分發揮作 用0 第5方式的特徵在於，在第4方式的半雜裝置（綱&〜ι〇⑹ 中’以螺錄地®繞所勒部電路（1G)的顺的方式來配置所 述RC分佈常數電路。 由此，可以將RC分佈常數電路的路徑設置得較長，在節省空 間的巧時，可以使EMI雜訊降低之應對充分地發揮作用。 第6方式的特徵在於，在第4方式的半導體裝置〇⑻、㈨ 〜100d)中’與所述週邊電源配線（2〇)相鄰地配置所述内部電 路（10b、l〇c、15、16)，所述Rc分佈常數電路蛇形地配置°在與 所述内部電路（l〇b、l〇c、15、16)的連接點（YV、Yg)和與^ 述週邊電源配線（20)的連接點（χν、Xg)之間。 ” 由此，即使在靠近半導體裝置的一侧來配置内部電路時，也 5 .201001671 =將鶴'崎的路餘置雜長，可歧錄進行顧雜訊的 體穿i 特徵在於’在第1至第6的任意—種方式的半導 筱戒置U00、i〇0a〜1〇〇d)中，具有多個所述内部電路（15、， 〇5、16)間彼此進行了用於供給所述電源電位以 及所述接地電位的連接。 炉，即使存在多侧部電路時，也可關定電源配線的路 二並且充分地進行ΕΜΙ雜訊之應對。 胁壯ί 8,方式的特徵在於，在第1至第6的任意一種方式的半導 1(K)a〜1(K)d)中’具有被供給的所述電源電位不同 =個所相部電路⑴、18)，對應於多個所述内部電路〇7、 砧獨立地設置所述電源端子墊（Pdv：l、Pdv2)以及所述接 内部jiP=、Pdg2)、所述週邊電源配線⑽、20e)、所述 电源笔供給用配線（31d、31e)以及所述内部電路接 地電位供給用配線（32d、32e)。 設置了多個内部電路、需要獨立的電源供給時，通 電路進行EMI雜訊之應對，可以使設置的EM!雜訊 應對路分別充分發揮作用，可以有效地抑制EMI雜訊。 Μ 徵在於，在第1至第7的任意—種方式的半導 iG、1GGa、_)中，在相互最接近地配置的所述電源 、胁2)以及所述接地端子墊⑽，卜 、寸近，设置所述内部電路電源電位供給用配線（31、31& 及戶斤述内部電路接地電位供給用配線⑶、32a〜32e) ^所^邊電源配線（2G、2Gd、2Ge)的 、χν1 xg、Xgl、Xg2)。 、、諸f Γ以簡單地構成輸人輸出電路，emi雜訊應對用的電 源配線的配置也變得容易。 ％ 式的半導體積體電路裝置（1〇〇、腕〜_)的特 至第9的任意―種方式的半導體裝置⑽、勵 〜100d) ’该半導體裝置被封裝。 6 201001671 番3 ΐ並Z以向用戶提供降低EMI雜訊的半導體積體電路裝 量以及ί短將可_減部件數 守髖積體电路裝置作為部件的其他產品的開發時 間0 此外：上述括弧内的參照符號是為了易於理解加 疋一例，亚不限定於圖示的形態。 m 果， 【實施方式】 ίί施’說·於實施本發明的最佳方式。 圖的的半導體裝置議的整體結構 40上具有‘電路1〇^^^1〇〇心在，體晶圓(―） i 和謂朗 給用=31和_^===2部蝴源電位供 内部電路10是具有半導體# ¥ 1〇 4ίϊϊ^〇Τ ° 給接地電位的内部雜σ卩電路電魏線11、和應該供 電源配線11以及内邱雷政^’ 4。内部電路10通過向内部電路 行預定的^ 接地崎12供給電力而進行動作，執 置端子墊pdg是用於進行與半導體裝 f過攸外部電源向電源端 ^^體裝置100 力，來進行半導體裝置1〇〇 塾Pdg供給電 即冋电位側的電位。另一方面，對接地端子墊^ 201001671 供給接地電位的o[v]、即低電位側的電位。 在半導體裝置100内可以配備多個電源端子墊Pdv以及接地 端子墊Pdg。為了不產生由於半導體裝置1〇〇内的位置而導致的不 均衡地、向半導體裝置100均勻地供給電力，最好儘量沿著半導 體裝置100的週邊等間隔地對稱地配置電源端子墊Pdv以及接地 端子墊Pdg。因此，為了進行均勻的電力供給，可以配備多個電源 端子塾Pvd以及接地端子墊Pdg。 電源端子墊Pdv以及接地端子墊Pdg，只要比内部電路1〇靠 外側，則可以配置在任何位置，但為了容易與外部電源連接，最 好設置在半導體裝置100的週邊邊緣附近。由此，可以縮短外部 電源與半導體裝置100的連接配線，另外還可以廣泛地使用半導 體裝置100。 ^ 週邊電源配線20是用於使得可以將提供給分散設置的電源端 子墊Pdv以及接地端子墊Pdg的電力，提供給半導體裝置1〇〇内 邛全體的電源供給用配線。因此，週邊電源配線與電源端子藝 Pdv以及接地端子墊Pdg連接。週邊電源配線2〇具備：供給電源 電位的電源電位用週邊電源配線21、和供給接地電位的接地電位 用週邊電源配線22。電源電位用週邊電源配線21與電源端子墊 Pdv連接，接地電位用週邊配線22與接地端子墊pdg連接。 週邊電源配線20是用於向内部電路丨〇供給電力的配線，因 置在㈣部電路1()靠外側，理想的是如圖1所示，沿著半 ΪίΪΪ⑽的週邊來配置。週邊電源配線2G具以下效果：作為 罢1ΠΛ破置1〇0内的電源供給配線，成為容易利用從在半導體裝 #的表面分散配置地設置的電源端子墊PdV以及接地端子墊 m的電_配置。因此，理想岐將猶電祕線2〇配置 及接地端子墊pdg的附近、並且易於進行向 20例如^源（、給的位置。考慮這樣的問題，週邊電源配線 與内部電二所示，在電源端子整_ “及接地端子塾响 pdg儘量外側的週i位配置置在接近電源軒墊_狀接地端子塾 .201001671 而起St Jii:蚩二:為半導體裝置100内的電源供給線 ^巧度大到_程度的配線卿 用電力供給的損耗小的配線。賴I、體地破设疋，但最好應 另外’週邊電源配線20也被用作向輸 100 ;的 電 i：^T,T20 10 電:電路10供給電源電位的内部電路Ϊ源 地電位^用配線3、2 iri電路10供給接地電位的内部電路接 以=:=配線32與_~== 内部路電源電位供給用配線31與内部電路10的 相連，内部電路接地電位供給用配線3 Ϊ 3 S路10的内部電路接地配線12相連。於是，^^ 電力配線^ 用配=電=====以及内部電路接地電位供給 器而作用，導體裝置100内ΕΜΙ雜訊的Rc據波 用配m電=電位供'給用配線31以及内部電路接地電位供給 内部電路^ Rc m、所需要的電阻成分。如圖1所示， t 給用配線31具有電阻Rv的寄生電阻。另外， ^及#供_碟32具有雜抑料生電阻電L 及電阻Rg，不特別設置個別的電阻體，而是内部電路電^ 9In the semiconductor device (100, 2+) of the first or second aspect, the internal circuit power supply potential supply wirings (31a to 31e) are provided by J, and the domain circuit ground potential is supplied. Wiring (5)~, at the connection point (Yv, Yg) with the inner J 丄 15 M) * connection point with the peripheral power supply, ', 20e) (Xv, Xvl, Xv2, Xg, Xgl, Between Xg2), each constitutes an RC distributed constant circuit. As a result, all the electric power supplied to the internal circuit is supplied to the (10)t road through the circuit for responding to the noise, and the noise path is fully utilized. The fifth mode is characterized by the half of the fourth mode. The RC distributed constant circuit is configured in a manner in which the RC distributed constant circuit is disposed in a singular manner in the splicing device (1G). In the semiconductor device (8), (9) to 100d) of the fourth aspect, the sixth embodiment is characterized in that it is sufficient to reduce the EMI noise. The internal power circuit (2〇) is disposed adjacent to the internal circuit (10b, 10c, 15, 16), and the Rc distributed constant circuit is arranged in a serpentine manner with the internal circuit (l〇b, l) The connection point (YV, Yg) of 〇c, 15, 16) and the connection point (χν, Xg) with the peripheral power supply wiring (20). Thus, even if the internal circuit is placed on the side close to the semiconductor device, it is also 5.201001671=The road of the crane's road is miscellaneous, and the body can be misinterpreted. In any of the first to sixth modes, the semi-conducting ring U00, i〇0a to 1〇〇d) has a plurality of the internal circuits (15, 〇5, 16) used for each other. The connection between the power supply potential and the ground potential is supplied. Even if there is a multi-side circuit, the furnace can be set to the second of the power supply wiring and fully cope with the noise. In the semiconductors (K) a to 1 (K) d) of any one of the first to sixth embodiments, the power supply potentials that are supplied are different from the phase circuits (1) and 18), corresponding to a plurality of the internal circuits 、7, anvil independently providing the power terminal pads (Pdv:1, Pdv2) and the internal jiP=, Pdg2), the peripheral power wirings (10), 20e), the power supply pen Supply wirings (31d, 31e) and the internal circuit ground potential supply wirings (32d, 32e). When the circuit and the independent power supply are required, the EMI noise can be handled by the circuit, and the EM! noise response path can be fully utilized to effectively suppress the EMI noise. 征 The code is in the first to the first In the semiconductor-type, the power supply, the threat 2) and the ground terminal pad (10) which are disposed closest to each other in any of the seven types of semiconductors, the internal circuit power supply is provided. The potential supply wirings (31, 31 & and the internal circuit ground potential supply wirings (3), 32a to 32e) χ ν1 xg, Xgl, Xg2) of the power supply wirings (2G, 2Gd, 2Ge). In addition, it is easy to configure the power supply wiring for the EMI noise response. The semiconductor integrated circuit device (1〇〇, wrist~_) is the ninth. Any type of semiconductor device (10), excitation ~ 100d) 'The semiconductor device is packaged. 6 201001671 番 3 ΐ and Z to provide users with semiconductor EMI circuit to reduce EMI noise and ί short will be _ reduce Number of components of the hip-preserving circuit device as part of its The development time of the product is 0. In addition, the reference symbols in the above brackets are for easy understanding of the example of the addition, and the details are not limited to the illustrated ones. m. [Embodiment] ίί施' said the best in the implementation of the present invention. In the overall structure 40 of the semiconductor device of the figure, there is a 'circuit 1 〇 ^ ^ ^ 1 〇〇 heart, the body wafer (―) i and the lang lang = 31 and _^ === 2 The source potential for the internal circuit 10 is to have a semiconductor #¥1〇4ίϊϊ^〇Τ ° to the ground potential of the internal impurity σ卩 circuit electric wire 11, and should be supplied to the power supply wiring 11 and the inner Qiu Leizheng ^' 4. The internal circuit 10 operates by supplying electric power to a predetermined internal circuit 12 of the internal circuit row, and the terminal pad pdg is used to perform a semiconductor power supply to the power supply terminal device 100 to perform semiconductor operation. The device 1 〇〇塾 Pdg supplies electric potential, that is, the potential on the zeta potential side. On the other hand, the ground terminal pad ^201001671 is supplied with o[v] of the ground potential, that is, the potential on the low potential side. A plurality of power supply terminal pads Pdv and a ground terminal pad Pdg may be provided in the semiconductor device 100. In order to uniformly supply electric power to the semiconductor device 100 without unevenness due to the position in the semiconductor device 1 , it is preferable to arrange the power supply terminal pads Pdv and ground at equal intervals along the periphery of the semiconductor device 100 as much as possible. Terminal pad Pdg. Therefore, in order to perform uniform power supply, a plurality of power supply terminals 塾Pvd and a ground terminal pad Pdg may be provided. The power terminal pad Pdv and the ground terminal pad Pdg may be disposed at any position as long as they are outside the internal circuit 1A. However, in order to facilitate connection with an external power source, it is preferably provided in the vicinity of the peripheral edge of the semiconductor device 100. Thereby, the connection wiring of the external power source and the semiconductor device 100 can be shortened, and the semiconductor device 100 can be widely used. The peripheral power supply wiring 20 is for supplying power to the power supply terminal pad Pdv and the ground terminal pad Pdg which are provided in a distributed manner to the entire power supply wiring of the semiconductor device 1 . Therefore, the peripheral power supply wiring is connected to the power supply terminal Pdv and the ground terminal pad Pdg. The peripheral power supply wiring 2 includes a power supply potential peripheral power supply wiring 21 for supplying a power supply potential, and a ground potential peripheral power supply wiring 22 for supplying a ground potential. The power supply potential is connected to the power supply terminal pad Pdv by the peripheral power supply wiring 21, and the ground potential peripheral wiring 22 is connected to the ground terminal pad pdg. The peripheral power supply line 20 is a wiring for supplying electric power to the internal circuit ,, and is disposed outside the (four) part circuit 1 (), and is preferably disposed along the periphery of the half Ϊ ΪΪ (10) as shown in Fig. 1 . The power supply wiring 2G has the following effect: the power supply wiring in the case where the power supply terminal pad PdV and the ground terminal pad m are disposed to be dispersed from the surface of the semiconductor package # are easily used. . Therefore, it is desirable to arrange the 电 电 秘 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Power terminal _ "and the grounding terminal 塾 p pdg as far as possible outside the circumference i position is placed close to the power supply 轩 pad _ shape ground terminal 塾.201001671 and St Jii: 蚩 2: for the power supply line in the semiconductor device 100 The wiring with a large degree of loss to the degree of power supply has a small loss of power supply. It is preferable to use a separate power supply line 20, which is also used as the power supply 100: , T20 10 Electricity: The internal circuit of the circuit 10 is supplied with the power supply potential. The ground potential is used. The internal circuit of the iri circuit 10 is supplied with the ground potential. =:=Wiring 32 and _~== Internal power supply potential supply The wiring 31 is connected to the internal circuit 10, and the internal circuit ground potential supply wiring 3 Ϊ 3 S circuit 10 is connected to the internal circuit ground wiring 12. Thus, ^^ power wiring ^ is equipped with = electric ===== and internal circuit ground The potential supplier acts, and the conductor device 100 is internally closed. The Rc according to the wave is supplied with the m electric power = potential for the supply wiring 31 and the internal circuit ground potential to supply the internal circuit ^ Rc m to the required resistance component. As shown in Fig. 1, the t supply wiring 31 has the resistance Rv. Parasitic resistance. In addition, ^ and #供_碟32 have a hybrid resistor L and a resistor Rg, and no individual resistors are provided, but the internal circuit is electrically
201001671 位供給用配線31以及内部電路接地電位供給用配線％分別自身 具有的配線電阻。因此，内部電路供給用配線30可以不設置個別 的電阻體地具備RC濾波器的R成分。 當使用通常的配線圖形來形成内部電路電源電位供給用配線 31以及内部電路接地電位供給用配線32，並得到了適當的電阻 Rv、Rg時，可以直接對其進行應用，但當電阻Rv、Rg的值較小、 不足以構成適當的RC濾波器時，可以如下之構成。 為使電阻Rv、Rg成為適當的電阻值，能夠以比週邊電源配線 20小的線寬的配線來構成内部電路電源電位供給用配線31以及 内部電路接地電位供給用配線32。由此，可以使内部電路電源電 位供給用配線31以及内部電路接地電位供給用配線32的電阻値 增加，可以得到構成RC濾波器所需要的電阻成分。另外，内部電 路電源電位供給用配線31以及内部電路接地電位供給配線32，為 使y阻Rv、Rg的電阻值增加，以及為了以足夠長度來設置尺^^濾 波态，可以在週邊電源配線2〇和内部電路1〇之間形成往復的配* 線結構。在這種情況下，内部電路供給用電源配線3〇至少構 比週邊電絲線20長’理想的是構成為麵電源崎2〇的15 =上’更理想的是構成為2倍以上。根據半導體裝置1〇〇的内 部電路10和週邊電源配線2〇間的空間大小等決定内部電路供仏 己線3〇長度的上限，但例如構成為週邊電源配線20長Ϊ 拉通過將内部電源電位供給用配線31以及内部電路 生ϋ遭原配線22長且細，可以使配線自身具有的寄 增加，可以設置良好寄生的此濾波器。 邱電路電源電位供給用配線31具有的電阻Rv、和内 ί 32 1Rg ^ ^ 用配線32形^'為=^用2線31以及内部電路接地電位供給 大體相同。為相同的線圖形，因此其配線電阻Rv、Rg也 201001671 =内部電路電源電位供給用配線31和内部電路接地電位供給 =配線32接近地配置，以便在兩配線間產生配線間電容&由此， 部電路魏電健給聽線31和内部電路接地電位供給用 以r產生寄生的RC遽波器，可以實現EMI雜訊的降低。 ΐ令通過調整内部電路電源電位供給用配線31和内部 ^接地電位供給聽線32的距離，可以調整其電減。例如， 電電源電位供給用配線31和内部電路接地電位供給 =配線32的間隔距離’則可以增大配線間電容c的電容值，反之， 右增大間隔距離，則配線間電容C的電容值減小。 4^ ^生配線間電容C的内部電路電源電位供給用配線31 /· L電路接地電位供給用配線32彼此相鄰地配置，但例如也可 乂在i體上構成為在半導體晶圓4〇上交替地配置内部電路 ，供，配線31和内部電路接地電位供給用配線32的配線圖、 二替地配置内部電路電源電位供給則己線31和 円4電路接地電位供給用配線32的平面形狀來構成。 形成的寄生的Rc濾波器作為使低頻成分通過、使高頻成 二二，的低通渡波器來工作，可以降低在半導體裝置100中產生 吝=員成分的EMI雜訊。在® 1中，内部電路1G是EMI雜 ’因此’在從内部電路10產生的EMI雜訊通過内部電路供 a用電源配線30的期間，得到充分的衰減。 、 ，著’說明用於使職RC濾波器充分發揮功能的内部電路 ^電位供給紐線31以制部電路接地電健給用配線32的結 土士上所述，内部電路電源電位供給用配線31以及内部電路接 及=供給用配線32 ’將内部電路10的内部電路電源配線11以 線電路接地配、線12、和週邊電源配線20的電源電位用週邊配 連接^及接地電位料姐線22之間賴，但翻部電路1?的 ί接‘相及與週邊配線20的連接轉僅是！個部位。具 雷牧3部電路電源電位供給用配線31與内部電路10僅通過内部 電源配線11和雜點γν來進行連接，與猶m線僅 11 201001671 ^過毛源包位用週邊電源配線21和連接點Χν來進行連接。同樣 中收Ξί電路接地電位供給用配線32與内部電路10僅通過内部 ί、畜線12和連接點¥§來進行連接，與週邊電源配線20 4 接地電位供給用週邊電源配線22和連接點乂§來進行連接。 Η ’通過使週邊電源配線20和内部電路供給用電源配線30 二連接點xv、Xg在電絲和接地線上各僅為-個部位，並使 ，f電路供給用電源配線30和内部電路10的連接點Yv、Yg也 線和接地線上各僅為一個部位，可以使得料部電源配線201001671 The wiring resistance of the bit supply wiring 31 and the internal circuit ground potential supply wiring % respectively. Therefore, the internal circuit supply wiring 30 can include the R component of the RC filter without providing an individual resistor. When the internal circuit power supply potential supply line 31 and the internal circuit ground potential supply line 32 are formed using a normal wiring pattern, and appropriate resistors Rv and Rg are obtained, they can be directly applied thereto, but when the resistors Rv and Rg are used, When the value is small and is insufficient to constitute an appropriate RC filter, it can be configured as follows. In order to make the resistors Rv and Rg have appropriate resistance values, the internal circuit power supply potential supply line 31 and the internal circuit ground potential supply line 32 can be configured by wiring having a line width smaller than that of the peripheral power supply line 20. Thereby, the resistance 値 of the internal circuit power supply potential supply line 31 and the internal circuit ground potential supply line 32 can be increased, and the resistance component required to constitute the RC filter can be obtained. In addition, the internal circuit power supply potential supply line 31 and the internal circuit ground potential supply line 32 increase the resistance value of the y-resistances Rv and Rg, and the peripheral power supply wiring 2 can be provided in order to set the filter state with a sufficient length. A reciprocating alignment structure is formed between the crucible and the internal circuit 1〇. In this case, the internal circuit supply power supply wiring 3 is at least longer than the peripheral electric wire 20. It is preferable that 15 = upper side of the surface power supply is preferably 2 or more. The upper limit of the length of the internal circuit supply line 3〇 is determined according to the size of the space between the internal circuit 10 of the semiconductor device 1 and the peripheral power supply wiring 2, etc., but for example, the peripheral power supply wiring 20 is configured to be pulled long to pass the internal power supply potential. The supply wiring 31 and the internal circuit are long and thin by the original wiring 22, so that the wiring itself can be increased, and the filter can be provided with good parasitics. The resistance Rv and the internal voltage of the connection circuit 31 of the Qiu circuit power supply potential supply 31 are substantially the same as those of the second circuit 31 and the internal circuit ground potential of the wiring 32. In the same line pattern, the wiring resistances Rv and Rg are also 201001671 = the internal circuit power supply potential supply line 31 and the internal circuit ground potential supply line = the wiring 32 are arranged close to each other so as to generate an inter-wiring capacitance between the two wirings. The part circuit Wei Weijian supplies the RC chopper for generating parasitic nucleus to the listening line 31 and the internal circuit ground potential, which can reduce the EMI noise. The electric power reduction can be adjusted by adjusting the distance between the internal circuit power supply potential supply line 31 and the internal ground potential supply line 32. For example, the electric power supply potential supply line 31 and the internal circuit ground potential supply = the distance between the wirings 32 can increase the capacitance value of the inter-wiring capacitance c. Conversely, if the distance is increased rightward, the capacitance value of the inter-wiring capacitance C can be increased. Reduced. The inner circuit power supply potential supply wiring 31 of the raw wiring capacitor C / / L circuit ground potential supply wiring 32 is arranged adjacent to each other, but for example, it may be configured as a semiconductor wafer 4 on the i body. The internal circuit is alternately arranged, and the wiring pattern of the wiring 31 and the internal circuit ground potential supply wiring 32, and the planar shape of the internal circuit power supply potential supply line 32 and the 电路4 circuit ground potential supply wiring 32 are alternately arranged. Come to form. The formed parasitic Rc filter operates as a low-pass ferrite that passes low-frequency components and high-frequency components, and can reduce EMI noise generated in the semiconductor device 100. In the ® 1, the internal circuit 1G is EMI erroneous. Therefore, during the period in which the EMI noise generated from the internal circuit 10 is supplied to the power supply wiring 30 through the internal circuit, sufficient attenuation is obtained. The internal circuit for the function of the RC filter is fully described. The potential supply line 31 is connected to the internal circuit power supply potential wiring. 31, internal circuit connection and supply wiring 32'. The internal circuit power supply wiring 11 of the internal circuit 10 is grounded by the line circuit, the line 12, and the power supply potential of the peripheral power supply wiring 20 are connected by the periphery and the ground potential material line. Between 22, but the connection of the flip circuit 1? and the connection with the peripheral wiring 20 is only! Parts. The three circuits of the power supply potential supply line 31 and the internal circuit 10 are connected only by the internal power supply wiring 11 and the noise point γν, and are connected to the peripheral power supply line 21 and the peripheral power supply line 21 of the source line only 11 201001671. Click Χν to connect. Similarly, the circuit ground potential supply wiring 32 and the internal circuit 10 are connected only by the internal ί, the livestock line 12, and the connection point §, and the peripheral power supply wiring 20 4 the ground potential supply peripheral power supply wiring 22 and the connection point 乂§ to connect. Η 'By the peripheral power supply wiring 20 and the internal circuit supply power supply wiring 30, the two connection points xv and Xg are only a part on the electric wire and the ground line, and the f-circuit supply power supply wiring 30 and the internal circuit 10 are provided. The connection point Yv, Yg is also only one part on the ground line and the ground line, which can make the power supply wiring of the material part
=部電路1G之間流過的電流流過内部電路供給用電源配線 的全部導線。 帝例如在圖1中，被供給電源端子墊Pdv的電源電位vcc導致 的電流，從電源電位用週邊電源配線21的連接點Xv被供給，流 =部電路電源餘供給絲線31。柳f路電源電位供給用配 ί、、Λΐί從賴點Uv起左右妓_線雜，流般些配線的 則十角線相對側的連接點Wv流入内侧的連接點Zv。内部電 f電源電=供給用配線31也具有從連接點Zv左右分支的配線路 =過這些配線路徑的電流也流入對角線相對侧的連接點W。 並且，電流從連接點Yv經由内部電路電源配線u流過内部電路 jo内的處理電路，實現預定的電路功能。同樣地，在接地線中， 從内。卩電路10的内部電路接地配線12流出的電流，也從内部電 ，接地電位供給用配線32的連接點Yg通過左右的内側的配線路 仅々IL入對角線相對側的連接點Zg。並且，電流從連接點夺向 連接點Wg流動’經由左右的外侧的配線路徑，電流流向對角線 相對側的連接點Ug，通過連接點Xg，電流從接地端子墊Pdg流 出。 這樣’通過使内部電路電源電位供給用配線31以及内部電] 接地電位供給用配線32與週邊電源配線2〇的連接點Xv、1 與内部電路10的連接點Yv、Yg分別僅為一個部位，可以將由 部電路電源電位供給用配線31以及内部電路接地電位供給用配〗 32構成的rc濾波器設置成，向内部電路1〇供給的電流必定通』 12 201001671 产部配線路徑。由此，可以最大限度地發揮由内部電 配線31 “及内部電路接地電位供給用配線&構成的、rc 濾波器的功能，能夠可靠地期待EMI雜訊的降低。 & =:在圖1的實施例1的半導體裝置100 t，以並聯連接 ϋ 2段的形態’在週邊電源配線20 *内部電路10之間 €源電位供給用配線31以及内部電路接地電“ ，，、σ用配線32。通過設置並聯電路的部分，可以減小電阻&、 的值，減小電力供給的損耗。 g 另外，在實施例1的半導體裝置1〇0中，内部電路電源電位 供給用配線31以及内部電路接地電位供給用電位32與週邊電源 配線20的連接點Xv、Xg，選擇了相互接近地配置了電源端子^ Pdv和接地端子墊Pdg的左下角的位置。内部電路電源電位供給 用配線31以及内部電路接地電位供給用配線32與週邊電源配線 2〇的連接點χν、Xg可以選擇任意位置，但從減小電力損耗的觀 點出發，最好是與電源端子墊Pdv以及接地端子墊pdg接近的位 置。在此，電源端子墊Pdv以及接地端子墊pdg在圖丨中表示了 4個部位，但最好選擇與電源端子墊Pdv和接地端子墊Pdg最接 近的組合的端子墊接近的位置。例如，在圖1中，最好不在右下 角的電源端子墊Pdvf以及接地端子墊Pdgf的附近配置連接點 Xv、xg，而選擇除此以外的電源端子pdv以及接地端子pdg的組。 電源端子墊Pdv和接地端子墊Pdg接近則電力供給穩定，因此， 當在半導體裝置100中電源端子墊Pdv以及接地端子墊Pdg的組 合有多個時’可以選擇相互最接近的組合的電源端子墊Pdv以及 接地端子塾Pdg的附近。 接著，使用圖2說明用於實現實施例1的半導體裝置1〇〇的 ，路結構的半導體裝置1〇〇的平面結構以及截面結構的一例。圖2 是表示實施例1的半導體裝置10〇的平面結構以及截面結構的一 例的圖。圖2 (a)是表示實施例1的半導體裝置1〇〇的平面結構 的一例的圖。圖2 (b)是表示實施例1的半導體裝置100的截面 結構的一例的圖，表示圖2 (a)中的a-A，截面。 13 ,201001671 在圖2 (b)巾’在最下層配置局部氧化雜〇c 〇，就 J^r^°i0C0S 50 mn^4 ! 61 ==電：第介r==vcc的第1多晶-忿 ϊ? :;=ΐ半=装置100的立趙結構中形 \ 二緣的絕緣膜。層間膜 體灰置00中’供、，、&電源電位的内部電 ίϊ=亦卩爾輪糊_32也各自並骑兩條交 氣導ί:ΐ ::)在:㊁二：J上下層的導電層間的電 14 201001671 Z J，’内部電路接地電位供給用配線32與供給了接地The current flowing between the portion circuits 1G flows through all the wires of the internal circuit supply power supply wiring. For example, in Fig. 1, the current caused by the power supply potential vcc supplied to the power supply terminal pad Pdv is supplied from the connection point Xv of the power supply potential peripheral power supply line 21, and the flow = part circuit power supply is supplied to the wire 31.柳, Λΐ 从 从 从 从 U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U Internal power f Power supply=The supply wiring 31 also has a distribution line branched from the connection point Zv. The current passing through these wiring paths also flows into the connection point W on the opposite side of the diagonal line. Further, a current flows from the connection point Yv to the processing circuit in the internal circuit jo via the internal circuit power supply wiring u, thereby realizing a predetermined circuit function. Similarly, in the ground line, from inside. The current flowing out from the internal circuit ground wiring 12 of the cymbal circuit 10 is also connected to the connection point Zg on the opposite side of the diagonal line from the connection point Yg of the internal potential and the ground potential supply wiring 32 through the right and left inner distribution lines. Then, the current flows from the connection point to the connection point Wg. The current flows to the connection point Ug on the opposite side of the diagonal line via the left and right wiring paths, and the current flows from the ground terminal pad Pdg through the connection point Xg. In this way, the connection points Xv and 1 of the internal circuit power supply potential line 31 and the internal power supply line 32 are connected to the peripheral power supply line 2, and the connection points Yv and Yg of the internal circuit 10 are only one portion. The rc filter composed of the partial circuit power supply potential supply line 31 and the internal circuit ground potential supply configuration 32 can be set such that the current supplied to the internal circuit 1A must pass through the 12 201001671 production part wiring path. Thereby, the function of the rc filter composed of the internal electric wiring 31 and the internal circuit ground potential supply wiring & can be maximized, and the reduction of EMI noise can be reliably expected. & =: Fig. 1 The semiconductor device 100 t of the first embodiment is connected in parallel with the second stage ′′ 'between the peripheral power supply wiring 20 *the internal circuit 10 and the source electric potential supply wiring 31 and the internal circuit grounding electric power ”, the σ wiring 32 . By setting a portion of the parallel circuit, the value of the resistor &, can be reduced, and the power supply loss can be reduced. In the semiconductor device 1A0 of the first embodiment, the connection points Xv and Xg of the internal circuit power supply potential supply line 31 and the internal circuit ground potential supply potential 32 and the peripheral power supply line 20 are selected to be close to each other. The position of the lower left corner of the power terminal ^ Pdv and the ground terminal pad Pdg. The connection points χν and Xg of the internal circuit power supply potential supply line 31 and the internal circuit ground potential supply line 32 and the peripheral power supply line 2A can be selected at any position. However, from the viewpoint of reducing power loss, it is preferable to connect the power supply terminal. The position where the pad Pdv and the ground terminal pad pdg are close to each other. Here, the power terminal pad Pdv and the ground terminal pad pdg are shown in four places in the drawing, but it is preferable to select a position where the terminal pad of the combination closest to the power terminal pad Pdv and the ground terminal pad Pdg is close. For example, in Fig. 1, it is preferable that the connection points Xv and xg are not disposed in the vicinity of the power terminal pad Pdvf and the ground terminal pad Pdgf in the lower right corner, and a group other than the power supply terminal pdv and the ground terminal pdg is selected. When the power supply terminal pad Pdv and the ground terminal pad Pdg are close to each other, the power supply is stabilized. Therefore, when there are a plurality of combinations of the power supply terminal pad Pdv and the ground terminal pad Pdg in the semiconductor device 100, the combination of the power supply terminal pads which are closest to each other can be selected. Pdv and the vicinity of the ground terminal 塾Pdg. Next, an example of a planar structure and a cross-sectional structure of a semiconductor device 1A for implementing the semiconductor device 1 of the first embodiment will be described with reference to FIG. Fig. 2 is a view showing an example of a planar structure and a cross-sectional structure of a semiconductor device 10A of the first embodiment. Fig. 2 (a) is a view showing an example of a planar configuration of a semiconductor device 1 of the first embodiment. Fig. 2 (b) is a view showing an example of a cross-sectional structure of the semiconductor device 100 of the first embodiment, and shows a-A in Fig. 2 (a) and a cross section. 13 , 201001671 In Figure 2 (b) towel 'in the lowermost layer is configured with local oxidized chopper c 〇, then J^r^°i0C0S 50 mn^4 ! 61 == electricity: the first polymorph of r == vcc -忿ϊ? :;=ΐ 半=Insulation film of the shape of the vertical structure of the device 100. Interlayer film ash set 00 in the 'supply,,, & power supply potential internal electric ϊ 卩 卩 卩 轮 轮 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Electricity between the lower conductive layers 14 201001671 ZJ, 'Internal circuit ground potential supply wiring 32 and ground supply
的苐2夕晶梦62實現了導通。 GNDThe 苐2 Xijing Dream 62 achieved conduction. GND
gp二己21〇，在配線層3〇彼此間也平面地產生配線間電容C 芦間，）對應的俯視圖，通過俯細可知，在 ΪΙ 〃每兩條㈣地配置向同—方向延伸的 =電^位供給用配線31以及内部電路接地電位供給用配^電 。虽者眼於與圖2⑻對應的斷開線A_A，的部辦，在中袁 j兩端部進行了供給電源電位vcc的第〗多祕&和二 路％源電位供給用配線3i _通。並且，在中 二 部分進行了供給接地電位GND的第2多晶石夕62和[^電 給用配線32的導通。在圖2 (a)中，為了易於理解，= 央°卩和兩知部的接觸孔80存在的區域的層間膜70、露出^ 1多气石夕61陳態進行了表#。另外’在内部電路接地電位供认 ，配線32的下層’經由層間膜7〇存在供給接地電位gnd的第^ Ϊ ί矽62，因此可知經由接觸孔8〇供給接地電位的情況與圖次b ) 於是，從圖2 (a)可知，内部電路電源電位供給用配線31和 内部電路接地電位供給用配線32相向的區域，形成了延 間電容。如此，在本實施例的半導體裝置1〇〇中，可以通過平面 以及立體結構來產生配線間電容c。並且如圖丨所示，通過使内 部電路供給用電源30與週邊電源配線20以及與内部電路1〇的連 接點XV、Xg、Yv、Yg分別為一個部位，可以使向内部電路1〇 供給的電流全部通過由配線間電容C和電阻Rv、Rg形成的RC 濾波器’可以使EMI雜訊有效地降低。 【實施例2】 圖3是應用了本發明的實施例2的半導體裝置1〇〇&的整體結 15 201001671 ·» 構圖的一例。實施例2的半導體裝置l〇〇a中，電源端子墊Pdv、 ，，子塾Pdg、週邊電源配線2G以及内部電路1G的配置結構與 、方例1的半導體裝置1〇〇相同，因此賦予相同的參照符號，省 略其說明。 、 實施例2的半導體裝置職巾，在轉體晶圓他上形成的 ^ °卩電路供給用電源配線30a沒有並聯電路部分，全部由RC分佈 ^數電路構成，並且平面結構成為螺旋狀，這一點與實施的 半導體裝置1〇〇不同。 、在實施例2中，内部電路供給用電源配線施中，内部電路 / 電位供給用配線3 la在連接點χν與電源電位用週邊電源配線 21相連’在連接點Υν與内部電路電源配線u相連。同樣地，内 部電路接地電位供給用配線32a在連接點Xg與接地電位用週邊電 源配線22相連’在連接點Yg與内部電路接地配線12相連。從連 接點Xv到連接點γν以及從連接點Xg到連接點Yg，内部電路電 源電位供給用配線31a以及内部電路接地電位供給用配線32a互 相平行地，螺旋狀地維持1條而被配置構成。並且，内部電路電 源電位供給用配線3la作為配線電阻而具有電阻Rva，内部電路接 地電位供給用配線32a作為配線電阻而具有電阻Rga。另外，將内 部電路電源電位供給用配線31a和内部電路接地電位供給用配線 C / 32a配置地足夠接近’產生配線間電容Ca，形成了寄生的尺(：濾 波器。 〜 通過成為這樣的結構，從電源端子墊Pdv以及接地端子势 向内部電路10供給的電流全部通過由螺旋狀的内部電路電源電位 供給用配線31a以及内部電路接地電位供給用配線32a形成的Rc 慮波裔’此夠可罪地降低EMI雜訊。另外，内部電路電源電位供 給用配線31a以及内部電路接地電位供給用配線似成為了螺旋 狀地包圍内部電路10的周圍的平面形狀，因此，與實施例丨同樣 地，在將内部電路10配置在中央時，在内部電路1〇和週邊電源 配線20間的空間中，能夠以沿著空間形狀的形態有效地配置Rc 慮波為’因此能夠設置最大限度地利用了空閒空間的Rc據波器， 16 201001671 可以提高RC濾波器的能力。 這樣’根據實施例2的半導體裝置100a，通過串聯地螺旋狀 地配置内部電路電源電位供給用配線31 a以及内部電路接地電位 供給用配線32a，可以提高RC濾波器的雜訊降低能力本身，並且 可以使所設置的RC濾波器可靠地發揮EMI雜訊降低功能。 【實施例3】 圖4是應用了本發明的實施例3的半導體裝置10%的整體結 構圖的一例。在圖4中，實施例3的半導體裝置l〇〇b中，關於電 源端子墊Pdv、接地端子墊Pdg以及週邊電源配線2〇的配置以及 結構，與實施例1以及實施例2的半導體裝置1〇〇、i00a相同， 因此賦予相同的參照符號，省略其說明。 實施例3的半導體裝置100b中’内部電路1〇b不在半導體晶 圓40b =中央部，而成為了靠近與週邊電源配線2〇鄰接的一側的 配置，這一點與實施例丨以及實施例2的半導體裝置1〇〇、1〇此 =同。如此，當内部電路1〇b的配置位置不是半導體晶圓4〇b的 央位置，也可以恰當地應用本實施例的半導體裝置1〇〇匕。 f圖4中，靠右地接近週邊電源配線2〇來配置内部電路丨㈨， 在半V體晶圓40b的左侧產生了空間。因此，在實施例3中，使 3用的左侧的空間，形成内部電路供給用電源配線 /•相丨夕叫從週邊電源配線2〇内的左侧到内部電路10b的 Ϊ ί日，是可以形成内部電路供給用電源配線施的區 =的?中可以使内部電路供給用電源配線娜 户:/! 可以最有效地形成11<：濾波器的結構。 30b 盖左到右蛇形地配置内部電路供給用電源配線 =的、，、°構。内邛電路電源電位供給用配線31b作為配線雷阻而呈 且有ίιί:内路接地電位供給用配線32b作為配線電阻而、 仕運接點Xv廷-個部位連接，與内部電路10b 17 .201001671 位供yv這—個部位電氣連接。囉地，㈣電路接地電 聿與週邊電源配線2〇僅在連接‘點々這一個部位 連接s 電路勘也僅在連接點Yg這一個部位連接。In the top view of the wiring layer 3〇, the inter-wiring capacitance C is generated in the plane between the wiring layers 3, and the corresponding plan view shows that the two sides (four) are arranged in the same direction. The bit supply wiring 31 and the internal circuit ground potential supply are supplied. In the case of the disconnection line A_A corresponding to FIG. 2 (8), the second power supply potential vcc is supplied to the both ends of the intermediate element j, and the two-way source electric potential supply wiring 3i_pass is provided. . Further, in the second half, the second polycrystalline stone 62 supplied to the ground potential GND and the conduction of the electric power supply wiring 32 are performed. In Fig. 2(a), for the sake of easy understanding, the interlayer film 70 of the region where the contact hole 80 of the two-part portion and the contact hole 80 of the two portions are present is exposed. Further, 'the internal circuit ground potential is supplied, and the lower layer of the wiring 32' is supplied to the ground potential gnd via the interlayer film 7, so that the ground potential is supplied via the contact hole 8〇 and the figure b) As can be seen from Fig. 2 (a), the inter-capacitance is formed in a region where the internal circuit power supply potential supply line 31 and the internal circuit ground potential supply line 32 face each other. As described above, in the semiconductor device 1 of the present embodiment, the inter-wiring capacitance c can be generated by the plane and the three-dimensional structure. As shown in FIG. ,, the internal circuit supply power supply 30 and the peripheral power supply wiring 20 and the connection points XV, Xg, Yv, and Yg of the internal circuit 1 are respectively provided as one portion, so that the internal circuit 1 can be supplied. The IGBT filter 'which is formed by the inter-wiring capacitance C and the resistors Rv and Rg' can effectively reduce the EMI noise. [Embodiment 2] Fig. 3 is an example of a composition of a whole junction 15 201001671 ·» of a semiconductor device 1 〇〇 & of a second embodiment to which the present invention is applied. In the semiconductor device 10a of the second embodiment, the arrangement configuration of the power supply terminal pads Pdv, , the sub-Pdg, the peripheral power supply wiring 2G, and the internal circuit 1G is the same as that of the semiconductor device 1 of the first example, and thus the same is given. The reference numerals are omitted, and the description thereof is omitted. In the semiconductor device of the second embodiment, the power supply wiring 30a formed on the rotor wafer has no parallel circuit portion, and is entirely composed of an RC distribution circuit, and the planar structure is spiral. One point is different from the implemented semiconductor device. In the second embodiment, the internal circuit supply power supply wiring is applied, and the internal circuit/potential supply wiring 3la is connected to the power supply potential peripheral power supply wiring 21 at the connection point χν. The connection point Υν is connected to the internal circuit power supply wiring u. . Similarly, the internal circuit ground potential supply wiring 32a is connected to the ground potential peripheral power supply line 22 at the connection point Xg, and is connected to the internal circuit ground wiring 12 at the connection point Yg. The internal circuit power supply line 31a and the internal circuit ground potential supply line 32a are arranged in parallel in a spiral shape from the connection point Xv to the connection point γν and from the connection point Xg to the connection point Yg. In addition, the internal circuit power supply line 3la has a resistance Rva as a wiring resistance, and the internal circuit ground potential supply line 32a has a resistance Rga as a wiring resistance. In addition, the internal circuit power supply potential supply line 31a and the internal circuit ground potential supply line C/32a are disposed close enough to generate the inter-wiring capacitance Ca, and a parasitic scale is formed (filter: ~ By such a configuration, All of the current supplied from the power supply terminal pad Pdv and the ground terminal potential to the internal circuit 10 is formed by the spiral internal circuit power supply potential supply line 31a and the internal circuit ground potential supply line 32a. In addition, the internal circuit power supply potential supply line 31a and the internal circuit ground potential supply line seem to have a planar shape that spirally surrounds the periphery of the internal circuit 10. Therefore, similarly to the embodiment, When the internal circuit 10 is placed at the center, the Rc wave can be effectively arranged in the space between the internal circuit 1A and the peripheral power supply line 20 in a spatial shape. Therefore, it is possible to provide maximum use of the free space. The Rc wave device, 16 201001671 can improve the capability of the RC filter. Thus [according to embodiment 2 In the semiconductor device 100a, the internal circuit power supply potential supply line 31a and the internal circuit ground potential supply line 32a are arranged in a spiral shape in series, whereby the noise reduction capability of the RC filter itself can be improved, and the set RC filter can be made. [Embodiment 3] Fig. 4 is an example of an overall configuration diagram of a semiconductor device according to a third embodiment to which the present invention is applied. In Fig. 4, the semiconductor device 1 of the third embodiment In the case of the power supply terminal pad Pdv, the ground terminal pad Pdg, and the peripheral power supply wiring 2, the arrangement and the configuration are the same as those of the semiconductor devices 1A and i00a of the first embodiment and the second embodiment, and therefore the same reference numerals are given. In the semiconductor device 100b of the third embodiment, the internal circuit 1b is not in the central portion of the semiconductor wafer 40b, and is disposed close to the side adjacent to the peripheral power supply line 2A.丨 and the semiconductor device 1 of the second embodiment, 1 〇 this same. Thus, when the arrangement position of the internal circuit 1 〇 b is not the central position of the semiconductor wafer 4 〇 b The semiconductor device 1 of the present embodiment can also be suitably applied. In Fig. 4, the internal circuit 丨 (9) is disposed to the right of the peripheral power supply wiring 2, and the left side of the half V-body wafer 40b is formed. Therefore, in the third embodiment, the space on the left side for the third side is formed, and the power supply wiring for the internal circuit supply is formed, and the left side of the peripheral power supply wiring 2 is turned to the internal circuit 10b. In the area where the internal circuit supply power supply wiring can be formed, the internal circuit supply power supply wiring can be used. /! The structure of the 11<: filter can be formed most effectively. 30b Cover left to right serpentine The internal circuit supply power supply wiring = , , and the configuration are arranged. The inner circuit power supply potential supply wiring 31b is provided as a wiring lightning resistance, and the internal circuit ground potential supply wiring 32b is used as the wiring resistance, and the customer contact Xv is connected to each other, and the internal circuit 10b 17 .201001671 The yv is a part of the electrical connection.啰 ,, (4) Circuit grounding 聿 and peripheral power wiring 2 〇 only in the connection ‘point 々 this part of the connection s circuit survey is also only connected at the connection point Yg.
門可樣的結構，相部電路1〇和週邊電源配線2〇之 二曰分佈常數電路具有蛇形地較長形狀的此濾波器。 二：，了四角形的空間時’通過構成為蛇形地配置内部電 給用配線31b以及内部電路接地電位供給用配線 =來延長RC渡波器，可以提高RC攄波器的能力，降低EMI "況另外，内部電路電源電位供給用配線31b以及内部電路接 地電位供給用配線32b與週邊電源配線2〇以及内部電路1〇的連 接,’4 Xv Xg、γν、Yg都僅是一個部位，因此，流過内部電路 的電流全部通過RC濾波器’能夠可靠地發揮據波器的功能。 此外，在實施例3中說明了靠近右側來配置内部電路1〇b的 例子，但也可以靠近左侧來配置内部電路l〇b，當然配置在遠側或 近側也同樣可以應用本實施例的半導體裝置l〇〇b。 【實施例4】 圖5是應用了本發明的實施例4的半導體裝置1〇〇c的整體妙 構圖的一例。在圖5中，實施例4的半導體裝置1〇〇(：中，電源^The gate-like structure, the phase circuit 1〇 and the peripheral power supply wiring 2〇 have a serpentinely long shape of this filter. (2) When the space of the square is formed, the RC waver can be extended by arranging the internal electric supply wiring 31b and the internal circuit ground potential supply wiring = in the form of a serpentine, thereby improving the capability of the RC chopper and reducing EMI " In addition, the internal circuit power supply potential supply line 31b and the internal circuit ground potential supply line 32b are connected to the peripheral power supply line 2A and the internal circuit 1A, and each of '4 Xv Xg, γν, and Yg is only one portion. All of the current flowing through the internal circuit can reliably function as a wave filter through the RC filter'. Further, in the third embodiment, an example in which the internal circuit 1b is disposed close to the right side has been described, but the internal circuit 10b may be disposed close to the left side. Of course, the present embodiment can also be applied to the far side or the near side. Semiconductor device l〇〇b. [Embodiment 4] Fig. 5 is an example of an overall configuration of a semiconductor device 1Ac to which Embodiment 4 of the present invention is applied. In FIG. 5, the semiconductor device 1 of the embodiment 4 (:, power supply ^
子墊Pdv、接地端子墊pdg以及週邊電源配線2〇的配置以及結構 與實施例3的半導體裝置i〇〇b相同，因此賦予相同的泉昭傅 省略其說明。 一現’ 在圖5中，實施例4的半導體裝置100c，在半導體晶圓4〇c 上形成的内部電路15、16為多個，具有第1内部電路15以及第2 内部電路16 ’這一點與實施例3的半導體裝置i〇〇b不同。内部電 路U、16，根據半導體裝置100c的用途，有時在一個半導體^置 100c内設置有多個。即使在這種情況下也可以應用本發明的 體裝置。 在圖5中，與週邊電源配線20鄰接地靠近一側來配置多個内 部電路15、16，但第1内部電路15和第2内部電路16彼此通過 内部電路電源配線11以及内部電路接地配線12相連。即，使^ 18 201001671 内部電路路接地_ 12來進行第1 在這種情況下，例如，若進行供给’供給了相同的電位。 此，成為向第1内部電路内部電路16的電源供給，因 4的轉體裳置l00c，可以將^ 構即可。於是’實施例 合併捕捉為-個_路2内部電路Μ λ a, j从⑽馮與實施例3 —樣。 實施例3大體^ )J。罝^而供給用電源配線30的結構與The arrangement and configuration of the sub-pad Pdv, the ground terminal pad pdg, and the peripheral power supply wiring 2 are the same as those of the semiconductor device i〇〇b of the third embodiment, and therefore the same description will be omitted. In the semiconductor device 100c of the fourth embodiment, a plurality of internal circuits 15 and 16 are formed on the semiconductor wafer 4〇c, and the first internal circuit 15 and the second internal circuit 16' are provided. It is different from the semiconductor device i〇〇b of the third embodiment. The internal circuits U and 16 may be provided in plurality in one semiconductor device 100c depending on the use of the semiconductor device 100c. Even in this case, the body device of the present invention can be applied. In FIG. 5, a plurality of internal circuits 15 and 16 are disposed adjacent to the peripheral power supply wiring 20, but the first internal circuit 15 and the second internal circuit 16 pass through the internal circuit power supply wiring 11 and the internal circuit ground wiring 12, respectively. Connected. In other words, the first circuit is grounded by _ 18 201001671 internal circuit _ 12 In this case, for example, the same potential is supplied when the supply is supplied. In this case, the power is supplied to the first internal circuit internal circuit 16, and the rotating body of the fourth internal circuit 16 can be configured. Thus, the embodiment merges and captures the internal circuit λ λ a, j from (10) von to the third embodiment. Example 3 is generally ^)J.罝^ and the structure of the power supply wiring 30 for supply and
具有作為配線2的電二f電路電源電位供給用配線31C 具有作為配線電阻的電阻:電路接地電位供給用配線3乂 和内部電路接I電位内3 源電位供給用配線31c ㈣雷^°用線32C足夠接近地被配置，產生配 g 接二 == ^第1内部電路15與第2内部電路16彼此連接，電力供 -方進行全部的供給。並且，將内部電路電源用 接電路接地電位供給用配線议作為整體，在連 =和Yv，連接點Xg和Yg彼此相連。由此，在四角連$點 用=長’™為_ rc遽波ii作 如此，即使内部電路15、16為多個，在向内部電路Μ Μ 可時’也可以作為與實施例1至3相同的結構來 另外’在實施例4中，說明了内部電路15、16為兩個愔 但即使在具備3個以上的若供給相同的電位則動作的内部電路 19 201001671 15、16時，也可以同樣地應用實施例4。 【實施例5】 圖6是應用了本發明的實施例5的半導體裝置麵 構圖的一例。實施例5的半導體裝置10似具有：第【 7α 第2内部電路Μ、第i電源端子塾Pdw、第i接i : 第2電源端子墊Pdv2、第2接地端子塾pdg2 g ，、第2刪_ 2Ge、第丨_路供_線 弟2内部電路供給用電源配線3〇e。 第1内部電路17與第2内部電路18是在功能上相互獨立的 =4電路，是需要不_位的電源供給的電路。於是 不同的多個内部電路17、18時’也可以應用本發明的 第1内部電路17和第2内部電路18’作為電源而供給的電位 此從外部連接用的外部電源供給不同的電位。因此，也 對應^各内部電路17、18 _立地設置外部連接㈣端子塾。 f 1電源端子塾Pdvl以及第i接地端子塾pdgl是用於接收 pH 電力的端子塾。另外，第2電源端子墊 給的i力的端=子龍82是驗純向第2崎電路18供 -蕾^^也第1週邊電源配線施是用於向第1内部電路17進 ίίΐΐ給進的電 第2週邊電源配線2〇6是用於向第2内 和第a2内部電路18獨立地供給不同電位的H向第1内部電路17 位供用電源配線30d具有第1内部電路電源電 内it第1内部電路接地電位供給用配線娜。第1 電健給用配線3id作為配線電阻而具有電阻 電阻二_32d作為配線電阻而具有 弟1内。卩電路電源電位供給用配線3 W和第1 201001671 衮電位供給用配線32<1接近地配置，以產生配線間電 备c^’形成寄生的波器。 =電路電源電位供給用配線31d與第1週邊電源配線 接點γ 1 點Χν1這一個部位連接，與第1内部電路17僅在連 用配線固部位連接。同樣地’第1内部電路接地電位供給 連接、i 21週邊電源配、線2〇d僅在連接點xgi這一個部位 ίΐ内^路m路17僅在連接點Ygl這—個部位連接。並且， 器。I過k士 ί導?ΐ8140d上左側的空間構成較長的RC濾波 RC#波第1内部電路17供給的電流必定全部經由 二 驗11的EMI雜降低魏充分發揮。 3〇e具有;第2内路_18也相同’第2内部電路供給用電源配線 地電位供給用配°線電電位供給用配線31e和第2内部電路接 為配線電二具有電内=電路電源電位供給用配線仙作 32e作g ”，弟2内部電路接地電位供給用配線 位^用酉有。並且，將第2内部電路電源電 地配置，以i生配電路接地電位供給用配線处接近 另外，篦2肉^电各 從而形成寄生的RC濾波器。 源配線20e僅在連接】=源:電，供給用配線31e與第2週邊電 僅在連接點j 廷一個部位連接’與第2内部電路18 位供給用配線32Γ盘第局同f也’第2内部電路接地電 個部位連接，與第jig^f^2〇e僅在連接點秘這— 有蛇形的平^結構，供給用配線31e作為整體也具 的RC遽波器。通過該圓40d上右側的空間構成較長 全部通過RC濾、波器，=2部電路18供給的電流必定 充分地發揮。 使RC濾波器的EMI雜訊降低的效果 此中共:路厂二8，㈣ $不冋蚪，根據實施例5的半導體裝置 21 201001671 100d，通過使電源供給系統獨立，還獨立地設置RC濾波器，可以 • 個別地降低在内部電路17、18中產生的EMI雜訊，結果是可以抑 制作為半導體裝置1〇〇d整體的EMI雜訊。 — ^另外’在圖6中舉了内部電路17、18為兩個的情況為例進行 工說明[但即使在具有更多内部電路17、18時，通過對應於電源 電位不同的數量來獨立地設置RC濾波器等，也可以同樣地降低 EMI雜訊。 此外’實施例1〜5的半導體裝置100、100a、l〇〇b、100c、 100d，通過進行封裝而收容在封裝内，可以作為半導體積體電路 产 裝置來產品化。應用了本實施例的半導體裝置1〇〇、1〇〇a〜l〇〇d 的半導體積體電路裝置，已經進行了 EM]^*訊應對，因此，不需 用戶進行EMI雜訊應對。因此’用戶在使用應用了本發明的半 導，積體電路裝置的情況下，可以削減EMI雜訊應對所需要的工 =里和部件數量，因此可以縮短將半導體積體電路裝置作為部件 來使用的產品的開發期間。 杏 >以上詳細說明了本發明的優選實施例，但本發明不限於上述 ^施例:在不脫離本發明的範圍的情況下，可以對上述實施例進 行各種變形以及替換。尤其，在實施例丨中說明的、當將内部電 • 路供給用電源配線30的線寬構成得比週邊電源配線2〇為小時， ί 選擇電源端子墊Pdv和接地端子墊Pdg最接近的組合的端子墊， f其附近配置内部電路供給用電源配線3〇和週邊電源配線2〇的 連接點Xv、Xg ’這種結構可以與實施例2〜5組合起來應用。另 外，在實施例1的圖2中說明的、當產生配線間電容c時，不僅 利用在平面的内部電路電源電位供給用配線31和内部電路接地電 ，供，用配線32之間產生的配線間電容，也可以利用在截面 中、在電源電位vcc供給用的第丨多晶矽61和接地電位GND供 給用的第2多晶矽62之間產生的配線間電容c，以上内容也可以 =樣應用於實細2〜5。本發明只要在平面結構等方面不產生 盾’便可以將實施例彼此組合。 22 201001671 【圖式簡單說明】 附圖說明 圖1是實施例1半導體裝置100整體結構圖的一例； 圖2是表示實施例1半導體裝置100平面結構以及截面結構的一 例之圖，圖2 (a)是表示實施例1半導體裝置1〇〇平面結構的一 例之圖、圖2 (b)是表示實施例1半導體裝置1〇〇截面結構的一 例之圖； 圖3是實施例2半導體裝置100a整體結構圖的一例，· 圖4是實施例3半導體裝置100b整體結構圖的一例； ^ 圖5是實施例4半導體裝置100c整體結構圖的一例；以及 f 圖6是實施例5半導體裝置100d整體結構圖的一例。 【主要元件符號說明】 10、10b、10c、15、16、17、18 内部電路 11 内部電路電源配線 12 内部電路接地配線 20、 20d、20e週邊電源配線 21、 21d、21e電源電位用週邊電源配線 22'22d > 22e接地電位用週邊電源配線 L 30、30a、30b、30c、30d、30e内部電路供給用電源配線The electric two-fuse power supply potential supply line 31C as the wiring 2 has a resistance as a wiring resistance: a circuit ground potential supply wiring 3A, and an internal circuit connected to the I potential 3 source potential supply wiring 31c (4) 32C is disposed sufficiently close to each other to generate a pair of g=2. The first internal circuit 15 and the second internal circuit 16 are connected to each other, and the power supply is supplied to all. Further, the internal circuit power supply circuit grounding potential supply wiring is considered as a whole, and the connection points Xg and Yg are connected to each other at the connection = and Yv. Therefore, in the four corners, the dot is used for the length = TM is _ rc 遽 ii. Even if there are a plurality of internal circuits 15 and 16, it is possible to use the same as in the first to third embodiments. In the fourth embodiment, the internal circuits 15 and 16 are two 愔, but even when three or more internal circuits 19 201001671 15 and 16 that operate when the same potential is supplied are provided, Example 4 was applied in the same manner. [Embodiment 5] Fig. 6 is a view showing an example of a surface view of a semiconductor device to which Embodiment 5 of the present invention is applied. The semiconductor device 10 of the fifth embodiment has the following: [7α second internal circuit Μ, i-th power supply terminal 塾Pdw, i-th connection i: second power supply terminal pad Pdv2, second ground terminal 塾pdg2g, and second deletion _ 2Ge, 丨 _ _ _ _ 2 2 internal circuit supply power supply wiring 3 〇 e. The first internal circuit 17 and the second internal circuit 18 are functionally independent =4 circuits, and are circuits that require no power supply. Then, the potentials supplied by the first internal circuit 17 and the second internal circuit 18' of the present invention as the power source can be applied to different internal circuits 17 and 18, respectively. This is supplied with different potentials from the external power supply for external connection. Therefore, the external connection (four) terminal 设置 is also provided correspondingly to the internal circuits 17, 18_. The f 1 power terminal 塾 Pdvl and the ith ground terminal 塾 pdgl are terminals for receiving pH power. In addition, the end of the i-force of the second power supply terminal pad is supplied to the second saki circuit 18, and the first peripheral power supply is applied to the first internal circuit 17. The second external power supply wiring 2〇6 for supplying the second inner and the a2 internal circuits 18 is supplied with a different potential to the first internal circuit. The 17th power supply wiring 30d has the first internal circuit power supply. It is the first internal circuit ground potential supply wiring Na. The first electric power supply wiring 3id has a resistance of 2d as a wiring resistance and has a wiring resistance as the wiring resistance. The circuit power supply potential supply wiring 3 W and the first 201001671 衮 potential supply wiring 32 < 1 are arranged close to each other to generate a parasitic wave device. The circuit power supply potential supply line 31d is connected to the first peripheral power supply line contact point γ 1 point Χν1, and is connected to the first internal circuit 17 only at the connection wiring portion. Similarly, the first internal circuit ground potential supply connection, the i 21 peripheral power supply, and the line 2〇d are connected only at one point of the connection point xgi. The internal path m17 is connected only at the connection point Ygl. And, the device. I have a long RC filter on the space on the left side of the 1408140d. The current supplied by the first internal circuit 17 of the RC# wave must be fully utilized by the EMI impurity reduction of the second test. 3〇e has the same meaning as the second internal circuit_18. The second internal circuit supply power supply wiring ground potential supply distribution line electric potential supply wiring 31e and the second internal circuit are connected to the wiring electric two. The power supply potential supply wiring is 32" as the "g", and the second internal circuit power supply wiring is used. The second internal circuit power supply is electrically disposed, and the grounding potential supply wiring is provided. In addition, the RC2 meat is electrically connected to form a parasitic RC filter. The source wiring 20e is connected only by the source=electricity, and the supply wiring 31e and the second peripheral power are connected only at one point of the connection point j. 2 Internal circuit 18-bit supply wiring 32 The first part of the circuit is connected to the second internal circuit grounding part, and the first part is connected to the jig^f^2〇e. This has a serpentine flat structure. The supply wiring 31e has an RC chopper as a whole. The space on the right side of the circle 40d is configured to pass through the RC filter and the filter, and the current supplied from the two-circuit circuit 18 must be sufficiently exhibited. The EMI noise reduction effect of this CCP: road factory two 8, (four) $ no In other words, according to the semiconductor device 21 201001671 100d of the fifth embodiment, by setting the RC filter independently of the power supply system, the EMI noise generated in the internal circuits 17, 18 can be individually reduced, and the result is EMI noise is suppressed as a whole of the semiconductor device 1 〇〇d. - ^ In addition, in FIG. 6, the case where the internal circuits 17 and 18 are two is described as an example [but even if there are more internal circuits 17, At 18 o'clock, the EMI filter or the like is independently provided in accordance with the number of power supply potentials differently, and the EMI noise can be similarly reduced. Further, the semiconductor devices 100, 100a, 10b, 100c of the first to fifth embodiments, The package 100d is housed in a package and can be used as a semiconductor integrated circuit device. The semiconductor integrated circuit device using the semiconductor device 1〇〇1〇〇1〇〇1〇〇d of the present embodiment is applied. EM]^* response has been carried out, so there is no need for users to deal with EMI noise. Therefore, the user can reduce EMI when using the semi-conductor and integrated circuit device to which the present invention is applied. In response to the required number of parts and the number of components, it is possible to shorten the development period of the product in which the semiconductor integrated circuit device is used as a component. Apricot> The preferred embodiment of the present invention has been described in detail above, but the present invention is not limited thereto. The above embodiment can be variously modified and replaced without departing from the scope of the invention. In particular, the line for supplying the internal power supply wiring 30 in the embodiment is described. The width is set to be smaller than the peripheral power supply wiring 2〇. ί The terminal pad of the combination in which the power supply terminal pad Pdv and the ground terminal pad Pdg are closest to each other is selected, and the internal circuit supply power supply wiring 3〇 and the peripheral power supply wiring 2 are disposed in the vicinity thereof. The structure of the connection points Xv, Xg' can be applied in combination with the embodiments 2 to 5. In addition, when the inter-wiring capacitance c is generated as shown in FIG. 2 of the first embodiment, not only the internal circuit power supply potential supply wiring 31 but also the internal circuit grounding power in the plane is used, and the wiring generated between the wirings 32 is used. The inter-wiring capacitance c generated between the second polysilicon 61 for supplying the power supply potential vcc and the second polysilicon 62 for supplying the ground potential GND in the cross section may be used as the same. Fine 2~5. The present invention can be combined with each other as long as the shield is not produced in terms of a planar structure or the like. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a view showing an example of a general configuration of a semiconductor device 100 according to a first embodiment; FIG. 2 is a view showing an example of a planar structure and a cross-sectional structure of a semiconductor device 100 according to a first embodiment, and FIG. 2 (a) FIG. 2(b) is a view showing an example of a cross-sectional structure of the semiconductor device 1 of the first embodiment; FIG. 3 is a view showing an example of a cross-sectional structure of the semiconductor device 1 of the first embodiment; FIG. 4 is an example of an overall configuration diagram of a semiconductor device 100b according to the third embodiment; FIG. 5 is an example of an overall configuration of a semiconductor device 100c according to the fourth embodiment; and FIG. 6 is an overall configuration of the semiconductor device 100d of the fifth embodiment. An example of the figure. [Description of main component symbols] 10, 10b, 10c, 15, 16, 17, 18 Internal circuit 11 Internal circuit power supply wiring 12 Internal circuit ground wiring 20, 20d, 20e Peripheral power supply wiring 21, 21d, 21e Power supply potential peripheral power wiring 22'22d > 22e power supply wiring for internal circuit supply of peripheral power supply wirings L 30, 30a, 30b, 30c, 30d, and 30e
3卜31a、31b、31c、31d、31e内部電路電源電位供給用配線 32、32a、32b、32c、32d、32e内部電路接地電位供給用配線 40、40a、40b、40c、40d 半導體晶圓 50 LOCOS 61、62 多晶矽 70 層間膜 71 絕緣膜 80 接觸孔 100、100a、100b、100c、l〇〇d 半導體裝置 Pdv、Pdvf、Pdvl、Pdv2 電源端子塾 23 2010016713b 31a, 31b, 31c, 31d, 31e internal circuit power supply potential supply wiring 32, 32a, 32b, 32c, 32d, 32e internal circuit ground potential supply wiring 40, 40a, 40b, 40c, 40d Semiconductor wafer 50 LOCOS 61, 62 polycrystalline silicon 70 interlayer film 71 insulating film 80 contact hole 100, 100a, 100b, 100c, l〇〇d semiconductor device Pdv, Pdvf, Pdvl, Pdv2 power terminal 塾 23 201001671
Pdg、Pdgf、Pdgl、Pdg2 接地端子墊Pdg, Pdgf, Pdgl, Pdg2 ground terminal pads
Rv、Rva、Rvb、Rvc、Rvd、Rve、Rg、Rga、Rgb、Rgc、Rgd、Rv, Rva, Rvb, Rvc, Rvd, Rve, Rg, Rga, Rgb, Rgc, Rgd,
Rge 配線電阻 - C、Ca、Cb、Cc、Cd、Ce 配線間電容Rge wiring resistance - C, Ca, Cb, Cc, Cd, Ce wiring between wiring
Xv、Xg、Yv、Yg、Uv、Ug、Wv、Wg、Zv、Zg 連接點 24Xv, Xg, Yv, Yg, Uv, Ug, Wv, Wg, Zv, Zg connection points 24
Claims (1)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008136059A JP5396746B2 (en) | 2008-05-23 | 2008-05-23 | Semiconductor device and semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201001671A true TW201001671A (en) | 2010-01-01 |
| TWI455284B TWI455284B (en) | 2014-10-01 |
Family
ID=41372031
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW098109600A TWI455284B (en) | 2008-05-23 | 2009-03-24 | Semiconductor device and semiconductor integrated circuit device |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP5396746B2 (en) |
| KR (1) | KR101330683B1 (en) |
| CN (1) | CN101587876B (en) |
| TW (1) | TWI455284B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20160276265A1 (en) * | 2013-12-06 | 2016-09-22 | Renesas Electronics Corporation | Semiconductor device |
| US20160276287A1 (en) * | 2013-12-06 | 2016-09-22 | Renesas Electronics Corporation | Semiconductor device |
| CN107508455A (en) | 2017-08-25 | 2017-12-22 | 惠科股份有限公司 | Buffer circuit and display device thereof |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01251639A (en) * | 1988-03-31 | 1989-10-06 | Toshiba Corp | Semiconductor integrated circuit device |
| JPH0629395A (en) * | 1992-03-18 | 1994-02-04 | Nec Corp | Semiconductor integrated circuit device |
| JPH0774322A (en) * | 1993-08-31 | 1995-03-17 | Toppan Printing Co Ltd | Integrated circuit with cmos inverter |
| JP3432963B2 (en) * | 1995-06-15 | 2003-08-04 | 沖電気工業株式会社 | Semiconductor integrated circuit |
| JP2834034B2 (en) * | 1995-06-22 | 1998-12-09 | 日本電気アイシーマイコンシステム株式会社 | Semiconductor device |
| JP4390304B2 (en) * | 1998-05-26 | 2009-12-24 | 株式会社ルネサステクノロジ | Semiconductor integrated circuit device |
| JP3236583B2 (en) * | 1999-06-24 | 2001-12-10 | ローム株式会社 | Semiconductor integrated circuit device |
| US6489850B2 (en) * | 2001-03-16 | 2002-12-03 | International Business Machines Corporation | Crosstalk suppression in differential AC coupled multichannel IC amplifiers |
| JP3934507B2 (en) * | 2002-08-08 | 2007-06-20 | 株式会社東芝 | Semiconductor memory device and manufacturing method of semiconductor memory device |
| JP2004241696A (en) * | 2003-02-07 | 2004-08-26 | Seiko Epson Corp | Semiconductor device, its manufacturing method, circuit board, and electronic equipment |
| KR100583458B1 (en) * | 2004-01-28 | 2006-05-26 | 삼성전자주식회사 | Printed Circuit Board |
| JP4367700B2 (en) * | 2004-03-30 | 2009-11-18 | 株式会社ルネサステクノロジ | Semiconductor integrated circuit device |
| JP2006196803A (en) * | 2005-01-17 | 2006-07-27 | Toshiba Lsi System Support Kk | Semiconductor device |
| JP5196868B2 (en) * | 2006-06-16 | 2013-05-15 | キヤノン株式会社 | Printed circuit board |
-
2008
- 2008-05-23 JP JP2008136059A patent/JP5396746B2/en active Active
-
2009
- 2009-03-13 KR KR1020090021571A patent/KR101330683B1/en active IP Right Grant
- 2009-03-24 TW TW098109600A patent/TWI455284B/en active
- 2009-03-31 CN CN200910130699.2A patent/CN101587876B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| KR101330683B1 (en) | 2013-11-18 |
| KR20090122112A (en) | 2009-11-26 |
| CN101587876B (en) | 2013-07-31 |
| JP2009283792A (en) | 2009-12-03 |
| JP5396746B2 (en) | 2014-01-22 |
| TWI455284B (en) | 2014-10-01 |
| CN101587876A (en) | 2009-11-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7042303B2 (en) | Energy conditioning circuit assembly | |
| US7593208B2 (en) | Multi-functional energy conditioner | |
| TWI293765B (en) | Planar inductor with segmented conductive plane | |
| TW488061B (en) | Apparatus for current ballasting ESD sensitive devices | |
| CN101930973B (en) | Electrostatic discharge structures and methods of manufacture | |
| EP1251559A2 (en) | Multiple terminal capacitor structure | |
| JP2000504497A (en) | Semiconductor integrated circuit with inductor | |
| CN105957712B (en) | Split type thin film capacitor for multivoltage | |
| TW201001671A (en) | Semiconductor device and semiconductor integrated circuit device | |
| TW201003868A (en) | Shielded integrated circuit pad structure | |
| TWI245419B (en) | High frequency semiconductor device | |
| US7253516B2 (en) | Electronic device and carrier substrate for same | |
| CN108573970A (en) | Protective device | |
| US5365103A (en) | Punchthru ESD device along centerline of power pad | |
| JP2003501992A (en) | Multi-function energy regulator | |
| US6961247B2 (en) | Power grid and bump pattern with reduced inductance and resistance | |
| TW200917289A (en) | Spiral inductor device | |
| TWI253741B (en) | Gate-coupled ESD protection circuit for high voltage tolerant I/O | |
| US20190348363A1 (en) | Semiconductor devices having electrostatic discharge layouts for reduced capacitance | |
| JP2002164509A (en) | Semiconductor device | |
| JP2003163278A (en) | Protection of integrated circuit against electrostatic discharges and overvoltages | |
| JP2004165246A (en) | Semiconductor device | |
| JP2004221260A (en) | Semiconductor device | |
| JP4000815B2 (en) | Semiconductor device | |
| WO2008015213A1 (en) | Distributed esd protection |