TW200947865A - Limit signal generator, PWM control circuit, and PWM control method thereof - Google Patents

Abstract

A PWM control circuit is disclosed. An oscillator generates a triangular signal, received by a limit signal genenerator to produce a limit signal accordingly. Corresponding to a rising period of the triangular signal, the limit signal sequentially experiences a first holding period, a rising period and a second holding period, wherein the limit signal has a first predetermined value during the first holding period and a second predetermined value during the second holding period. A compare/control circuit compares the limit signal with a detection signal corresponding to a current through a power switch, and controls the power switch accordingly.

Description

200947865 IX. Description of the invention: [Technical field to which the invention pertains] - This description relates to a power supply, particularly for pulse width modulation (Pulse Width) used in a power supply.

Modulation, PWM) control circuit. [Prior Art] In the switching power supply, PWM technology has been widely used to control or adjust the output power. In order to prevent the power supply from being permanently damaged, more than 5 noon protection circuits, such as over voltage and over current circuits, are built into the power supply. Among them, the limitation of output power is generally used to protect against overload (overl〇ad) or output short circuit. Please refer to FIG. 1 , which is a conventional PWM power supply 100 . The controller 106 can generate a PWM signal to control whether the power switch 1 〇 2 is turned "ON" or "OFF". When the power switch 1〇2 is turned on, the power supply voltage VIN charges the primary coil of the transformer 104 so that the current flowing through the main winding gradually increases. When the power switch 1〇2 is turned off, the energy stored in the transformer 104 is discharged by charging the output capacitor through the secondary coil. The resistor Rcs is connected in series with the power switch 102, so its voltage across the Vcs is the current flowing through the power switch 1〇2 and/or the main winding. When the voltage across the voltage Vcs is greater than or equal to a certain value, such as the value indicated by the limit signal Vlimit, it means that the flow through the power switch 102 will continue to increase according to the shutdown of the 200947865 controller 106. In other words, the maximum output of the source supply 100 and/or the current of the main winding is excessively risky, and the closed power switch 102' stops the electrical limit signal VLIMIT of the main winding to limit the PWM output power. However, if the limit signal VLIMIT θ ^ is a constant, the maximum output power can be changed due to the signal propagation delay of the switch, and the power supply voltage Vin changes.

change. When the voltage across the voltage is greater than or equal to the limit signal, when the controller 106 actually turns off the power switch 102, a signal delay time tDELAY is required. During this signal delay time, the current of the main winding will still increase, and the increase will be proportional to the value of the current power supply voltage VIN. Therefore, the true maximum output power increases as the power supply voltage VIN becomes larger. U.S. Patent No. 6,674,656 (hereinafter referred to as the 656 patent) provides a solution (PWM controller having a saw-limiter for output power limit without sensing input voltage). Figure 2 is a simplified illustration of a method concept in the '656 patent. In the '656 patent, the limit signal VLIMIT is not a constant. The waveform converter 202 receives the saw-tooth signal output from the oscillator 204, and then generates a limit signal vLIMIT as shown in FIG. 2 after each adjustment of the slope, the clamp processing, and the level shift. . In each cycle, the limit signal VLIMIT changes over time, initially rising from a minimum voltage' and finally clamped to a maximum voltage. Figure 3 shows the waveform of VlAMIT with limit letter 200947865, and the wave of two voltages across voltage V. Among them, the VS (viNHiGH) represents the voltage across the V-shape when the power supply voltage Vw is high, Vcs( V_w) means that the power supply is repeated: wave ~ waveform. From Fig. 3, it can be found that the power supply second power "VCS (V, _GH) also rises faster" will encounter a lower limit; W, thereby improving the signal delay time possible:: Unstable rate (4) Questions. Large Output Power ❹ SUMMARY OF THE INVENTION The present invention provides a limiting signal generator for converting a signal to a limit signal. The limit signal has a - first - flat = wave - brother - one flat interval, and a rising interval. When the ice-曰: period begins to rise, the limit signal is sequentially (-♦ the rising interval, and the second flat m-limit signal generator includes a search for a thousand S. The device, and a second Clamping test Μ 盗 、 — — — — — — — — — ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° The value in the rising interval. The first value, the first J lj signal is - the first preset second in the first - flat interval; and the limiting signal is a containment-concussion in the second flat interval: A pulse width modulation (PWM) control circuit 'packet σ, a limit signal generates a crying, a power comparison controller. The earthquake generates a power switch, and a 0 generates a two-wave signal. The limit signal is produced in 200947865 Benefit to receive the triangle wave Lumei, the land / according to the birth - (four) (6) tiger. The limit ^ tiger has a brother - a flat interval, a second flat interval, and a rise = = = = signal in the rise period of the week , the limit: - bracket: "4 brother - flat interval, the upper The interval and the second flat interval. The limit #•办-value is - the preset - the preset between the second and the preset value is a preset value of the second brother. The corresponding flow through the power switch The thunder, ^ from ^ 匕 乂 乂 乂 ] ] ] ] ] ] ] 关 关 关 关 关 , , , , , , , , , , , , , , , , , , , , , , , 一 一 一 一 一Pulse wave width phase change control method. First receive - two angle wave nickname. When the triangle wave = line the following steps '(4) a limit letter:: liter = level =: make the limit signal gradually from the first preset value Rising to a first: pre-quote value, and 3) in a _# j in a thousand Q, so that the limit signal is maintained at a second: pre-value: comparing the limit signal with a corresponding flow through a power switch The above-mentioned and other objects, features, and advantages of the invention will be more apparent. 1. The following is a preferred embodiment of the invention. And the detailed description is as follows: Port, 讣峄路_1 is a power supply for the power supply according to the embodiment of the present invention. Benefit 400 is - flyback power conversion α '匕3 has power switch 402, transformer 404, disc 406, limit 200947865 signal generator 408, comparator 41 〇, controller 412, resistor Rcs, two poles The body 414 and the rectified load capacitance c. The controller 412 controls the power switch „402 to be turned off or on to control the charging of the transformer 4〇4 or the discharging 407 state. The resistor Rcs detects the current flowing through the main winding of the transformer 404 and is also used to control the output power of the power supply 4〇〇. The oscillator 4〇6 outputs a corner wave #号V〇sc to the limit signal generator 408, and the limit signal generator 408 outputs the limit signal VuMiT accordingly. The limit signal generator ❹ 408 will be explained in detail later. The comparator 41 〇 compares the limit signal ν [_ with the voltage across the voltage Vcs generated by the resistor RCS, and the controller 412 controls the power switch 402 in accordance with the output of the comparator 410. Please refer to Fig. 4B' for the timing relationship between the limit signal VLIMIT generated by the limit signal generator 408 and the triangular wave signal v〇sc. Each cycle of the triangular wave signal v〇sc has a rising interval Prise and a falling interval Pfall. The limit signal Vlimit has three intervals with respect to the rising interval Prise of the triangular wave signal V〇sc, and the timing is sequentially the flat interval pHL, the ❹ rising interval PR, and the flat interval Phh. When the limit signal Vumit is in the flat interval pHL, the limit signal Vlimit is held at a certain preset value, for example, the voltage vH0LD_MIN; when the limit signal Vlimit is in the rising interval Pr, the limit signal vL1MIT gradually decreases with the voltage Vh〇ld min over time. Rising, finally reaching another predetermined value, such as voltage vh〇ldmax; when the limit signal VLIMIT is in the flat interval PHH, the limit signal vLIMIT is held at the power supply 400 in the voltage Vhold-max 0 in FIG. 4A because In Figure 4B, 11 200947865 limits the signal VlimIT ' so it can provide a more stable start-up output current, so that the output voltage V 〇 rises faster from the 0 potential at power-on. When the power supply source 400 is just beginning to be connected to the power supply, the cross-voltage of the rectified load capacitance C〇 is very low or almost equal to zero because it has not been charged, and therefore can be regarded as the secondary winding of the transformer 404 ( The cross-over voltage Vs on the secondary coil is close to zero. At this time, the voltage across the main winding VP (= VS * NP / NS) is also close to 〇, where NP and Ns are the number of coils of the main winding and the secondary winding, respectively. Therefore, the transformer 404 starts to supply power at the power supply voltage VIN, and when the power switch 402 is turned on, it will exhibit the characteristics of the transformer, not storing energy in the transformer 404, but passing the energy of the main winding directly from the secondary winding. Output. Therefore, a considerable amount of current flows through the main winding at a moment, and at the same time, a corresponding current is induced to flow through the secondary winding to charge the rectified load capacitor C?. The instantaneous large current flowing through the main winding is determined by the resistor Rcs and the current limit signal VLIMIT. When the rectified load capacitance C〇 is charged to a certain degree, when the power switch ❹ 402 is turned on, the voltage across the rectified load capacitor C〇 prevents the induced current of the secondary winding from charging it. At this time, the main winding of the transformer 404 is equivalently decoupled from the secondary winding, exhibiting a general single inductance characteristic, so that the reluctance of the main winding of the transformer 404 causes the current through the main winding of the transformer 404 to follow. The nature of time passing and linearly increasing. Figure 5A shows the possible problem with the limit signal V LIMIT in Figure 2. Figure 5A also shows the signal change in one cycle of Figure 3, the same as the power of 12200947865 when it is erected...~Η, electricity=electricity [the resistance of Rcs when VVIN is low, Vcs^, and the voltage of turn-off voltage. It is the resistance Rcs_ w when it is just turned on. . From the figure, the voltage V- and the voltage across the WL can be seen, the limit signal (4) w different power supply ν νπ ^ ^, to provide different levels of ❹ and two: Tiger Vlimit ′ and produce the desired signal delay compensation effect. However, 1 2 5 Α * map can also be known, Vcs-P ·. It will be limited to a very low value because the limit signal _ is quite low at the beginning of the second two. Also: :, : = Using the limit signal V_, - in Figure 2 to start the negative, the battle 冤 c c〇 this 垔 will be very limited. In case, the load: C◦ in parallel with other resistive loads, the 嶋^晴 in Fig. 2 may even lead to the round-out of the power, the vo can not reach the expected value of the error, the Ludi 5B picture shows the limited Yuelu in Figure 4b The result of the corpse _ 咕. The first UMIT may be generated at the same time ^= also the signal change of the one cycle of the 4A figure, the power supply Γνι=the resistance of the voltage v'n high, Han, ~, V. Very low (also: H cs_ w and the cap 5B = just: machine soon) resistance Rcs across the pressure v_. And V A is the same as VcsPH in Fig. 5 by the second picture = Γ, 'the phase _ signal delay compensation effect is not repeated. It is set at the beginning of a higher quasi-two VVUMIT ^ — cycle. That is, 1 1 kg 乂 Vcs-p-〇 will have a higher output 疋 5 brothers, if you use the limit signal VLIMIT in the figure, _ 13 200947865

The energy transmitted to the load capacitor at the start of power-on is relatively large compared to the result of Figure 5A, and therefore there is no comparison of the output voltage V0 after power-on. The erroneous result of the expected value cannot be reached. The simulation also confirms that the output voltage V〇 generated by using the limit signal Vlimit in FIG. 4B will reach the desired certain voltage output faster than the output voltage V〇' generated by the limit signal Vlimit in FIG. value. Figure 6 has a limit signal for generating the picture in Figure 4B

A limit signal generator 600 of Vlimit. The limit signal generator 600 is used to convert a triangular wave signal Vosc generated from an oscillator 602 into a limit signal Vlimit. In Fig. 6, the limit signal generator 600 linearly adjusts the triangular wave signal Vosc by the adder 606 and the multiplier 610 to generate another triangular wave signal (i.e., an adjusted signal) 611. The adder 606 subtracts the triangular wave signal V OSC from the offset signal v SHIFT , that is, adjusts the DC level. The multiplier 610 receives an output of the adder 606 and performs slope adjustment to generate a triangular wave signal 611. Because of the linear adjustment, the difference between the triangular chopping signal 611 and the triangular wave signal Vosc is different between the slope and the DC quasi-bit, and the period is substantially the same as the corresponding rising and falling switching starting point. The triangular wave signal 611 is then clamped by the clampers 612 and 614. If the triangular wave signal 611 is higher than a preset value set by the clamp 612, for example, the voltage Vh 〇 LD - MAX 5, the clamp 612 holds the limit signal Vlimit at the voltage Vhold-max. Relative 'If the dichroic signal 611 is lower than a preset value set by the clamp 614, such as voltage 14 200947865 VH 〇 LD-MIN, the clamp 614 will hold the limit signal VuMIT at V - if the triangular wave signal The value of 611 is between Vh〇ldmax and VH0LD_MIN, and the output value of the signal Vlimit is limited to the value of the triangular wave signal 611'. Therefore, as shown in Fig. 4B, the limit signal v is τ, and the rising interval P of the triangular wave signal V〇sc is sequentially entered into the flat interval PHL, the rising interval Pr, and the other flat interval Phh. The addition state 606 and the multiplier 610 together determine the value of the limit signal Vumit when it is in the up range Pr. The clamp 612 holds the limit signal Vlimit at Vh 〇 ld_max when the limit signal Phh is held; the clamp 614 holds the limit signal Vlimit at VH0LD-MIN when the limit signal Vlimit is at the flat interval PHL. Fig. 7 is a circuit diagram of the limit signal generator 6 〇 0 in Fig. 6. Of course, Fig. 7 does not limit the implementation of the present invention, and the limit signal generator 600 can also be implemented by a circuit different from Fig. 7. The voltage-to-current converter 702 converts the triangular wave signal v 〇 sc into a current signal 〇 I 〇 sc. The voltage-to-current converter 702 has a comparator OPosc, a resistor R〇sc, a switch Sosc, and a current mirror formed by two transistors. The voltage-current converter 7〇4 converts the offset signal Vshift into a current signal ISHIFT. The voltage to current converter 704 has a comparator 〇pSHIFT, a resistor Rshift, and a switch SSHIFT. The current signal IsmFT is subtracted from I〇sc and passed through two current mirrors to the gain resistor Rscale. The gain resistor Rscale can be regarded as a multiplier, and the ratio of the resistance value to the resistance value of the resistor R〇sc can determine the rising slope of the limiting signal Vlimit in the rising interval Pr and the ratio of the rising slope of the triangular wave signal V〇sc. . In the seventh 200947865 diagram, the clamp 612 is a right L-, a ~ comparator 706, and a switch 710. If the voltage of the voltage VSCALE is higher than the voltage Vh〇ld-max, the comparator 706

The output will turn on the switch 710, and the AL chasing the limit signal Vlimit is pulled down by a low voltage source, so that the limit signal v 1 〇唬 is greater than the voltage Vhold_max ,, and the clamp DD "λ 〇 gt" in Fig. 7 State 614 has a comparator 708 and a switch 712. If the voltage ν. The voltage of SCalb is lower than VH0LD-MIN, the output of compare 706 turns on the open _k switch 710' forces the limit signal Vlimit to be a high voltage source VDD. Pull-up, eclipse 1 β makes the piece limit signal VLIMIT not less than the voltage Vhold-min.

When the SCALE is between the voltage Vh〇LD -MAX and the voltage Vhold^n

At T switch 712 and switch 710 are both off, so the limit signal VT A » MIT will be dedicated to voltage VSCA; LE. In other words, the clampers 612 and 614 together draw the electrical Vscale between the voltage Vhold-max and the voltage VH(10) to turn the limit signal VL skin out. The address signal generated by the embodiment of the present invention can make the output voltage of the power supply rise rapidly from 0 to 0, and can prevent the output voltage from being turned on due to the power of the transformer. Too small, causing problems with boot failure. Although the present invention has been disclosed in the preferred embodiments as above, it is not intended to be used in the present invention, and any general knowledge in the technical field to which the present invention pertains may be made in the spirit and scope of the present invention. /71Following The scope of this Maoming protection is subject to the definition of the patent application scope. [Simplified illustration] 200947865 Figure 1 shows a conventional PWM power supply. Figure 2 A method concept in the '656 patent. Figure 3 shows the waveform of the limit signal _VliMIT generated according to the implementation of the '656 patent, and the waveforms of the two vcs. Figure 4A is a power supply according to an embodiment of the present invention. Figure 4B is a timing diagram of the generated limit signal Vlimit and the triangular wave signal V OSC according to an embodiment of the present invention. 〇 Figure 5A shows a problem that may occur in the limit signal VLIMIT in Figure 2 .

Fig. 5B shows the possible result of the limit signal V LIMIT in Fig. 4B. Figure 6 has a limit signal generator for generating the limit signal V LIMIT in Figure 4B. Fig. 7 is a diagram showing an example of circuit implementation of the limit signal generator in Fig. 6. [Main component symbol description] 100 PWM power supply 106 controller 102 power switch 104 transformer 202 waveform converter 204 oscillator 17 200947865 400 power supply 402 power switch. 404 transformer 406 oscillator 408 limit signal generator 410 comparator 412 Controller 414 Diode ❹ R Resistor c〇 Rectified Load Capacitor 600 Limit Signal Generator 602 Oscillator V〇sc Triangle Wave Signal Vlimit Limit Signal 606 Adder © 610 Multiplier 611 Triangle Wave Signal VsHIFT Offset Signal 612 Clamp 614 Clamp 702 Voltage to Current Converter 704 Voltage to Current Converter OP osc Comparator 18 200947865

Rose resistance S〇SC switch OP SHIFT comparator Rshift resistance SsHIFT switch Rscale gain resistor 706 comparator 710 switch 708 comparator 712 switch V〇 output voltage Vin supply voltage P FALL falling interval Prise rising interval Phl P HH flat interval IsHIFT current signal Ves-PH cross voltage VDD still voltage source Ves-PL cross pressure Ves-po cross pressure 19 200947865

VcS-I-H Trans-voltage VcS-I-L Trans-voltage Vcs-I-O Trans-voltage Vcs Trans-voltage Vh〇LD-MAX Voltage Vh〇LD-MIN Voltage VcS(VlNLOW) Voltage VcS(VlNHIGH) Voltage Ο

Claims (1)

200947865 X. Patent application scope: 1 · A limiting signal generator for converting a triangular wave signal into a - limiting signal having a first flat interval, a second flat interval, and a rising interval When the triangular wave signal starts to rise in the -period, the limit signal sequentially enters the first flat interval _ding period, the ±liter interval, and the second flat: the limit signal generator includes: ❹ a multiplier (SCaler) 'to determine the slope of the limit signal between the rises F; an ^adder' is used to subtract the triangular wave signal from the -offset to determine the off signal at the rise The value in the interval; The second brother-clamper causes the limit signal to be in the first-level interval, and the second clamper is the second preset value. 2, as claimed in the patent scope, the adder includes: a limit signal generator for causing the limit signal to be in the second flat interval, wherein: -π咏2 month wave signal corner wave current; and - The two voltage-current converters are replaced by -off currents; the difference between the purely shifted signal signal and the current is outputted by the Hecha adder and the offset current 21 200947865 3. The limit as described in claim 1 a signal generator, wherein the multiplier includes a first resistor, and the adder includes a second resistor, and a ratio of the resistance of the first resistor to the second resistor affects a rising slope of the limit signal in the rising interval. 4. The limit signal generator of claim 1, wherein: the adder receives the triangular wave signal and the offset signal; the multiplier receives an output of the adder to generate an adjusted signal; The first clamper and the second clamper monitor the adjusted signal, and the adjusted signal does not exceed a first preset value and a second preset value. 5. The limit signal generator of claim 4, wherein the / first clamp comprises: a first comparator for comparing the adjusted signal with the first preset value; A tight one switch is controlled by one of the outputs of the first comparator, and has a first end and a second end, respectively receiving a high power supply and the adjusted signal. 6. The limit signal generator of claim 5, wherein the second clamp comprises: a second comparator for comparing the adjusted signal with the second preset value, and a The second switch is controlled by one of the outputs of the second comparator, having a first end and a second end of 22 200947865, respectively receiving a low power and the adjusted signal. 7. The limit signal generator of claim 1, wherein the first preset value is lower than the second preset value. 8. A pulse width modulation (PWM) control circuit, comprising: an oscillator for generating a triangular wave signal; a limiting signal generator for receiving the triangular wave signal, and a production limit of the number 5 The limit signal has a first flat interval, a first flat interval, and a rising interval. When the triangular wave signal rises within a week/month, the limit signal sequentially enters the first flat interval: the rise (4) and the second flat interval, the limit signal is a first preset value in the first flat interval, and a second preset value in the second flat interval; a power switch; and a first comparison The controller compares the value of a 9 corresponding to the current flowing through the power switch to the limit signal, and controls the power switch accordingly. 9. The pulse width modulation control circuit of claim 8, wherein the first preset value is lower than the second preset value. The pulse width modulation control circuit of claim 8, wherein the limit signal generator comprises: a multiplier for determining a slope of the limit signal in the rising interval; An adder for subtracting the triangular wave signal from an offset signal 23 200947865 , to determine a value of the limit signal in the rising interval; a first clamp to cause the limit signal to be in the first hold And the second preset value; and the second clamper, the limiting signal is the second preset value in the second flat interval. β f 11. A pulse width modulation control method, comprising: receiving a triangular wave signal; when the sky angle signal is in the rising range of one week, the following steps are performed according to the library and the good line to output a limit signal , : 4 enters a first flat interval, so that the limit signal is maintained at a first preset value; 'in a rising interval, the limit signal is gradually increased from the first preset value to - the second pre- Setting a value; and in the second flat interval, maintaining the limit signal at the second predetermined value; and comparing the limit field with a detection signal corresponding to the current flowing through a power switch, and To control the power switch. 12. The pulse width modulation control method of claim 11 further comprising: secretly adjusting the triangular wave signal to generate an adjusted signal; and pushing the adjusted signal to the first preset The value is between the second preset value to output the limit signal. twenty four