200947514 九、發明說明： 【發明所屬之技術領域】 本發明係關於—種形成絕緣結構的方法。特定言之， 本發明係關於-種形成科過路閘極⑽麵g㈣的自對準 絕緣結構的方法。 【先前技術】 ❹ ❹ 在動機存取έ己憶體（DRAM)製程的發展中，為 f要增加晶片上的元件密度’會安排字讀（w〇rdHne) 從上方路過」其他未受此字元線控制的深溝渠電容，以 有效提高積集度(integmiGn)。第1，例示字元線從上方 路ϋ其他未TJt字TL線控制的㈣渠電容。如第^圖所 =在佈局圖案上’各別字元線101從主動區域102、深 及淺溝槽隔離_上方跨過，其中在尚未製 103日夺’基板中只有淺溝槽隔峨T)及主動 搬。由於字元線非】為淺溝槽隔離(STI)的區域即為主動區域 m ; 、、01與主動區域102重疊的部分才會形成 因频切「料」非絲區域 渠電谷的字元線部分即被稱為過路閘極刚。」 溝渠電容的上方要從其他的記憶胞(memory ceI1)之深 性元件，因此同時過路_與深溝渠電容都是電 緣社楢⑼ 閉極與深溝渠電容之間建構-声絕 I。構，，過路_溝渠電容間的電絕：： 200947514 圖所示絕緣結構105即作為過路閘極i〇4與深溝渠電 谷 邑、、表之用。應注意，在第丨圖中僅圖示出一絕緣結 一 而省略了其他不完整的絕緣結構105，但此並不表 示’、他。的深溝渠電容上方無絕緣結構。 、胃過㈣極要從淺溝槽隔離與深溝渠電容的上方路 過^順序上，通常是先製作淺溝渠隔離、然後形成深溝 渠電:、、再定義過路間極之絕緣結構。第2-8圖即例示傳 〇、先上疋義過路閘極之絕緣結構之步驟。首先，如第2圖所 丁在基材2〇1中製作完成淺溝渠隔離搬後，再形成深 溝渠電谷203。形成深湛里a 取*木溝渠電各203的步驟可以是先蝕刻 出電容溝渠的輪靡，秋德 w力“、、優擴大溝渠電容底部成為瓶狀以提 昇内表面積，隨後建立1 /、他u卩分，例如頸部氧化層，再回 填導電材料’例如發。形忐、、吨、盘 、 v成/木溝渠電容203後，開始進行 各式所需之離子井佈植（岡土 、圖未示）、清洗、高溫回火等之製 〜 程。其次，如第3圖所夼 .^ 0 1 R ’在基材201上全面地依序形成 概塾氧化層204與氮化石夕層2〇5，以便之後使用光阻來定 義絕緣結構的位置。之後，如第4圖所示，形成抗反射層 (BARC) 206’並使用〜圖案化之光阻2〇7定義出過路問 極之絕緣結構的位置，此時光阻2〇7應該要準確的覆蓋在 淺溝渠隔離202與溝渠電容2〇3上，以確保過路閘極的絕 緣結構具有正確的位置。 跟著’如第5 ®所示’利雜刻法移除部分的抗反射 層206與氮化矽層205。然後，如第6圖所示，移除剩餘 200947514 的光阻207與抗反射層2〇6而 ^下所1¾之氮化石夕層205彻 襯墊氧化層204，此時氮化矽a μ 日^)與 卞亂化秒層205即作為硬遮罩 再來，如第7圖所示，利用翁 早<用 扪用虱化矽層205作為硬適置 由蝕刻移除未被氮化矽層2〇5 ''' ! ^ ^ m ^ 3所覆盍的墊氧化層204。接 者’如第：圖所不’形成1極氧化層(圖 ： 習知的方式在間極氧化層上建立問極2 ^據 205上建立過路閘極22〇。此 社乳化石夕層 此時，理論上來說，過路閘極 ❹220此特即應該位在深溝渠電容2 中未被移除的氮切層挪斑執〃換吕之’弟7圖 層 與墊氧化層204即作為過路閘 極22:緣結構22丨。而間極⑽則啊^ 203並構成-記憶胞(memGry ,。於是絕緣結構2 保過路閘極220 ij：下方盔M , _ 、/、下方無關之溝渠電容203有良好的絕 緣避免短路免影響動態隨機存取記憶體的正常操作。 然而，前述的製程不但需要使用一額外的光罩來定義 ❹絕緣、、’。構221的位置’而且要將絕緣結構221，亦即氮化 石夕層2〇5鱗氧化層204，幾無對準偏差(misalignment)地 定義在深溝渠電容203的上方亦是-件非常困難的工作。 另外’在絕緣結構221完成前並不能產生足夠的保護作 用’使得暴露的淺溝槽隔離202與深溝渠電容203免於離 子井佈植、凊洗、高溫回火等製程可能造成的傷害。 於是急需要一種形成絕緣結構的新穎方法，不但可以 免除使用額外的光罩來定義絕緣結構位置的步驟、不用解 決在建立絕緣結構時必需與已經存在的深溝渠電容間精確 7 200947514 對準的問題’在絕緣結構完成前也能保護基材、淺溝槽隔 離與深溝渠電容使之不會暴露出來，避免當其他區域的建 立過程中可能受到的波及與傷害。 【發明内容】 本發明於是提供—種形成用於過路閘極的絕緣結構 的新穎方法’亦即’在移除定義深溝渠開口的硬遮罩前， ❹就直接使用溝渠㈣口作為建立第—氧化層與第一石夕層的 依據，而成為日後的絕緣結構。所以，一方面省卻了使用 額外的光罩來定義絕緣結構位置的代價，另一方面，第一 氧化層與第-梦層又能以自對準㈤f alignment)的方式 精確地形成在冰溝渠之上，自動地解決了絕緣結構與溝渠 電合間對準的問題’完美地達成了絕緣結構能準確覆蓋深 溝渠電容的要求。還有，在絕緣結構完成前，襯塾氧化層、 © 層與^氧化層—起使得基材、淺溝槽隔離與深溝 渠不a暴路出來。所以還能夠保護基材、淺溝槽隔離與深 溝渠不受到其他區域的建立過程中可能的傷害，可以一次 解決前述的三項問題。 本發明所提供形成自對準(self align)絕緣結構的方 法’百先，提供-基材。基材中包含填滿妙之深溝渠以及 鄰接深溝渠之淺溝槽隔離。基材上依序包含襯墊氧化層與 硬遮罩纟中襯塾氧化層與硬遮罩一起定義了深溝渠之開 口。其次進行-氧化步驟，使得料表面形成第—氧化層， 200947514 其中第-氧化層即作為所需的絕緣結構。然 層以覆蓋第-氧化層。再來·遮Π 後，在絕緣結構上建立過路閘極。 本發明又提供一種半導體結構，其包含位於基材中， 填滿石夕之深溝渠、位於料面㈣輕緣結 層、位於第-氧化層上之第-珍層、位於第 極、以及與深溝渠鄰接之淺溝槽隔離。 〇 Ο 【實施方式】 本發明在於提供—種形仙於過路閘極的自對準 (rriign)絕緣結構的新穎方法，其中既免除使用額外的光 罩來定義絕緣結構的位詈、一從初 貝卜的九 . 併解決絕緣結構與深溝渠電 問：，在絕緣結構完成前淺溝槽隔離與深 虚深、》冓:電::二：出來’可有效保護暴露的漫溝槽隔離 :;程:::幅提升動態隨機存取繼一等 第9.Π關林發明形成絕緣結翁法之—較佳實 施例。首先，如第9圖所千 ^ 中包含填滿石夕311之深、、⑽:基材3G1。基材3〇1 深溝渠”。之淺溝槽隔=2 Γ電容之用’以及鄰接 氧化層331與硬遮基材⑽上依序包含襯塾 …基材3〇1之二情3要’深溝渠31°中的 1 了以進一步包含一複合材料層312, 9 200947514 例如由氧化物-氮化物-氧化物（ΟΝΟ)所組成之複合材料 層，用來當作電容介電層。此外，深溝渠310中還可以包 含其他之結構，例如瓶形底部（bottle bottom )或是頸部氧 化層。 ------w…加y 丁 組巫竹，例如呀 〇 硬遮罩332可由氮化物、氮氧化物、碳化物或其複合層所 組成’例如氮化石夕、氮氧化石夕、碳化石夕等。概塾氧化層％ 則包含錢化物。在本發明之較佳實施财，淺溝槽隔離 =形成在深溝渠310之前。例如，先在基材3〇ι上依 ，：統之溝槽隔離製程定義出淺溝槽隔離32〇。狹 =:與_步歡義出圖案化的硬遮罩说，独 卜概塾氧化層331與幾溝槽 : 冰溝渠310，使得深溝渠31〇 木❿風 其中。深溝渠3K)形成後、可溝槽隔離細位於 部成為瓶狀並建立其他部分 續大深溝渠電容底 電材料，例如矽扣，以完成深顯部氧化層，再回填導 皆為熟習相關技藝者與通常知^渠310的製作。至此， 述。但值得注意的是，從蝕刻二=熟知，在此不多加贅 渠電容之時，都不要移除硬遮渠310 一直至完成深溝 由於位於基材301上的_ 3，° 332，共同具有定義深溝渠虱化層331與硬遮罩 留硬遮罩332的用意，係在省去之開〇 314。因此本發明保 的目的，亦即直接使用深溝渠^〜步光罩以達到自對準 〇之開口 314來定義用於 200947514 過路開極之絕緣結構的位置。 其-欠，如第ίο圖所示，如果深溝渠31〇中已經形成 有複合材料層312時，要先行移除暴露出之複合材料層 312。例如，若是複合材料層312由氧化物-氮化物氧化物 所組成，可以使用熱磷酸的條件來移除複合材料層。 接下來，請參考第u圖，進行一氧化步驟，將深溝 渠310中石夕3U的表面氧化形成第一氧化層315。此等第 ❹ A化層315即將作為部分絕緣結構之用。其可以使用熱 氧化法來形成第-氧化層315，例如使用乾式熱氧化法或 濕式熱氧化法來形成第一氧化層315。較佳者，第一氧化 層315與鄰近的襯墊氧化層331 一起保護基材3〇1、深溝 渠310與淺溝槽隔離32〇。 然後’於開口 314中形成石夕層34〇以覆蓋第一氧化層 315。石夕層340可以是使用化學氣相沉積法所形成的非晶 _石夕、多晶石夕或是其組合。形成石夕層34〇的方法可以是，如 第12圖所示，例如使用化學氣相沉積法使得石夕们4〇全面 性的共形覆蓋在第—氧化層315與硬遮罩332上。然後， 如第13圖所示，再使用化學機械研磨等之平坦化製程移除 多餘的石夕層340 ’使得第1層341覆蓋第一氧化層 與部分的硬遮罩332。在化學機械研磨之後，較佳者，第 一石夕層341會在第一氧化層315上，從側視角度來看，形 成不對稱的U形結構。第1夕層341的厚度可以介於％ 埃（angstrom, A)-40〇A 之間。 200947514200947514 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to a method of forming an insulating structure. In particular, the present invention relates to a method of forming a self-aligned insulating structure of a pass gate (10) face g (d). [Prior Art] ❹ ❹ In the development of the MV process, the component density on the wafer is increased by f. The word read (w〇rdHne) is passed from above. Others are not affected by this word. The deep trench capacitance controlled by the element line is used to effectively increase the integration (integmiGn). First, the (4) channel capacitance controlled by the other word lines not controlled by the TJt word from the top of the word line. As shown in Fig. = on the layout pattern, the individual word lines 101 are crossed from the active area 102, the deep and shallow trench isolation_, and only the shallow trench isolation T is in the substrate. ) and take the initiative to move. The area where the word line is not the shallow trench isolation (STI) is the active area m; the part where the 01 and the active area 102 overlap will form the character of the channel in the non-wire area of the "material". The line portion is called the crossing gate. The top of the trench capacitor is from the deep component of other memory cells (memory ceI1). Therefore, both the pass-through and deep-ditch capacitors are electrically connected (9) between the closed-pole and deep-ditch capacitors. Structure, the way of passing _ trench between the capacitors:: 200947514 The insulation structure 105 shown in the figure is used as the overpass gate i〇4 and deep trenches, and the table. It should be noted that only one insulating junction is illustrated in the first drawing and other incomplete insulating structures 105 are omitted, but this does not mean ', he. There is no insulation structure above the deep trench capacitor. The stomach (4) should be separated from the shallow trench isolation and the upper channel of the deep trench capacitor. Usually, the shallow trench is isolated first, then the deep trench is formed: and the insulating structure between the vias is defined. Figure 2-8 shows the steps for transmitting the insulation structure of the pass gate. First, as shown in Fig. 2, after the shallow trench is isolated and formed in the substrate 2〇1, the deep trench electric valley 203 is formed. The step of forming a deep zhili a _ _ wood trench can be etched out of the rim of the capacitor trench first, the Qiu De w force,, and expand the bottom of the ditch capacitor into a bottle shape to enhance the internal surface area, and then establish 1 /, he u 卩, for example, the neck oxide layer, and then backfilling the conductive material 'such as hair, shape, ton, disk, v into / wooden ditch capacitor 203, began to carry out the various types of ion wells required (Oka, The figure is not shown), cleaning, high temperature tempering, etc. Next, as shown in Fig. 3, ^ 0 1 R 'completely forms a general oxide layer 204 and a nitride layer on the substrate 201. 2〇5, in order to use the photoresist to define the position of the insulating structure. Then, as shown in Fig. 4, an anti-reflective layer (BARC) 206' is formed and a patterned photoresist is used to define the crossing. The position of the insulation structure, at this time, the photoresist 2〇7 should be accurately covered on the shallow trench isolation 202 and the trench capacitor 2〇3 to ensure that the insulation structure of the pass gate has the correct position. Follow the '5® Removing the portion of the anti-reflective layer 206 from the tantalum nitride layer 205 Then, as shown in FIG. 6, the remaining photoresist layer 207 of 200947514 and the anti-reflection layer 2〇6 are removed, and the nitride layer 205 of the nitride layer 205 of the lower layer is removed, and then the tantalum nitride a μ day. ^) and the disordered second layer 205 is used as a hard mask again, as shown in Fig. 7, using the 翁 & 扪 扪 虱 虱 205 205 205 205 205 205 205 205 205 205 205 205 205 205 205 Layer 2〇5 ''' ! ^ ^ m ^ 3 covered pad oxide layer 204. The connector 'as shown in the figure: does not form a 1-pole oxide layer (Figure: a conventional way on the inter-electrode oxide layer Established the question 2 2 According to the 205, the road gate 22 was established. This company emulsified the stone layer at this time, in theory, the crossing gate pole 220 this special should be located in the deep trench capacitor 2 not removed nitrogen cut The layer of the plaque is changed to the "Layer 7" layer and the pad oxide layer 204 as the crossing gate 22: the edge structure 22 丨. The interpolar (10) ah ^ 203 and constitutes - memory cell (memGry, then the insulating structure 2 Guaranteed crossing gate 220 ij: lower helmet M, _, /, under the undivided trench capacitor 203 has good insulation to avoid short circuit from affecting the normal operation of dynamic random access memory. The foregoing process not only needs to use an additional mask to define the ❹ insulation, 'the position of the structure 221' but also the insulation structure 221, that is, the nitride layer 2 〇 5 scale oxide layer 204, a few misalignment deviation Definitely defined above the deep trench capacitor 203 is also a very difficult task. Also 'does not provide sufficient protection before the insulating structure 221 is completed' such that the exposed shallow trench isolation 202 and the deep trench capacitor 203 It is free from damage that may be caused by processes such as ion well planting, rinsing, and high temperature tempering. Therefore, there is an urgent need for a novel method of forming an insulating structure, which not only eliminates the need to use an additional mask to define the position of the insulating structure, but also eliminates the need to align with the existing deep trench capacitance when establishing the insulating structure. 'The substrate, shallow trench isolation and deep trench capacitance can be protected from exposure before the insulation structure is completed, so as to avoid possible damage and damage during the establishment of other areas. SUMMARY OF THE INVENTION The present invention thus provides a novel method of forming an insulating structure for a pass gate 'i.e., 'before removing a hard mask defining a deep trench opening, the crucible directly uses the trench (four) port as the first - The basis of the oxide layer and the first layer is the insulating structure in the future. Therefore, on the one hand, the cost of using an additional mask to define the position of the insulating structure is eliminated. On the other hand, the first oxide layer and the first layer can be accurately formed in the ice trench by means of self-alignment. In the above, the problem of alignment between the insulation structure and the divergence of the trench is automatically solved, which satisfactorily achieves the requirement that the insulation structure can accurately cover the capacitance of the deep trench. Also, before the completion of the insulation structure, the lining oxide layer, the © layer and the oxidized layer together cause the substrate, the shallow trench isolation and the deep trench to not come out. Therefore, it is also possible to protect the substrate, shallow trench isolation and deep trenches from possible damage during the establishment of other regions, and solve the above three problems at a time. The present invention provides a method of forming a self-aligned insulating structure that provides a substrate. The substrate contains a deep trench filled with a deep trench and a shallow trench isolation adjacent to the deep trench. The substrate is sequentially provided with a pad oxide layer and a hard mask. The lining oxide layer together with the hard mask defines the opening of the deep trench. Next, an oxidation step is performed to form a first oxide layer on the surface of the material, 200947514 wherein the first oxide layer serves as the desired insulating structure. The layer covers the first oxide layer. After the concealing, a pass gate is established on the insulating structure. The present invention further provides a semiconductor structure comprising a deep trench in a substrate filled with a stone, a light edge layer on the material surface (four), a first layer on the first oxide layer, a first layer, and a The shallow trenches adjacent to the deep trench are isolated. 〇Ο [Embodiment] The present invention provides a novel method for forming a self-aligned insulating structure of a pass gate, which eliminates the use of an additional mask to define the position of the insulating structure,卜的九. And solve the insulation structure and deep trench electric power:, before the completion of the insulation structure shallow trench isolation and deep virtual depth, "冓: electricity:: two: come out" can effectively protect the exposed diffuse trench isolation:; Cheng::: Amplitude-enhanced dynamic random access followed by the first-order 9. Shaoguan Lin invented the method of forming an insulating knot - a preferred embodiment. First, as shown in Fig. 9, the depth of the stone 311 is filled, and (10): the substrate 3G1. Substrate 3〇1 deep trench". Shallow trench isolation = 2 tantalum capacitor 'and the adjacent oxide layer 331 and the hard mask substrate (10) sequentially include the lining... substrate 3〇1 bis 2) One of the deep trenches 31° further comprises a composite material layer 312, 9 200947514, for example, a composite material layer composed of an oxide-nitride-oxide (ΟΝΟ), which is used as a capacitor dielectric layer. The deep trench 310 may also include other structures, such as a bottle bottom or a neck oxide layer. ------w... plus y ding group, such as 〇 〇 hard mask 332 may be nitrogen The compound, the nitrogen oxide, the carbide or a composite layer thereof is composed of, for example, nitrite, oxynitride, carbonized stone, etc. The oxide layer % contains the money. In the preferred embodiment of the present invention, shallow Trench isolation = formed before the deep trench 310. For example, first on the substrate 3〇, the trench isolation process defines shallow trench isolation 32〇. Narrow =: and _steps are patterned The hard mask says that the monolithic oxide layer 331 and several trenches: the ice trench 310, making the deep trench 31 〇 ❿ ❿ After the formation of the deep trench 3K), the groove can be separated into a bottle shape and other parts of the deep ditch capacitor bottom material, such as a shackle, can be built to complete the deep oxide layer, and then backfilling is familiar. Related art and the production of the conventional channel 310. So far, it is worth noting that, from etching 2 = well-known, do not remove the hard canal 310 until the deep trench is completed. Since _ 3, ° 332 located on the substrate 301 has the intention of defining the deep trench smear layer 331 and the hard mask leaving the hard mask 332, it is omitted from the opening 314. Therefore, the purpose of the present invention is That is, the deep trench can be directly used to reach the self-aligned opening 314 to define the position of the insulating structure for the opening of the 200947514. It is owed, as shown in Fig. οο, if the deep trench 31〇 When the composite layer 312 has been formed, the exposed composite layer 312 is removed first. For example, if the composite layer 312 is composed of an oxide-nitride oxide, the conditions of the hot phosphoric acid can be used to remove the composite. Material layer Referring to FIG. u, an oxidation step is performed to oxidize the surface of the deep trench 310 to form a first oxide layer 315. These first A layer 315 is to be used as a partial insulating structure. Oxidation to form the first oxide layer 315, for example, using a dry thermal oxidation process or a wet thermal oxidation process to form the first oxide layer 315. Preferably, the first oxide layer 315 is protected with an adjacent pad oxide layer 331 The material 3〇1, the deep trench 310 is isolated from the shallow trenches 32. Then, a layer of germanium 34 is formed in the opening 314 to cover the first oxide layer 315. The sap layer 340 may be amorphous or stellite formed by chemical vapor deposition or a combination thereof. The method of forming the glazed layer 34 可以 may be such that, as shown in Fig. 12, for example, a chemical vapor deposition method is used to make a comprehensive conformal coating of the ruthenium layer 315 and the hard mask 332. Then, as shown in Fig. 13, the excess layer 340' is removed by a planarization process using chemical mechanical polishing or the like so that the first layer 341 covers the first oxide layer and a portion of the hard mask 332. Preferably, after the chemical mechanical polishing, the first layer 341 is formed on the first oxide layer 315 to form an asymmetrical U-shaped structure from a side view. The thickness of the first layer 341 may be between % angstroms (Astroms - 40) A. 200947514
Ο 由於本發明方法是保留定義溝渠310的硬遮罩332， 並直接使用溝渠31〇的開口 314來建立第一氧化層315與 第一矽層341’並作為日後所需用於過路閘極的絕緣結構'， 所以方面省卻了再使用—額外光罩來定義絕緣結構位置 的步驟，另一方面在矽311的誘導下，第一氧化層315又 能以自對準的方式精確地形成在溝渠31〇之上，自動的解 决了後續的絕緣結構與先前深溝渠電容間對準的問題，完 美的達成了絕緣結構需能準確覆蓋溝渠電容的要求。 冉來，如第14圖所示 .…叫"丨，丨 π丨本％処早。如果硬遮 罩332係由氮化物所組成，可以使用熱磷酸來移除硬遮罩 M2。於是留下襯墊氧化層331位在基材3〇1上，第一矽層 341與第一氧化層315位在深溝渠31〇上。 曰 从在移除硬料332之後，可以視產品製程之需要，進 :二材，上其他邏輯元件區域的修飾與程序，例如高溫 潔、離子井佈植或退火等步驟。由於塾氧化層331 ==材3〇1上’而且第1層341與第一氧化層315 深溝=Γ〇上，因此不但可以分別使得基材撕、 保频材〇 #顧離32G不會暴露出來，還可以有效 千蔓基材301、深溝渠31〇與淺溝槽 他區域在修飾過程中可能的波及 又至- 是’第1層341在其他區域的修=:值得注意的' 洗製程後，可能會因為波及與傷：井區退火或>月 縮小並氧化。 而有相當程度的犧牲而 12 200947514 跟著，如第15圖所示，移除基材3〇〗表面原先的襯 墊乳化層331，而暴露基材301。移除襯墊氧化層mi的方 法可以使用含氟的蝕刻劑，例如氟化氫或是氧化物蝕刻緩 衝液(BOE’Buffer oxidation etchant)等等，來移除襯墊氧化 層331。在移除襯墊氧化層331同時亦會移除部分之已被 氧化的第一矽層341及第一氧化層315，於是，第—矽層 341及第一氧化層315縮小。 ❹ 繼續，如第16圖所示，進行至少一高溫氧化製程， 在暴露的基材301上形成另一層品質較佳之氧化物3幻， 用以製備所需之閘極介電層，以及一併將第一矽層34ι轉 化為第二氧化層316，而成為絕緣結構317的—部份。由 於在基材301上的其他邏輯元件區域（圖未示）或靜電保 護元件區（圖未示）也需要閘極介電層，例如，使用多^ 熱氧化步驟與多次局部移除步驟來於不同的區域中分別二 〇成厚度不同的氧化物層’於是在基材3〇1上的其他二輯二 域或靜電保護元件區在形成厚度不同的氧化物時，當作 制冰溝渠電容之閘極的閘極介電層之氧化物333就伴: 等熱氧化步驟或最後再形成在基材3〇1上，而第一石夕層^ 則一併轉化為第二氧化層316，並與先前的第一氧化層= 完全合併而成為絕緣結構317的—部份。在考慮9 5 對第-石夕層產生氧化作用、會移除已被氧化之石夕層 步驟後，可事先預估第1層341的厚度，俾使第一石夕: 341在形成閘極之前可以完全轉化為第二氧化層316，或^ 13 200947514 僅有部分的第一石夕層341轉化為第二氧化層3i6，而留下 了 I5刀的第一矽層341。若第—矽層341太厚，則在形成 閑極之則’會有大部分的第—石夕層未被轉化成第二氧化層 316而造成後續餘刻的負擔；若第一碎層341太薄，則第 -石夕層會太早被完全轉化為第二氧化層316而無法保護下 方㈣1化層315。苐16圖中即例示第—㈣完全轉化 為弟二氧化層的情況。 ❹ 接著，要在基材301上建立閘極/字元線，並安排字 元線從淺溝槽隔_ 32〇的上方路過相鄰的深溝$ 31〇。可 以使用習知的方法來建立閘極/字元線。如第17圖所示， 各別字元線350A、350B、35〇C、350D就從基材3〇1、深 溝渠310上方通過。一方面，部分的字元線35〇a/35〇d即 成為建立在閘極氧化物333上的閘極351/354，並分別控制 相對應之深溝渠電容31〇(即過路閘極352、353下方的深溝 ◎ 渠電容310)。另一方面，從深溝渠31〇上方路過的字元線 35GB、350C ’即成為建立在絕緣結構317上所謂的的過路 閘極352、353。由於絕緣結構317夾在深溝渠31〇、過路 閘極352、353之間，加上絕緣結構317至少由第一氧化層 315與第二氧化層316所組成，於是成為深溝渠31〇與過 路閘極352、353之間的優良絕緣結構。 於是本發明又提供一種半導體結構4〇〇。如第18圖 所示’半導體結構400包含基材401、深溝渠41〇、第一氧 化層420、第一石夕層430、閘極440以及淺溝槽隔離45〇。 14 200947514 深溝渠410位於基材401中’並填滿石夕411。位於石夕411 表面的第一氧化層420,即作為此絕緣之用。第一矽層430 位於第一氧化層420之上。另外，閘極440位於第—石夕層 430之上。淺溝槽隔離450則鄰接深溝渠410。形成半導體 結構400之方式可以如前所述，故不再重複。 由於本發明方法是故意保留定義深溝渠開口的硬遮 罩，並在移除定義深溝渠的硬遮罩前，就直接使用深溝渠 Ο ❹ 的開口作為建立第一氧化層與第一石夕層的依據，而成為曰 後絕緣結構。所以，一方面省卻了使用額外的光罩來定義 絕緣結構位置的代價，另一方面，第一氧化層與第一砍層 又能以自對準的方式精確地形成在深溝渠之上，自動地解 決了絕緣結構與深溝渠電容間、絕緣結構與主動區域間的 對準問題’完美地達成了絕緣結構鮮確覆蓋深溝渠電容 的要求。還有，在絕緣結構完成前，硬遮罩、襯墊氧化層、 第-石夕層與第-氧化層奸使得基材、淺溝_離與深曰溝 渠不會暴露出來’所以還能夠保護基材、淺溝槽隔離與深 溝渠不會受到其他區域的修询過程中可能的傷害。 以上所述僅為本發明之較佳實施例，凡依本 圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍 轨 【圖式簡單說明】 方路過未被其 第1圖例不字兀線從灸溝槽隔離的上 15 200947514 控制的深溝渠電容。 第2-8圖即例示傳統上定義過路閘極之絕緣結構之 步驟。 第9-17圖例示本發明形成絕緣結構方法之一較佳實 施例。 第18圖例示本發明半導體結構之一較佳實施例。 【主要元件符號說明】 301基材 310深溝渠 311矽 312複合材料層 314 開口 315第一氧化層 316第二氧化層 317絕緣結構 320淺溝槽隔離 331概塾氧化層 332硬遮罩 333閘極氧化物 340矽層 341第一砍層 350A、350B、350C、 350D字元線 351/354 閘極 352、353過路閘極 400半導體結構 16Ο Since the method of the present invention retains the hard mask 332 defining the trench 310, and directly uses the opening 314 of the trench 31〇 to establish the first oxide layer 315 and the first germanium layer 341' and serve as a pass gate for future use. The insulating structure' eliminates the need to reuse the additional mask to define the position of the insulating structure. On the other hand, under the induction of the crucible 311, the first oxide layer 315 can be accurately formed in the trench in a self-aligned manner. Above 31〇, the problem of the alignment between the subsequent insulation structure and the previous deep trench capacitance is automatically solved, and the requirement that the insulation structure needs to accurately cover the trench capacitance is perfectly achieved. Later, as shown in Figure 14 .... called "丨,丨 π丨%% early. If the hard mask 332 is composed of nitride, hot phosphoric acid can be used to remove the hard mask M2. Thus, the pad oxide layer 331 is left on the substrate 3〇1, and the first buffer layer 341 and the first oxide layer 315 are located on the deep trench 31〇.曰 After removing the hard material 332, you can follow the steps of the product process: the two materials, the modification and procedures of other logic component areas, such as high temperature cleaning, ion well implantation or annealing. Since the tantalum oxide layer 331 == material 3〇1 on the upper layer 341 and the first oxide layer 315 deep groove = Γ〇, it can not only make the substrate tear, the frequency protection material 顾 #顾从32G will not be exposed Come out, it can also be effective for thousands of basal substrates 301, deep trenches 31 〇 and shallow trenches in the region of the modification process may be affected again and again - is the first layer 341 repair in other areas =: notable 'washing process After that, it may be due to damage and injury: well area annealing or > month shrinking and oxidation. There is a considerable degree of sacrifice. 12 200947514 Subsequently, as shown in Fig. 15, the substrate lining emulsion layer 331 is removed from the substrate, and the substrate 301 is exposed. The method of removing the pad oxide layer mi may use a fluorine-containing etchant such as hydrogen fluoride or a BOE'Buffer Oxide etchant or the like to remove the pad oxide layer 331. When the pad oxide layer 331 is removed, a portion of the first ruthenium layer 341 and the first oxide layer 315 which have been oxidized are also removed, and the first ruthenium layer 341 and the first oxide layer 315 are shrunk. ❹ Continuing, as shown in FIG. 16, performing at least one high temperature oxidation process to form another layer of a better quality oxide 3 on the exposed substrate 301 for preparing the desired gate dielectric layer, and The first layer 34d is converted into a second oxide layer 316 to become a portion of the insulating structure 317. A gate dielectric layer is also required due to other logic element regions (not shown) or electrostatic protection device regions (not shown) on the substrate 301, for example, using multiple thermal oxidation steps and multiple partial removal steps. In the different regions, respectively, the oxide layers of different thicknesses are formed. Then, the other two-stage or two-domain or electrostatic protection element regions on the substrate 3〇1 are used as ice-making trench capacitors when forming oxides having different thicknesses. The oxide 333 of the gate dielectric layer of the gate is accompanied by: an isothermal oxidation step or finally formed on the substrate 3〇1, and the first layer is converted into the second oxide layer 316, And completely merged with the previous first oxide layer = to become part of the insulating structure 317. After considering the oxidation of the osmotic layer on the ninth layer, the step of removing the oxidized slab layer may be performed, and the thickness of the first layer 341 may be estimated in advance, so that the first eve: 341 is formed in the gate It can be completely converted to the second oxide layer 316 before, or ^ 13 200947514 Only a portion of the first layer 341 is converted into the second oxide layer 3i6, leaving the first layer 341 of the I5 knife. If the first layer 341 is too thick, then in the formation of the idle pole, there will be a majority of the first layer - the layer is not converted into the second oxide layer 316, causing the burden of subsequent engraving; if the first layer 341 If it is too thin, the first layer will be completely converted into the second oxide layer 316 too early to protect the lower (four) layer 315. In the figure 苐16, the case where the (-)th is completely converted into the younger dioxide layer is exemplified. ❹ Next, a gate/character line is created on the substrate 301, and the word line is arranged to pass the adjacent deep trench $31〇 from above the shallow trench _32〇. A conventional method can be used to create a gate/word line. As shown in Fig. 17, the respective word lines 350A, 350B, 35A, and 350D pass over the substrate 3'1 and the deep trench 310. On the one hand, part of the word line 35 〇 a / 35 〇 d becomes the gate 351 / 354 built on the gate oxide 333, and respectively controls the corresponding deep trench capacitor 31 〇 (ie, the crossing gate 352, Deep groove below 353 ◎ channel capacitor 310). On the other hand, the word lines 35GB and 350C' which pass over the deep trench 31 are formed as the so-called crossing gates 352 and 353 which are formed on the insulating structure 317. Since the insulating structure 317 is sandwiched between the deep trench 31〇 and the crossing gates 352 and 353, and the insulating structure 317 is composed of at least the first oxide layer 315 and the second oxide layer 316, it becomes a deep trench 31〇 and a crossing gate. Excellent insulation between poles 352 and 353. The invention then provides a semiconductor structure 4A. As shown in Fig. 18, the semiconductor structure 400 includes a substrate 401, a deep trench 41, a first oxide layer 420, a first layer 430, a gate 440, and a shallow trench isolation 45. 14 200947514 The deep trench 410 is located in the substrate 401' and fills the stone 411. The first oxide layer 420 located on the surface of the stone 411 is used for this insulation. The first germanium layer 430 is over the first oxide layer 420. In addition, the gate 440 is located above the first layer 430. The shallow trench isolation 450 is adjacent to the deep trench 410. The manner in which the semiconductor structure 400 is formed can be as described above and will not be repeated. Since the method of the present invention deliberately retains the hard mask defining the opening of the deep trench, and directly removes the hard mask defining the deep trench, the opening of the deep trench is directly used as the first oxide layer and the first layer Based on the basis of the insulation structure. Therefore, on the one hand, the cost of using an additional mask to define the position of the insulating structure is eliminated. On the other hand, the first oxide layer and the first layer can be accurately formed on the deep trench in a self-aligned manner, automatically The solution solves the problem of the alignment between the insulation structure and the deep trench capacitor, the insulation structure and the active region. The perfect requirement for the insulation structure to cover the deep trench capacitor is achieved. Also, before the completion of the insulation structure, the hard mask, the pad oxide layer, the first-slip layer and the first-oxidized layer make the substrate, the shallow trench_deep and the deep trench not exposed, so it can also protect Substrate, shallow trench isolation and deep trenches are not subject to possible damage during repairs in other areas. The above description is only the preferred embodiment of the present invention, and all the equivalent changes and modifications made according to the present invention should belong to the scope of the present invention. [Simple description of the drawing] The path is not the first picture. The squall line is isolated from the moxibustion trenches on the upper 15 200947514 controlled deep trench capacitors. Figures 2-8 illustrate the steps conventionally defining the insulating structure of the pass gate. Figures 9-17 illustrate a preferred embodiment of the method of forming an insulating structure of the present invention. Figure 18 illustrates a preferred embodiment of the semiconductor structure of the present invention. [Main component symbol description] 301 substrate 310 deep trench 311矽312 composite material layer 314 opening 315 first oxide layer 316 second oxide layer 317 insulating structure 320 shallow trench isolation 331 general oxide layer 332 hard mask 333 gate Oxide 340 layer 341 first chopped layer 350A, 350B, 350C, 350D word line 351/354 gate 352, 353 pass gate 400 semiconductor structure 16