TW200945521A - Method for forming solder balls on a surface of a semiconductor component - Google Patents

Method for forming solder balls on a surface of a semiconductor component Download PDF

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Publication number
TW200945521A
TW200945521A TW97115102A TW97115102A TW200945521A TW 200945521 A TW200945521 A TW 200945521A TW 97115102 A TW97115102 A TW 97115102A TW 97115102 A TW97115102 A TW 97115102A TW 200945521 A TW200945521 A TW 200945521A
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Taiwan
Prior art keywords
ball
solder
flux
solder paste
forming
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TW97115102A
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Chinese (zh)
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TWI371840B (en
Inventor
Chien-Hung Chen
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Powertech Technology Inc
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Priority to TW097115102A priority Critical patent/TWI371840B/en
Publication of TW200945521A publication Critical patent/TW200945521A/en
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Publication of TWI371840B publication Critical patent/TWI371840B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

Disclosed is a method for forming solder balls on a surface of a semiconductor component. A layer of flux is formed on metal pads of the semiconductor component. What is next is a stencil printing step to apply solder paste on the flux, where the utilized stencil has a groove and a plurality of through holes connected to the groove for filling solder paste. The groove has a depth greater than the layer thickness of the flux so that the stencil is not pressed to and not in contact with the flux. Then, the solder paster is reflowed to form a plurality of solder balls bonded to the metal pads. This method can eliminate void issue at bottom of solder balls by conventional method to directly printing solder paste on metal pads, also can save cleaning of the stencil or change frequency.

Description

200945521 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種丰连機 裡+導體裝i的製造技術 係有關於一種在半導體元件表 竹⑺ 1卞衣由形成銲球之方法。 【先前技術】 新一代的半導體封裝盘组鞋杜〜 展〃組裝技術是以球栅陣列 (BGA，ball grid array paek )、日200945521 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a manufacturing technique of a +conductor in a Fenglian machine. A method for forming a solder ball in a semiconductor component is described. [Prior Art] A new generation of semiconductor packaged disc shoes ~ 〃 assembly technology is based on ball grid array (BGA, ball grid array paek), day

g)日日片尺寸封裝（CSP chip size/scale package)及霜曰. ’g) CSP chip size/scale package and frost 曰. ’

)覆日日（fhP-chip)封裝技術為 主流。皆是在一半導體元件之 佝為 σ表面设置複數個銲 球（MW)，利用銲球做為與外部電路板連接之介 面。而已知銲球的形成技術以植球為±，先利用一丨 盤或對位板將等球徑的自由銲球放置於半導體元2 上，經回焊使其固著接合至半導 卞守體7L件之金屬墊。 種低成本的銲球形成方法是採用模板印刷將錫膏 paste)直接塗施在半導體元件之金屬塾 回焊’使錫膏形成銲球，但長期以來存在著製 問題。在填入錫膏到模板之通孔時 叮4易在錫膏底部殘 留氣洞（void) ’此氣洞被錫膏覆蓋後， ^ +易排出，俟銲 球形成之後亦存在於銲球底部，影響 竦的接合強度 與尺寸。 習知利用模板印刷方式在半導體元件形成銲球之方 法可見於如第1A至1E圖所示的元件截面示意圖。如 第1A圖所示，一半導體元件n〇係具—人 111以及複數個位於該接合表面111之金屬 i 1 2。該 5 200945521 半導體元件1 1 〇係為晶片已封裝狀態，主要包含一 片113、一基板114以及一封膠體115。該晶片 以複數個銲線116電性連接至該基板114，再以該 膠體115¾、封該晶片113與該些焊線116，但顧母 一 ί^露出 些金屬墊1 1 2，以供設置銲球。在習知的模板 I刷 程中，如第1Β圖所不’該半導體元件11〇放置於 台120上，並提供一模板（stencil)140於該半導體_ 110上，該模板140位於該些金屬墊U2位置 上係 〇 成有複數個通孔143，並具有一刮印平面141。 0锡 160形成於該模板140之該刮印平面141上，# 並以 刮刀（squeegee)150自該模板140之該刮印平面 錫膏160填滿該些通孔143。之後，如第i c圖所示 移開該模板140，以使錫膏160直接形成於該半導 元件110之該些金屬墊112上。由於錫膏16〇為點 態，在錫膏160與該些金屬墊112之間容易產生積 殘留空氣的空隙。之後，進行一回焊步驟，如第 ❹. 圖所示，加熱錫膏160使其溶融，冷卻後即會在兮 導體元件110之該些金屬塾112上形成複數個銲 1 6 1 (如第1 E圖所示）’而構成一球柵陣列封裝。 然而，在習知印錫膏並回焊以形成銲球的過程中 在錫膏160與該些金屬墊112之間的空隙係積存殘 空氣，空氣被錫膏160覆蓋後’不易在回焊中被排注 俟錫膏160冷卻後’即會在該些銲球161底部形成 洞162(如第2圖所示）’氣洞162中的氣體存在可能 晶 係 封 該 過 載 件 形 膏 將 ϊ 體 铜 存 1D 半 球 留 氣 會 200945521 在熱循環過種 該些具有氣祠 錫連接（solder 1 6 1的尺寸。 中產生收縮和膨脹的應力 162之銲球161產生裂痕 joint)之品質及可靠性， 集中點，而使 ’而影響了銲 也會改變銲球 【發明内容】 ❹ 的係在於提供一種在半 能消除習知由模板印刷 位在接合底部的氣洞 有鑒於此，本發明之主要目 導體元件表面形成銲球之方法， 與回焊方法形成之銲球會產生 (void)問題。The day-to-day (fhP-chip) packaging technology is the mainstream. A plurality of solder balls (MW) are disposed on a σ surface of a semiconductor device, and the solder balls are used as a interface to an external circuit board. However, it is known that the formation technique of the solder ball is based on the ball placement. First, a ball-free free solder ball is placed on the semiconductor element 2 by a disk or a counter plate, and the bonded ball is fixedly bonded to the semi-conductive body 7L by reflow soldering. Metal pad for pieces. A low-cost solder ball forming method is to apply a solder paste directly to a metal element of a semiconductor element by stencil printing, so that the solder paste forms a solder ball, but there has been a problem for a long time. When filling the solder paste into the through hole of the template, 叮4 is easy to leave a void at the bottom of the solder paste. 'This hole is covered by solder paste, ^ + is easy to discharge, and the solder ball is also formed at the bottom of the solder ball after it is formed. , affecting the joint strength and size of the crucible. A method of forming a solder ball on a semiconductor element by a stencil printing method can be found in a cross-sectional view of an element as shown in Figs. 1A to 1E. As shown in Fig. 1A, a semiconductor element n-clamps - a person 111 and a plurality of metals i 1 2 located on the bonding surface 111. The 5 200945521 semiconductor device 11 is a wafer packaged state, and mainly includes a chip 113, a substrate 114, and a gel 115. The wafer is electrically connected to the substrate 114 by a plurality of bonding wires 116, and the wafer 113 and the bonding wires 116 are sealed by the colloid 1153, but the metal pads 1 1 2 are exposed for setting. Solder balls. In the conventional template I brushing process, the semiconductor device 11 is placed on the stage 120 as shown in FIG. 1 and a stencil 140 is provided on the semiconductor 110, and the template 140 is located on the metal. The pad U2 is pivotally formed with a plurality of through holes 143 and has a squeegeing plane 141. The tin 160 is formed on the squeegee plane 141 of the stencil 140, and the through holes 143 are filled from the squeegee solder paste 160 of the stencil 140 by a squeegee 150. Thereafter, the template 140 is removed as shown in Fig. 2c, so that the solder paste 160 is directly formed on the metal pads 112 of the semiconductor element 110. Since the solder paste 16 is in a dot state, a gap in which residual air is accumulated between the solder paste 160 and the metal pads 112 is likely to occur. Thereafter, a reflow step is performed, as shown in Fig. ,. The solder paste 160 is heated to melt, and after cooling, a plurality of solders 1 6 1 are formed on the metal crucibles 112 of the germanium conductor element 110 (e.g. 1 E shows) 'and constitutes a ball grid array package. However, in the process of solder paste soldering and reflow soldering to form solder balls, residual air is accumulated in the gap between the solder paste 160 and the metal pads 112, and the air is covered by the solder paste 160, which is difficult to reflow. After the solder paste 160 is cooled, a hole 162 is formed at the bottom of the solder balls 161 (as shown in FIG. 2). The gas in the gas hole 162 may be crystal-sealed. The overloaded paste will be in the form of a body. Copper storage 1D hemisphere gas retention 200945521 The quality and reliability of these solder balls 161 with a gas-tin-tin connection (the size of the solder 161 in which the shrinkage and expansion is generated) is generated in the thermal cycle. Concentrating the point, and causing the welding to change the solder ball. [Inventive content] The system is to provide a gas hole that can be removed from the bottom of the joint by the stencil printing in the light of the above. A method of forming a solder ball on the surface of a conductor element, and a solder ball formed by the reflow method may cause a void problem.

本發明的目的及解決其技術問題是採用以下技術方 案來實現的。依據本發明所揭示之一種在半導體元件表 面形成銲球之方法’首先’提供一半導體元件，其係具 有在一表面之複數個金屬塾。接著，形成一層助銲劑於 該些金屬墊上。之後，以模板印刷方式形成錫膏於該助 銲劑上’所使用之模板係具有一刮印平面，並在該刮印 平面之另一相對表面形成有一凹槽，該模板係另具有複 數個可供錫膏填入之通孔，其係連通該刮印平面至該凹 槽’其中該凹槽之深度係大於該助銲劑之厚度，以使該 模板不壓觸至該助錄劑。最後’回焊該錫膏，以形成為 複數個接合於該些金屬墊上的銲球。 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。 在前述之半導體封裝構造中’該錫膏係可不包含助 銲劑。 7 200945521 在前述之半導體封裝構造中，回焊步驟係可為〆連 續昇溫過程’先到達該助銲劑之彿點，以移除該助銲劑 並帶出該錫膏底部之氣體，再使該锡膏熔化以内聚成 球。 在前述之半導體封裝構造中’目帛步驟之昇溫曲線 係可為階梯狀’第—階段是約維持在該助銲劑之彿點， 第二階段是約維持在該些銲球的熔點。 I前述之半導體封裝構造中，㉟些輝球係彳具有大 P 致共平面的對外接觸點。 在前述之半導體封裝構造中，當該半導體元件之該 表面係可為凸弧面時，該些銲球中周邊銲球的球徑係大 於中央鲜球的球後。 在前述之半導體封裝構造中，當該半導體元件之該 表面係可為凹弧面時，該些銲球中周邊銲球的球徑係小 於中央銲球的球徑。 〇 在刖述之半導體封裝構造中，該半導體元件之該表 面係可形成於一基板條之一單元區内，而該模板之該四 槽係具有稍小於該單元區但覆蓋該些金屬墊之覆蓋 區域。 在前述之半導體封裝構造中，該半導體元件係可選 自；球柵陣列封裝構造（BGA package)、一覆晶封裝 構造（fhp chip package)與一半導體晶圓之其中之—。 在前述之半導體封裝構造中，該些通孔在朝向該 之開口周緣係可形成有一銳角邊緣。 8 200945521 在前述之半導體封裝構造中，該模板在形成有該凹槽 之表面係可形成有一或更多的排氣槽孔，其係連通到該凹 槽。 ^ 在前述之半導體封裝構造中，該助銲劑的圖案形狀係 可對應於該些金屬墊。 由以上技術方案可以看出，本發明之在半導體元件 表面形成銲球之方法，有以下優點與功效： 、藉由凹槽模板印刷方式能使錫膏形成於已在金屬墊 上的助銲劑上，相對於習知以模板印刷將錫膏直接 形成於半導體元件的金屬墊上，能夠消除回焊後形 成之銲球產生位在接合底部的氣洞（v〇id)問題。 一、即使半導體元件的接合表面有翹曲或扭曲等非平面 現象，塗施的錫膏用量能自動調整，能進行微調以 使由錫膏回焊形成之銲球具有大致共平面的對外 接觸點，藉以解決表面接合時銲球的空焊或假焊 象。 —藉由模板之凹槽設計，使模板不與助銲劑直接接 觸，能增加模板印刷次數，減少模板清潔或更換頻 率〇 四藉由模板之凹槽縮短模板的通孔深度，藉以減少通 孔與錫膏的沾黏面積，有助於錫膏受重力垂落故 能符合微小銲球間距的要求，達成高密度之銲球佈 置及有助於半導體元件微小化之發展。 五由於銲球底部的氣洞消除，可以提高球栅陣列元件 200945521 焊接的強度與效果。 六、利用模板的通孔在朝向凹槽之開口周緣可形成有一 銳角邊緣，故模板能限制錫膏填充到模板之通孔時 往模板凹槽的側向溢流。 【實施方式】 依據本發明之一種在半導體元件表面形成銲球之方 法’第—具體實施例圖例說明於第3A至3F圖的元件 截面示意圖。 首先，如第3A圖所示，提供一半導體元件210。在 本實施例中，該半導體元件2 1 0係為尚未設置銲球之球 柵陣列封裝構造（BGA package, Ball Grid Array package)，主要包含一晶片213、一基板214以及一封 膠體2 1 5。該晶片2 1 3係以複數個銲線2 1 6電性連接至 該基板214之導電線路（圖未繪出），再以該封膠體215 密封該晶片213與該些銲線216’提供適當的封裝保護 以防止電性短路與塵埃污染。通常該基板2 1 4係包含至 少一絕緣層與至少一線路層，其中該絕緣層係為玻璃纖 維布含浸樹脂、雙馬來醯亞胺三嗓樹脂（BT resin， bismaleimide triazine resin)或 FR-4 環氧樹脂。該半導 體元件210係具有一接合表面211，作為對外表面接 合，即該基板214外露於該封膠體215之—表面。在該 接合表面211上係設有複數個金屬塑* 212，以供設置銲 球。 之後，如第3B圖所示’將該半導體元件210放置並 10 200945521 固定於一載台220上，並可形成一層助銲劑230於該接 合表面211之該些金屬墊212上。其中該助銲劑230的 圖案形狀是對應於該些金屬墊212，以稍大於該些金屬 墊212為較佳。而該助銲劑230的形成方法是可利用網 板印刷（screen printing)技術。而該助知劑230之厚度係 約為30〜300 β m。目前常使用的助銲劑230是以松脂 (rosin)與稀釋劑混合物為主要成分。在元件銲接過程 中，該助銲劑230的功能為清潔該些金屬墊212的表面 Φ 與加強銲接能力，可清除銲接金屬表面的氧化物、油 脂、及其他會妨礙連接的物質，降低熔融銲錫與金屬墊 之間的表面張力以提高潤濕性、提供適當的腐#性、發 泡性（foaming)、揮發性與黏滯性，可加強銲接效果並有 利於銲接的進行。 接著，如第3C圖所示，提供一模板240於該半導體 元件210上，並以模板印刷（stencii printing)方式形成 錫膏260於該助銲劑230上。具體而言，如第3C圖及 第5圖所示’在本實施例中所使用之模板240係具有一 刮印平面241及一壓合面244，並該壓合面244係為在 該刮印平面241之一相對表面並形成有一凹槽242。該 模板240係另具有複數個可供錫膏260填入之通孔 243 ’其係連通該刮印平面241至該凹槽242，其中該 凹槽2 42之深度係大於該助銲劑230之厚度，以使該模 板240不壓觸至該助銲劑230，進而可增加該模板240 13刷欠數，減少該模板240清潔或/與更換頻率。此外， 11 .200945521 ' 利用該凹槽242 ’在模板印刷時該模板240不會擠壓該 助銲劑230，故在對應金屬墊212上的助銲劑230不會 擴散連接’能達成利用模板印刷達成錫膏260形成在該 助銲劑230上的技術手段。而連通該凹槽242之該些通 孔2 43如同點膠針頭般提供錫膏260更能整面形成，故 錫膏260的塗施量可以獲得控制並能高效率形成。 模板印刷過程如第3C及3D圖所示，可藉由一刮刀 25〇自該模板240之該刮印平面241填入錫膏260至該 ® 些通孔243内，以使錫膏260形成於該助銲劑230上。 較佳地，錫膏260係可不包含或僅含少量的助銲劑，使 得錫膏260内的金屬顆粒為微小空隙的密實排列，以便 於控制銲球内部不會產生氣洞。 詳細而言’如第5圖所示，該模板24 0在該壓合面 244係可具有複數個排氣槽孔245，可有利於該模板24〇 在填入錫膏260時空氣之導出。此外，由於習知之錫膏 ⑩ 及印刷模板之特性有所謂1比1 · 5之比例限制，亦即模 板的通孔直徑必須大於模板的厚度（即通孔深度）達1 5 倍以上’否則將易造成錫膏阻塞於模板之通孔中，而無 法印刷於金屬墊上。而本發明之模板240係具有一凹槽 2 42 ’在不影響模板的支撐強度下減少該些通孔243之 深度，藉以減少該些通孔243與錫膏260的沾黏面積， 有助於錫膏260受重力垂落，故該些通孔243之直徑可 有效縮小並可縮小間距，形成較小之銲球間距，達成高 密度之銲球佈置及有助於半導體元件微小化之發展。 12 200945521 之後’如第3E圖所示，、金> 所 進仃一回焊步驟，將印上錫 膏260之該半導體元件21〇 〇移至一回焊爐（refl〇w 〇ven) 内，然後經由回焊製程回焊媒者 坪錫膏260，以形成為複數個 接合於該些金屬墊212上的銲碰 幻銲球261(如第3F圖所示）。 在回焊時，在錫膏260下方站兮 的忒助銲劑230在揮發時一 併帶出錫膏260底部之氣體 札體，促進錫膏260的熔化以内 聚成球。因此，如第4圖所示，各丨由士政 固^不’利用本發明的上述方法 回焊出之該些銲球261不會在在加f * ❹ ❿ f在底部形成氣洞，能消除習 知直接印刷錫膏在金屬墊 35它上會產生位在銲球底部的氣 洞（void)問題。具體而言，回 ^ ^ θ 知步驟係可為一連續昇溫 過程’先到達該助銲劑230之捆鉻躭以教人 > 上扣 <揮發點U移除該助銲劑 230，再到達該錫膏26〇的燒妹々机 晃結熔點，以使錫奮260熔 化以内聚成球。 較佳地’如第6圖所示， Q焊步驟之昇溫曲線係可 為階梯狀’第一階段是約維持 F付在该助知劑230之揮發 點，由於該助悍劑23 0的主要出A 4 J 土要成分為松香與稀釋劑混合 物。一般稀釋劑混合物的彿點 約介於攝氏125 至250 °C之間。而松香則會在攝氏7。 0 獬K 70 C至1〇〇 C甚至120。(：開 始軟化並流動至待接合的焊接 吁钱表面上。回焊過程中，該 助焊劑2 3 0中之稀釋劑混人私t 1 t 砰削浞σ物會不斷的從錫膏260中揮 發出來，由於該助焊劑230係 丨尔形成在鍚骨260之下，將 有助於將錫膏260底部之空氣由 馇_ 工乳排出。第一階段是約維持 在該些銲球261的炫點，通縈β人从媒Λ 。 通I疋介於攝氏185。(：至400 °C ’以使錫膏260熔化而内聚成球。 13 200945521 此外，本發明之該半導體元件210除了可以是一球 柵陣列封裝構造（BGA package)，或可選自於一覆晶封 裝構造（flip chip package)與一半導體晶圓之其中之 φThe object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. A method of forming solder balls on the surface of a semiconductor device according to the present invention 'first' provides a semiconductor device having a plurality of metal turns on a surface. Next, a layer of flux is formed on the metal pads. Thereafter, the template used to form the solder paste on the flux by stencil printing has a squeegee plane, and a groove is formed on the other opposite surface of the squeegee plane, and the template has a plurality of A through hole filled with a solder paste, which communicates the squeegee plane to the groove ′ wherein the depth of the groove is greater than the thickness of the flux so that the template does not press against the Assisting Agent. Finally, the solder paste is re-polished to form a plurality of solder balls bonded to the metal pads. The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. In the foregoing semiconductor package construction, the solder paste may not contain a flux. 7 200945521 In the foregoing semiconductor package construction, the reflow step may be a continuous heating process 'first reaching the flux point of the flux to remove the flux and bring out the gas at the bottom of the solder paste, and then make the tin The paste melts to condense into a ball. In the above-described semiconductor package structure, the temperature rise curve of the step of the step can be stepped. The first stage is maintained at about the point of the flux, and the second stage is maintained at about the melting point of the solder balls. In the aforementioned semiconductor package structure, 35 of the glow ball systems have large P-coplanar external contact points. In the above semiconductor package structure, when the surface of the semiconductor element is a convex arc surface, the ball diameter of the peripheral solder balls in the solder balls is larger than the ball of the center fresh ball. In the above semiconductor package structure, when the surface of the semiconductor element is a concave curved surface, the spherical diameter of the peripheral solder balls in the solder balls is smaller than the spherical diameter of the center solder balls. In the semiconductor package structure described above, the surface of the semiconductor component can be formed in a cell region of a substrate strip, and the four trenches of the template have a slightly smaller than the cell region but cover the metal pads. Coverage area. In the foregoing semiconductor package structure, the semiconductor component is optional; a ball grid array package structure (BGA package), a flip chip package (fhp chip package), and a semiconductor wafer. In the foregoing semiconductor package construction, the through holes may have an acute-angled edge formed toward the periphery of the opening. 8 200945521 In the foregoing semiconductor package construction, the template may have one or more vent holes formed in the surface on which the groove is formed, which is connected to the groove. ^ In the foregoing semiconductor package construction, the pattern shape of the flux may correspond to the metal pads. It can be seen from the above technical solution that the method for forming a solder ball on the surface of a semiconductor component of the present invention has the following advantages and effects: The solder paste can be formed on the flux on the metal pad by the stencil printing method. Compared with the conventional method of forming a solder paste directly on a metal pad of a semiconductor element by stencil printing, it is possible to eliminate the problem of a gas hole (v〇id) at the bottom of the bond formed by the solder ball formed after the reflow. 1. Even if the bonding surface of the semiconductor component has a non-planar phenomenon such as warpage or distortion, the amount of solder paste applied can be automatically adjusted, and fine adjustment can be performed to make the solder ball formed by the solder paste reflow have substantially coplanar external contact points. In order to solve the problem of empty or false soldering of solder balls during surface bonding. - By using the groove design of the template, the template is not in direct contact with the flux, the number of times of template printing can be increased, and the frequency of template cleaning or replacement can be reduced. Fourth, the depth of the through hole of the template is shortened by the groove of the template, thereby reducing the through hole and The adhesive area of the solder paste helps the solder paste to fall by gravity, so it can meet the requirements of the tiny solder ball pitch, achieve high-density solder ball placement and contribute to the development of miniaturization of semiconductor components. 5. Due to the elimination of the cavity at the bottom of the solder ball, the strength and effect of the ball grid array component 200945521 can be improved. 6. The through hole of the template can be formed with an acute angle edge at the periphery of the opening facing the groove, so that the template can restrict lateral overflow of the solder paste into the through hole of the template toward the template groove. [Embodiment] A method of forming a solder ball on a surface of a semiconductor element in accordance with the present invention is described as a cross-sectional view of an element in Figs. 3A to 3F. First, as shown in Fig. 3A, a semiconductor element 210 is provided. In this embodiment, the semiconductor device 2 10 is a ball grid array package (BGA package) that does not have a solder ball, and mainly includes a wafer 213, a substrate 214, and a gel 2 1 5 . . The wafer 2 1 3 is electrically connected to the conductive lines (not shown) of the substrate 214 by a plurality of bonding wires 2 16 , and the wafer 213 is sealed with the sealing body 215 and the bonding wires 216 ′ are appropriately provided. The package is protected against electrical shorts and dust contamination. Generally, the substrate 2 14 includes at least one insulating layer and at least one wiring layer, wherein the insulating layer is a glass fiber cloth impregnating resin, BT resin (bismaleimide triazine resin) or FR- 4 epoxy resin. The semiconductor component 210 has a bonding surface 211 that is bonded to the outer surface, i.e., the substrate 214 is exposed to the surface of the encapsulant 215. A plurality of metal plastics * 212 are attached to the joint surface 211 for providing solder balls. Thereafter, the semiconductor device 210 is placed and 10 200945521 is fixed on a stage 220 as shown in Fig. 3B, and a layer of flux 230 is formed on the metal pads 212 of the bonding surface 211. The pattern shape of the flux 230 corresponds to the metal pads 212, and is preferably slightly larger than the metal pads 212. The flux 230 is formed by a screen printing technique. The thickness of the sensitizer 230 is about 30 to 300 β m. The flux 230 which is currently used is mainly composed of a mixture of rosin and a diluent. During the component soldering process, the flux 230 functions to clean the surface Φ of the metal pads 212 and enhance the soldering ability, and can remove oxides, greases, and other substances that may interfere with the soldering of the solder metal surface, and reduce the soldering of the solder. The surface tension between the metal mats improves the wettability, provides proper rot, foaming, volatility, and viscosity, which enhances the soldering effect and facilitates the soldering process. Next, as shown in Fig. 3C, a template 240 is provided on the semiconductor device 210, and a solder paste 260 is formed on the flux 230 by stencii printing. Specifically, as shown in FIG. 3C and FIG. 5, the template 240 used in the embodiment has a squeegeing plane 241 and a pressing surface 244, and the pressing surface 244 is in the squeegee. One of the printing planes 241 is opposite the surface and is formed with a recess 242. The template 240 further has a plurality of through holes 243 ′ for filling the solder paste 260 to communicate with the squeegee plane 241 to the recess 242, wherein the depth of the recess 2 42 is greater than the thickness of the flux 230 In order to prevent the template 240 from being pressed against the flux 230, the template 240 13 can be increased in number, and the template 240 can be reduced in cleaning or/and replacement frequency. In addition, 11 . 200945521 'Using the groove 242 ′ during the stencil printing, the template 240 does not squeeze the flux 230, so the flux 230 on the corresponding metal pad 212 does not diffuse the connection 'can achieve the use of stencil printing A solder paste 260 is formed on the flux 230 by a technical means. The through holes 2 43 communicating with the recesses 242 are more fully formed as the solder paste 260, so that the application amount of the solder paste 260 can be controlled and formed with high efficiency. The stencil printing process is as shown in FIGS. 3C and 3D, and the solder paste 241 can be filled into the through holes 243 from the lithographic plane 241 of the template 240 by a doctor blade 25 to form the solder paste 260. The flux 230 is on. Preferably, the solder paste 260 may contain no or only a small amount of flux, so that the metal particles in the solder paste 260 are densely arranged in a small gap so as to prevent air holes from being generated inside the solder ball. In detail, as shown in Fig. 5, the template 240 may have a plurality of venting holes 245 in the pressing surface 244 to facilitate the evacuation of air by the stencil 24 when the solder paste 260 is filled. In addition, since the characteristics of the conventional solder paste 10 and the printing template have a so-called ratio of 1 to 1.5, that is, the through-hole diameter of the template must be greater than the thickness of the template (ie, the depth of the via) by more than 15 times. It is easy to cause the solder paste to block in the through hole of the template, and cannot be printed on the metal pad. The template 240 of the present invention has a recess 2 42 ′ which reduces the depth of the through holes 243 without affecting the supporting strength of the template, thereby reducing the adhesion area of the through holes 243 and the solder paste 260, thereby contributing to The solder paste 260 is dropped by gravity, so the diameter of the through holes 243 can be effectively reduced and the pitch can be reduced to form a small solder ball pitch, achieving a high-density solder ball arrangement and contributing to the development of miniaturization of semiconductor components. 12 200945521 After that, as shown in Figure 3E, gold > a reflow process, the semiconductor component 21 printed with solder paste 260 is transferred to a reflow oven (refl〇w 〇ven) Then, the solder paste solder paste 260 is reflowed through the reflow process to form a plurality of solder bump solder balls 261 bonded to the metal pads 212 (as shown in FIG. 3F). At the time of reflow, the bismuth flux 230 standing under the solder paste 260 brings out the gas slab at the bottom of the solder paste 260 when volatilized, thereby promoting the melting of the solder paste 260 to be cohesive into a ball. Therefore, as shown in Fig. 4, the solder balls 261 which are reflowed by the above-mentioned method of the present invention by the sergeant do not form a gas hole at the bottom of the f* ❹ ❿ f, Eliminating the conventional direct printing solder paste on the metal pad 35 creates a void problem at the bottom of the solder ball. Specifically, the step θ θ knows that the continuous tempering process is to first reach the bundle of chrome enamel of the flux 230 to teach the person > the upper button < the volatilization point U to remove the flux 230, and then reach the The solder paste of the 26-inch solder paste machine smashes the melting point so that the tin 260 melts to form a ball. Preferably, as shown in Fig. 6, the temperature rise curve of the Q-welding step may be stepped. The first stage is to maintain the F at the volatilization point of the sensitizer 230 due to the main component of the auxiliaries 230. The A 4 J soil component is a mixture of rosin and diluent. The general diluent mixture has a point of between about 125 and 250 °C. The rosin will be at 7 Celsius. 0 獬K 70 C to 1〇〇C or even 120. (: begins to soften and flow to the surface of the welding call to be joined. During the reflow process, the flux in the flux 2300 is mixed with the private t 1 t 砰 浞 浞 σ will continue to be from the solder paste 260 Volatilized, since the flux 230 is formed under the tibia 260, it will help to discharge the air at the bottom of the solder paste 260 from the 馇_ work emulsion. The first stage is maintained at about the solder balls 261. Hyun point, through the beta people from the media. Pass I Between 185 ° C. (: to 400 ° C ' to melt the solder paste 260 and cohesion into a ball. 13 200945521 In addition, the semiconductor component 210 of the present invention It may be a ball grid array package structure (BGA package), or may be selected from a flip chip package and a semiconductor wafer.

一，可運用於球柵陣列封裝構造之銲球製作與晶片或晶 圓的覆晶凸塊製作。此外m量生產的考量，該半 導體元件210之該接合表面211係可形成於一基板條 (StHP)之一單元區内，而該模板24〇之該凹槽242係具 有猶小於該單元區但覆蓋該些金屬塾212之覆蓋區 域在大量生產時，一般係將複數個球栅陣列基板整合 在一基板條上，該基板條上具有複數個對正孔 (alignment hole)，用以使封裝製程（包括封膠）自動化。 因此，可以理解的，根據本發明較佳實施例之製造方法 的圖示僅繪示單一球格陣列基板，但在應用上本發明的 每步驟亦可同時實施在該基板條上的所有球栅陣列 基板。 本發明之第一具體實施例，揭示另一種在半導體元 件表面形成銲球之方法。第7A至7C圖為在一種半導 體元件表面形成銲球之方法中元件截面示意圖。 首先’如第7A圖所示，提供一半導體元件3 10,該 半導體7L件310係具有一接合表面311，即該基板314 之外表面’該接合表面311係設置有複數個金屬墊 312 ’以供接合銲球。在本實施例中，該半導體元件310 係為覆日日封裝構造（flip chip package)，主要包含一晶 片313、一基板314以及複數個凸塊315。該晶片313 14 ❿First, it can be used in the fabrication of solder balls for ball grid array package construction and the fabrication of wafer or crystal flip chip bumps. In addition, in consideration of the mass production, the bonding surface 211 of the semiconductor device 210 may be formed in one of the cell regions of the substrate strip (StHP), and the recess 242 of the template 24 is smaller than the cell region. When the cover area covering the metal crucibles 212 is mass-produced, a plurality of ball grid array substrates are generally integrated on a substrate strip, and the substrate strip has a plurality of alignment holes for the packaging process. (including sealing) automation. Therefore, it can be understood that the illustration of the manufacturing method according to the preferred embodiment of the present invention only shows a single ball grid array substrate, but in the application, all the ball grids on the substrate strip can be simultaneously implemented in each step of the invention. Array substrate. A first embodiment of the present invention discloses another method of forming solder balls on the surface of a semiconductor device. 7A to 7C are schematic cross-sectional views of elements in a method of forming a solder ball on the surface of a semiconductor element. First, as shown in FIG. 7A, a semiconductor device 3 10 is provided. The semiconductor 7L member 310 has a bonding surface 311, that is, the outer surface of the substrate 314. The bonding surface 311 is provided with a plurality of metal pads 312'. For bonding solder balls. In this embodiment, the semiconductor device 310 is a flip chip package, and mainly includes a wafer 313, a substrate 314, and a plurality of bumps 315. The wafer 313 14 ❿

200945521 係以該些凸塊315電性連接至該基板314之 (圖未繪出），並以一底部填充膠316密封保護 凸塊315。具體而言，在本實施例中，該半導體 之該接合表面3 1 1有著趣曲、扭曲或非平面的 如該接合表面311係為凸弧面。這是因為在半 中之溫度變化如基板烘烤（baking)、封用 (curing)、後續熱循環（thermal cycle)作業等環 基板314之該接合表面311與内表面之間產生 應力（thermal stress)而造成非平面現象。 再如第7A圖所示，將該半導體元件31〇放 於一載台320上’並形成一層助銲劑330於該 311之該些金屬墊312上。並提供一模板340 體元件310上’以模板印刷方式形成錫膏360 劑330上。具體而言，如第7A圖所示，在本 所使用之模板340係具有一刮印平面341，在 面341之另一相對表面係為一壓合面344，其 該半導體元件310之該接合表面311周邊。 344係形成有一凹槽342，該楔板34〇係另具 可供錫膏360填入之通孔343,其係連通該刮科 至該凹槽342 ’其中該凹槽342之深度係大於 330之厚度，以使該模板340不壓觸至該助錦 進而可增加該模板3 40印刷次數，減少該模板 或更換頻率’雄可達成在錫膏360下方的該琢 無溢流擴散的功效。較佳地，該些通孔343在 導電線路 該些該些 元件3 1 0 現象，例 導體製程 I體固化 境下，該 不同之熱 置並固定 接合表面 於該半導 於該助銲 實施例中 該刮印平 可壓合至 該壓合面 有複數個 »平面341 該助銲劑 劑 330， 3 40清潔 |銲劑3 3 0 朝向該凹 15 200945521 槽342之開口周緣係形成有一銳角邊緣345 ’該銳角邊 緣345可限制錫膏360填入該些通孔343時錫膏360往 兩邊溢流。再如第7A圖所示，在模板印刷過程中，可 藉由刮刀3 5 0自該模板3 4 0之該到印平面3 4 1填入錫 膏360至該些通孔343内，以使錫膏36〇形成於該助銲 劑330上。 ❹ ❿ 一如第7B圖所示，在模板印刷之後，移除該模板34〇， 該模板340不會沾附該助銲劑33〇,並且藉由該凹槽342 能縮短該些通孔343的深度，以減少錫膏36〇在該些通 ? 3内的殘留量。此外，形成於該助銲劑上之錫 膏360係可因應該接合表面311自動修正而具有不同之 厚度，例如該半導體元件31〇之該接合表面3ιι為凸弧 面時，位於該接合表面311外邊緣之錫膏36〇則具有較 高之厚度，而中間料36G則具有較低之厚度，以在回 焊成球時具有大致共平面的銲球接合點。 之後，進行-回焊步驟，將已印上錫膏36〇在助銲 劑330上之該半導體元件31 — 移至 回爐内，經由回 焊製程回焊錫膏3 6〇，而开；# 士、[姑 而形成如第7C圖所示之複數個 接合於該些金屬墊312上的捏 的銲球361。回焊過程中，該 助銲劑330可帶出錫膏36〇 展邛之虱體，再使錫膏3 60 熔化以内聚成球。因此，利用士士、+ ^ J用此方法回焊出之該些銲球 361底部不會形成氣洞， 月除S知直接印刷錫膏在金屬 墊上會產生位在銲球接合底部的氣洞(v〇id)問題。 在本實施例中，第7C圖所示，該些銲球361係可具 16 200945521 有大致共平面的對外接觸點。即當該半導體元件310之 該接合表面311係為凸弧面時，該些銲球361中周邊銲 球的球徑係大於中央銲球的球徑，而形成一大致共平面 的對外接觸點，以利於與外部印刷電路板之電性連接。 即使該半導體元件310的該接合表面311有翹曲或扭曲 等非平面現象，利用本發明之銲球形成方法，能進行微 調以使該些銲球3 61具有大致共平面的對外接觸點，藉 以解決該半導體元件310在表面接合時的空焊或假焊 ❹ 現象。 本發明之第三具體實施例，揭示另一種在半導體元 件表面形成銲球之方法。第8A至8C圖為在半導體元 件表面形成銲球之方法中元件截面示意圖。 首先，如第8A圖所示，提供一半導體元件41〇,在 本實施例中，該半導體元件4 1 0係為一開窗型球柵陣列 (WBGA, window ball grid array)半導體封裝件，其係製 備一基板4 1 4，其係開設有一開孔4 1 7，該半導體元件 410係具有一接合表面411’即該基板414之對外表面。 該接合表面411係形成有複數個金屬墊412，以供設置 銲·球。一晶片413係貼置於該基板414且遮覆住該開孔 4 1 7。複數個銲線4 1 6係穿過該開孔4 1 7並電性連接該 晶片4 1 3至該基板4 1 4。至少包含絕緣樹脂之一封膠體 4 1 5係包覆該晶片4 1 3並填入該開孔4 1 7中，以密封該 些銲線416。在本實施例中’該半導體元件41〇之該接 合表面411係可為凹孤面或其它非平面現象，形成之原 17 200945521 因包括該基板414烘烤、該封膠體415固化（curing)、 後續熱循環（thermal cycle)作業等等所造成。 ❹ ❹ 再如第8A圖所示，在模板印刷之前，先將該半導體 元件41〇放置並固定於一載台420上，並形成一層助銲 劑43 0於該接合表面4"之該些金屬墊412上。在模板 印刷過程中，提供一模板440於該半導體元件410上， 利用一刮刀450的刮印，以形成錫膏460於該助銲劑 430上。具體而言，如第7A圖所示，在本實施例中所 使用之模板440係具有一刮印平面441與一相對之壓合 面444 ’並在該壓合面444形成有一凹槽442，該模板 440係另具有複數個可供錫音46〇填入之通孔443，其 係連通該刮印平面441至該凹槽442，其中該凹槽442 之深度係大於該助銲劑430之厚度，以使該模板44〇不 壓觸至該助銲劑430。藉由該到刀45〇的動作，使在該 刮印平面441上的錫膏460被填入於該些通孔443内， 再形成於該助銲劑430上。如第8B圖所示，在模板印 刷之後，移除該模板440，再進行一回焊步驟。 回焊過程中，將印上錫膏460在該助銲劑43〇上之 該半導體元件41〇移至一回焊爐内，移除該助銲劑43〇 並使錫膏460經由回焊製程而形成如第8C圖所干之複 數個接合於該些金屬墊412上的銲球461。該助銲劑々Μ 在回焊步驟時，可帶出錫膏460底部之氣體，再使锡膏 46〇熔化以内聚成球…匕’利用此方法回焊形成之該 些銲球461在底部不會形成氣洞，消除習知直接印刷^ 18 200945521 成在金屬墊上錫膏會產生位在銲球接合底部的氣洞問 題。 在本實施例中，即使該半導體元件410之該接合表 面411係為凹弧面或其它非平面現象。利用該模板 440，可修正凹弧面而使形成於該助銲劑430上之錫膏 460具有不同之厚度，也就是說在接近該半導體元件 410之該接合表面411中央的錫膏厚度會大於在該接合 表面411周邊的錫膏厚度。因此，第8C圖所示，回焊 形成之該些銲球461係可具有大致共平面的對外接觸 點。當該半導體元件410之該接合表面411係為凹弧面 時，該些銲球46 1中周邊銲球的球徑係小於中央銲球的 球徑’以利於與外部印刷電路板之電性連接。 因此’即使該半導體元件41〇的該接合表面411有 勉曲或扭曲等非平面現象，利用本發明之銲球形成方 法，能進行微調以使該些銲球461具有大致共平面的對 外接觸點，藉以解決表面接合時的空焊現象。 以上所述’僅是本發明的較佳實施例而已，並非對 本發明作任何形式上的限制，本發明技術方案範圍當依 所附申明專利範圍為準。任何熟悉本專業的技術人員可 利用上述揭不的技術内容作出些許更動或修飾為等同 變化的等效實施例’但凡是未脫離本發明技術方案的内 容，依據本發明的技術實質對以上實施例所作的任何簡 單修改、等同變化與修飾，均仍屬於本發明技術方案的 範圍内。 ' 19 200945521 【圖式簡單說明】 面形成銲球之 第1A至1E圖：為習知在半導體元件表 方法中之元件截面示意圖。The bumps 315 are electrically connected to the substrate 314 (not shown), and the protective bumps 315 are sealed with an underfill 316. Specifically, in the present embodiment, the joint surface 31 of the semiconductor is interesting, twisted or non-planar as the joint surface 311 is a convex curved surface. This is because thermal stress is generated between the bonding surface 311 and the inner surface of the ring substrate 314 such as substrate baking, curing, and subsequent thermal cycle operations. ) caused a non-planar phenomenon. Further, as shown in Fig. 7A, the semiconductor device 31 is placed on a stage 320 and a flux 330 is formed on the metal pads 312 of the 311. A template 340 body element 310 is provided to form a solder paste 360 agent 330 by stencil printing. Specifically, as shown in FIG. 7A, the template 340 used in the present invention has a squeegeing plane 341, and the other opposing surface of the surface 341 is a pressing surface 344 to which the semiconductor element 310 is bonded. The periphery of the surface 311. The 344 is formed with a recess 342. The wedge 34 is further provided with a through hole 343 for filling the solder paste 360, and communicates the scraping to the recess 342', wherein the depth of the recess 342 is greater than 330. The thickness is such that the template 340 does not press the brocade to further increase the number of times the template 340 is printed, and the stencil or replacement frequency can be reduced to achieve the effect of the 琢 without overflow diffusion under the solder paste 360. Preferably, the through holes 343 are in the conductive line of the plurality of elements 3 10 , in the case of a conductive process, the different heat is applied and the bonding surface is fixed in the semiconductor in the soldering embodiment. The squeegee can be pressed to the pressing surface to have a plurality of » planes 341. The fluxing agent 330, 3 40 cleaning|flux 3 3 0 toward the concave 15 200945521 The opening periphery of the groove 342 is formed with an acute angle edge 345 ' The sharp edge 345 limits the solder paste 360 from overflowing on both sides when the solder paste 360 is filled into the vias 343. Further, as shown in FIG. 7A, in the stencil printing process, the solder paste 360 may be filled into the through holes 343 from the template 3404 by the doctor blade 350 to the through holes 343. A solder paste 36 is formed on the flux 330. ❿ ❿ As shown in FIG. 7B, after the stencil printing, the template 34 is removed, the template 340 does not adhere to the flux 33, and the through holes 343 can be shortened by the recess 342. Depth to reduce the amount of residual solder paste 36 in the pass 3 . In addition, the solder paste 360 formed on the flux may have different thicknesses due to the automatic modification of the bonding surface 311. For example, when the bonding surface 3 ι of the semiconductor component 31 is a convex curved surface, the bonding surface 311 is located outside the bonding surface 311. The edge solder paste 36 turns to a higher thickness, while the intermediate material 36G has a lower thickness to have a substantially coplanar solder ball joint when reflowed into a ball. Thereafter, the -reflow step is performed, and the semiconductor element 31 on which the solder paste 36 is soldered on the flux 330 is moved to the furnace, and the solder paste is returned to the solder paste via the reflow process, and is opened; #士,[ A plurality of pinned solder balls 361 bonded to the metal pads 312 as shown in Fig. 7C are formed. During the reflow process, the flux 330 can carry out the solder paste 36, and then the solder paste 3 60 is melted to cohesively form a ball. Therefore, the use of the gentleman, + ^ J in this way to reflow the solder balls 361 at the bottom of the solder ball 361 will not form a hole, the monthly visible S paste direct printing solder paste on the metal pad will create a hole in the bottom of the solder ball joint (v〇id) question. In the present embodiment, as shown in Fig. 7C, the solder balls 361 may have a substantially coplanar external contact point with 16 200945521. That is, when the bonding surface 311 of the semiconductor component 310 is a convex arc surface, the ball diameter of the surrounding solder balls in the solder balls 361 is larger than the ball diameter of the center solder ball, and a substantially coplanar external contact point is formed. In order to facilitate the electrical connection with the external printed circuit board. Even if the bonding surface 311 of the semiconductor element 310 has a non-planar phenomenon such as warpage or distortion, the solder ball forming method of the present invention can be fine-tuned so that the solder balls 3 61 have substantially coplanar external contact points, thereby The phenomenon of void welding or false soldering of the semiconductor element 310 at the time of surface bonding is solved. A third embodiment of the present invention discloses another method of forming solder balls on the surface of a semiconductor device. Figs. 8A to 8C are schematic cross-sectional views showing the elements in a method of forming solder balls on the surface of a semiconductor element. First, as shown in FIG. 8A, a semiconductor device 41 is provided. In the embodiment, the semiconductor device 410 is a window ball grid array (WBGA) semiconductor package. A substrate 4 1 4 is formed which has an opening 4 17 . The semiconductor component 410 has an bonding surface 411 ′ which is an outer surface of the substrate 414 . The joint surface 411 is formed with a plurality of metal pads 412 for providing a solder ball. A wafer 413 is attached to the substrate 414 and covers the opening 4 17 . A plurality of bonding wires 4 16 are passed through the opening 4 17 and electrically connected to the substrate 4 1 3 to the substrate 4 1 4 . A colloid comprising at least an insulating resin 4 1 5 coats the wafer 4 1 3 and fills the opening 4 17 to seal the bonding wires 416. In the present embodiment, the bonding surface 411 of the semiconductor device 41 can be a concave orbital surface or other non-planar phenomenon. The original 17 200945521 is formed by baking the substrate 414, and the sealing body 415 is cured. Subsequent thermal cycle operations and the like. ❹ ❹ As shown in FIG. 8A, before the stencil printing, the semiconductor device 41 is placed and fixed on a stage 420, and a layer of flux 43 0 is formed on the bonding surface 4" 412. In the stencil printing process, a template 440 is provided on the semiconductor component 410, and a squeegee of a doctor blade 450 is used to form a solder paste 460 on the flux 430. Specifically, as shown in FIG. 7A, the template 440 used in the embodiment has a squeegeing plane 441 and an opposite pressing surface 444', and a recess 442 is formed in the pressing surface 444. The template 440 further has a plurality of through holes 443 for filling the tin tones 46, which are connected to the printing plane 441 to the recess 442, wherein the depth of the recess 442 is greater than the thickness of the flux 430. So that the template 44 does not touch the flux 430. The solder paste 460 on the dicing plane 441 is filled in the through holes 443 by the action of the knives 45 ,, and is formed on the flux 430. As shown in Fig. 8B, after the stencil is printed, the template 440 is removed and a reflow step is performed. During the reflow process, the semiconductor component 41 on which the solder paste 460 is printed on the flux 43 is transferred to a reflow furnace, the flux 43 is removed, and the solder paste 460 is formed through a reflow process. A plurality of solder balls 461 bonded to the metal pads 412 are dried as shown in FIG. 8C. The flux 々Μ can bring out the gas at the bottom of the solder paste 460 during the reflow step, and then melt the solder paste 46 to cohesively form a ball... 匕 'The solder balls 461 formed by reflow by this method are not at the bottom A cavity will be formed to eliminate the conventional direct printing ^ 18 200945521 The solder paste on the metal pad will create a cavity problem at the bottom of the solder ball joint. In the present embodiment, even if the joint surface 411 of the semiconductor element 410 is a concave curved surface or other non-planar phenomenon. With the template 440, the concave arc surface can be corrected to make the solder paste 460 formed on the flux 430 have different thicknesses, that is, the thickness of the solder paste near the center of the bonding surface 411 of the semiconductor device 410 is greater than The thickness of the solder paste around the bonding surface 411. Thus, as shown in Figure 8C, the solder balls 461 formed by reflow can have substantially coplanar external contacts. When the bonding surface 411 of the semiconductor component 410 is a concave curved surface, the spherical diameter of the surrounding solder balls in the solder balls 46 1 is smaller than the spherical diameter of the central solder ball to facilitate electrical connection with the external printed circuit board. . Therefore, even if the bonding surface 411 of the semiconductor element 41 has a non-planar phenomenon such as distortion or distortion, the solder ball forming method of the present invention can be fine-tuned so that the solder balls 461 have substantially coplanar external contact points. In order to solve the phenomenon of surface welding during surface bonding. The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. The scope of the present invention is defined by the scope of the appended claims. Any person skilled in the art can make a few changes or modifications to the equivalent embodiment by using the above-mentioned technical content. However, without departing from the technical solution of the present invention, the above embodiments are in accordance with the technical essence of the present invention. Any simple modifications, equivalent changes and modifications made by the invention are still within the scope of the technical solutions of the present invention. ' 19 200945521 [Simple description of the drawing] The surface forming the solder balls 1A to 1E are schematic cross-sectional views of the elements in the conventional semiconductor device method.

第2圖：為習知利用該方法形成之銲球之 & % ^^示音IS 第3A至3F圖：為依據本發明第一具 *、。 道触- 見施例的在主 導體7L件表面形成銲球之方法 半 意圖。 之7"件截面示Fig. 2 is a view of a solder ball formed by the method of the prior art. & % ^^ shows a sound IS 3A to 3F: a first * according to the present invention. Road contact - see the method of forming a solder ball on the surface of the main conductor 7L of the embodiment. 7"

❹ 第4圖：為依據本發明第一具體實施例所 銲球之 截面不意圖。 第5圖：使用本發明第一具體實施例的模板之立體示意 圖。 第6圖：為依據本發明第一具體實施例在回焊步驟中的 溫度與時間之曲線圖。 第7A至7C圖.為依據本發明第二具體實施例的在半 導體元件表面形成銲球之方法之元件截面示 意圖。 第8A至8C圖：為依據本發明第三具體實施例的在半 導體元件表面形成銲球之方法之元件截面示 意圖。 【主要元件符號說明】 11〇半導體元件 ill接合表面 113晶片 114基板 116銲線 120載台 112金屬墊 115封膠體 20 200945521 140模板 141 150刮刀 160錫膏 161 210半導體元件 211 213晶片 214 216銲線 220載台 230 240模板 241 © 243 通孔 244 250刮刀 260 310半導體元件 311 313晶片 314 3 1 6底部填充膠 320載台 330 340模板 341 343通孔 344 ❹ 3 50刮刀 3 60 410半導體元件 411 413晶片 414 416銲線 420載台 430 440模板 441 443通孔 450刮刀 460 刮印平面 143 通孔 鲜球 162 氣洞 接合表面 212 金屬墊 基板 215 封膠體 助銲劑 刮印平面 242 凹槽 壓合面 245 排氣槽孔 錫膏 261 鲜球 接合表面 312 金屬墊 基板 315 凸塊 助銲劑 刮印平面 342 凹槽 壓合面 345 銳角邊緣 錫膏 361 鲜球 接合表面 412 金屬墊 基板 415 封膠體 助銲劑 刮印平面 442 凹槽 錫膏 461 鮮球 21❹ Fig. 4 is a cross-sectional view of the solder ball according to the first embodiment of the present invention. Fig. 5 is a perspective view showing the use of the template of the first embodiment of the present invention. Figure 6 is a graph showing temperature versus time in a reflow step in accordance with a first embodiment of the present invention. 7A to 7C are cross-sectional views showing the elements of a method of forming solder balls on the surface of a semiconductor element in accordance with a second embodiment of the present invention. 8A to 8C are cross-sectional views showing the elements of a method of forming solder balls on the surface of a semiconductor element in accordance with a third embodiment of the present invention. [Main component symbol description] 11 〇 semiconductor component ill bonding surface 113 wafer 114 substrate 116 bonding wire 120 stage 112 metal pad 115 sealing body 20 200945521 140 template 141 150 blade 160 solder paste 161 210 semiconductor component 211 213 wafer 214 216 bonding wire 220 stage 230 240 template 241 © 243 through hole 244 250 blade 260 310 semiconductor element 311 313 wafer 314 3 1 6 underfill 320 stage 330 340 template 341 343 through hole 344 ❹ 3 50 blade 3 60 410 semiconductor element 411 413 Wafer 414 416 bond wire 420 stage 430 440 template 441 443 through hole 450 scraper 460 stencil plane 143 through hole fresh ball 162 cavity joint surface 212 metal pad substrate 215 sealant flux squeegee plane 242 groove press surface 245 exhaust Slot solder paste 261 Fresh ball joint surface 312 Metal pad substrate 315 Bump flux squeegee plane 342 Groove press surface 345 Sharp corner edge solder paste 361 Fresh ball joint surface 412 Metal pad substrate 415 Sealant flux squeegee plane 442 Groove solder paste 461 fresh ball 21

Claims (1)

200945521 十、申請專利範圓： 之方法，包含： 表面之複數個金屬墊； 、-種在半導體元件表面形成鮮球 提供一半導體元件，其係具有在一 形成一層助銲劑於該些金屬墊上；200945521 X. Patent application: The method comprises: a plurality of metal pads on a surface; and a seed forming a fresh ball on the surface of the semiconductor component, wherein a semiconductor component is formed on the metal pad; 以模板印刷方式形成㈣於該助銲劑上所使用之模板 係具^料平面，並在該料平面之另—相對表面形 成有間’該模板係另具有複數個可供錫膏填入之通 孔’其係連通該刮印平面至該凹槽，其中該凹槽之深度 係大於該助銲劑之厚度，以使該模板不壓觸至該助鮮 回焊該錫膏，以形成為複數個接合於該些金屬墊上的銲 面形成銲 2、如申請專利範圍帛1項所述之在半導體元件表 球之方法，其中該錫膏係不包含助銲劑。 3、 如申請專利職第1項所述之在半導體元件表面形成銲 球之方法，其中上述回焊步驟係為一連續昇溫過程，先 到達該助銲劑之沸點，以移除該助銲劑並帶出該錫膏底 部之氣體，再使該錫膏熔化以内聚成球。 4、 如申請專利範圍第3項所述之在半導體元件表面形成鲜 球之方法，其中上述回焊步驟之昇溫曲線係為階梯狀， 第一階段是約維持在該助銲劑之沸點，第二階段是約維 持在該些銲球的熔點。 5、如申請專利範圍第丨項所述之在半導體元件表面形成銲 球之方法，其中該些銲球具有大致共平面的對外接觸點。 22 200945521 6 7 9、 10 Ο 11 、如申請專利範圍第5項所述之在半導體元件表面形成辉 球之方法，其中當該半導體元件之該表面係為凸派面 時’該些銲料周邊銲球的球徑係大於中央銲球的球捏。 ‘如申請專利範圍第5項所述之在半㈣元件表面形成鲜 球，方法，其中當該半導體元件之該表面係為凹弧面 時’该些銲球巾周邊料的球彳线小於巾央銲球的球徑。 如申請專利範圍第i項所述之在半導體元件表面形成鲜 球之方法’《中該何體元件之該表面係形成於一基板 條之一單元區内，而該模板之該凹槽係具有一稍小於該 單兀區但覆蓋該些金屬墊之覆蓋區域。 如申請專利範圍第i項所述之在半導體元件表面形成鲜 球之方法’其中該半導體元件係選自於—球栅陣列封裝 構造（BGA package)、一覆晶封裝構造（fUp响 與一半導體晶圓之其中之一。 、如申請專利範圍第i項所述之在半導體元件表面形成 銲球之方法’其中該些通孔在朝向該凹槽之開口周緣係 形成有一銳角邊緣。 、如申請專利範圍第i項所述之在半導體元件表面形成 銲球之方法，其中該模板在形成有該凹槽之表面係形成 有一或更多的排氣槽孔，其係連通到該凹槽。 、如申請專利範圍第1項所述之在半導體元件表面形成 銲球之方法’其中該助銲劑的圖案形狀係對應於該呰金 屬塾。 23 12Forming (4) the template used on the flux is formed by stencil printing, and a surface is formed on the other opposite surface of the material plane. The template has a plurality of passes for filling the solder paste. The hole 'connects the printing plane to the groove, wherein the depth of the groove is greater than the thickness of the flux, so that the template does not press the solder paste to the solder paste to form a plurality of A soldering surface bonded to the metal pads forms a soldering method according to the invention of claim 1, wherein the solder paste does not contain a flux. 3. The method of forming a solder ball on a surface of a semiconductor component according to claim 1, wherein the reflowing step is a continuous heating process, and first reaches a boiling point of the flux to remove the flux and bring The gas at the bottom of the solder paste is removed, and the solder paste is melted to be cohesive into a ball. 4. The method of forming a fresh ball on a surface of a semiconductor component according to claim 3, wherein the temperature rise curve of the reflow step is stepped, the first stage is maintained at a boiling point of the flux, and the second The stage is maintained at about the melting point of the solder balls. 5. A method of forming solder balls on a surface of a semiconductor component as described in the scope of the patent application, wherein the solder balls have substantially coplanar external contact points. 22 200945521 6 7 9, 10 Ο 11 . The method of forming a glow sphere on a surface of a semiconductor component according to claim 5, wherein when the surface of the semiconductor component is a convex surface, The ball diameter of the ball is larger than the ball pinch of the center solder ball. The method of forming a fresh ball on the surface of a half (four) component as described in claim 5, wherein when the surface of the semiconductor component is a concave curved surface, the ball line of the peripheral material of the solder ball is smaller than the towel The ball diameter of the ball. The method of forming a fresh ball on the surface of a semiconductor component as described in the scope of claim [i] of the invention, wherein the surface of the component is formed in a cell region of a substrate strip, and the recess of the template has A cover area slightly smaller than the single turn but covering the metal pads. A method for forming a fresh ball on a surface of a semiconductor element as described in the scope of claim 4, wherein the semiconductor element is selected from a ball grid array package structure (BGA package), a flip chip package structure (fUp ring and a semiconductor) A method of forming a solder ball on a surface of a semiconductor device as described in claim i wherein the through holes are formed with an acute-angled edge at an opening toward the opening of the groove. The method of forming a solder ball on a surface of a semiconductor element according to the invention of claim 4, wherein the template forms one or more exhaust slots formed on the surface on which the groove is formed, and is connected to the groove. A method of forming a solder ball on a surface of a semiconductor element as described in claim 1 wherein the pattern shape of the flux corresponds to the ruthenium metal. 23 12
TW097115102A 2008-04-24 2008-04-24 Method for forming solder balls on a surface of a semiconductor component TWI371840B (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI409891B (en) * 2010-02-11 2013-09-21
CN116825752A (en) * 2023-08-29 2023-09-29 江西兆驰半导体有限公司 Wafer and printing method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI409891B (en) * 2010-02-11 2013-09-21
CN116825752A (en) * 2023-08-29 2023-09-29 江西兆驰半导体有限公司 Wafer and printing method thereof
CN116825752B (en) * 2023-08-29 2024-02-09 江西兆驰半导体有限公司 Wafer and printing method thereof

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