200941263 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種積體電路佈局設計之檢驗方法， 特別是關於-種設計制檢查和佈局與圖式規則檢查。 【先前技術】 隨著積體電路技術之發展，電顧助設計（cad)系統 尤其是電子料自動化(EDA)技術係日益被運㈣半導體 積體電路之設計中。 ❹ 在實際生產製造積體電路晶片前，一般會以審查軟體 進行檢查，確涊此積體電路的設計符合將要用以生產製造 此一晶片之製程要求與限制，包括確認此積體電路實體設 計之佈局相付於其圖式之設計，這些都是在實際製造一電 路前非常重要的步驟。有了這些確認的程序，由指定製程 所製造出來的電路特性才得以保障。 諸如用以生產製造一晶片之製程要求與限制，檢查積 艘電路實體設計之佈局是否相符於其圖式之設計的方法， ©〆般統稱為「規則」。在實際執行上，這些規則被稱為設 計規則檢查規則（design rule check rules，DRC rules)及佈局 與圖式規則（layout versus schematic rules，LVS rules)。 在設計積體電路(IC)之金屬導線(特別是電源線時），若 不同層之金屬導線銜接處的接觸孔(via)排列太狹長，或接 觸孔數量不夠，很容易發生燒毀的現象，因此有必要針對 此問題’在進行設計規則檢查(DRC)時，找出有問題之設 計部份’並把其標示出來。 6 200941263 【發明内容】 根據上述問題，本發明提出一種積體電路佈局設計之 檢驗方法，包括以下步驟：選擇一電路設計佈局進行檢查， 根據一判斷規則，判斷電路設計佈局中，位於不同層間導 線重疊處之接觸孔(via)排列是否太狹長，或接觸孔數量是 否不夠。在一實施例中，電路設計佈局中包括位於一第一 金屬層之導線和位於一第二金屬層之導線，第一金屬層之 導線和第二金屬層之導線至少在一重疊區域彼此重疊，且 ❿第一金屬層之導線和第二金屬層之導線係藉由複數個接觸 孔電性連接，判斷重疊區域中接觸孔之總面積和重疊區域 之面積的比例是否小於一警示值，以判斷電路設計佈局 中，位於不同層間導線重疊處之接觸孔(via)排列是否太狹 長，或接觸孔數量是否不夠。 【實施方式】 以下根據第1圖詳細說明本發明之流程，其中並會以 第2圖和第3圖輔助說明之。首先，進行步驟S102，設定 ® 判斷規則，用以判斷電路設計佈局中不同層之金屬導線(例 如電源線)銜接處的接觸孔(via)排列是否太狹長，或接觸孔 數量是否不夠，以避免發生燒毁的現象。請同時參照第2 圖，輔助說明本實施例判斷規則之設定，如圖所示，一第 一金屬層202和一第二金屬層206位於不同層，且第一金 屬層202係位於第二金屬層206上方。在本實施例中，第 一金屬層202包括複數條大體上沿Y轴方向延伸之導線 204，第二金屬層206包括複數條大體上沿X軸方向延伸 7 200941263 之導線208，第一金屬層和第二金屬層之導線204、208則 藉由接觸孔(via)212電性連接。本實施例第一金屬層之導 線204的寬度W!大於第二金屬層之導線208的寬度W2。 爲避免上述不同層之金屬導線銜接處接觸孔(via)排列 太狹長，或接觸孔數量不夠，而造成燒毁之問題，本實施 例進行設計規則檢查（DRC)，以一例如Mentor Graphics Corp.公司所提供之Calibre軟體，計算出第一金屬層之導 線204和第二金屬層之導線208的重疊區域210，本實施 ⑩例將重疊區域210之面積定義為第一金屬層之導線204的 寬度W!乘以第一金屬層之導線204的寬度（亦即 WpWO。另外，本實施例可以Calibre軟體計算重疊區域 210中接觸孔212之總面積a。本實施例之判斷規則即是重 疊區域210中接觸孔212之總面積a除以重疊區域210之 -^τ<Ρ 面積（WfWO是否小於一警示值Ρ(亦即是否W )。重疊區 域中接觸孔212之總面積a除以重疊區域210之面積 ❹X小於警示值P，則代表第一金屬層之導線204和第 二金屬層之導線208銜接處的接觸孔212排列太狹長，或 接觸孔212數量不夠。 進行步驟S104，對所選擇之電路設計佈局進行設計規 則檢查，於步驟S106中，判斷第一金屬層之導線和第二金 屬層之導線銜接處的接觸孔是否排列太狹長，或接觸孔數 量是否不足。在本實施例中，以下列方式作出判斷：重疊 區域中接觸孔之總面積a除以重疊區域之面積（WfW!)* —<p 否小於一警示值P(—般為1/4)，亦即是否β2 。若小於警 200941263 示值P，則進行步驟S108，發出警示訊號，把警示之區域 標示（highlight)出來。此時，可進行步驟S110，增加接觸 孔之數量或面積，例如第3圖所示，將第一金屬層之導線 204a向下延伸，和/或增加部份第二金屬層之導線208a的 寬度，於其間增加接觸孔212a之數量。 本發明在設計積體電路(1C)之金屬導線時，可根據上述 方法警示不同層之金屬導線銜接處接觸孔(via)排列是否太 狹長，或接觸孔數量是否不夠，以避免發生燒毁的現象。 ❹ 以上提供之實施例係用以描述本發明不同之技術特 徵，但根據本發明之概念，其可包括或運用於更廣泛之技 術範圍。須注意的是，實施例僅用以揭示本發明製程、裝 置、組成、製造和使用之特定方法，並不用以限定本發明， 任何熟習此技藝者，在不脫離本發明之精神和範圍内，當 可作些許之更動與潤飾。因此，本發明之保護範圍，當視 後附之申請專利範圍所界定者為準。 ❹ 9 200941263 【圖式簡單說明】 第1圖繪示本發明一實施例積體電路佈局設計之檢驗 方法之流程圖。 第2圖繪示本發明一實施例電路設計佈局之平面圖， 用以輔助說明本發明一實施例積體電路佈局設計之檢驗方 法。 第3圖繪示本發明一實施例電路設計佈局之平面圖， 用以輔助說明本發明一實施例增加接觸孔之數量之範例方 〇法。 【主要元件符號說明】 202〜第一金屬層； 204〜第一金屬層之導線； 204a〜第一金屬層之導線； 206〜第二金屬層； 208〜第二金屬層之導線； 208a〜第二金屬層之導線； ❿ 210〜重疊區域； 212〜接觸孔； 212a〜接觸孔。200941263 Nine, the invention description: [Technical field to which the invention pertains] The present invention relates to an inspection method for an integrated circuit layout design, in particular, a design inspection and layout and pattern rule inspection. [Prior Art] With the development of integrated circuit technology, the cad system, especially the electronic material automation (EDA) technology, is increasingly being designed in the design of semiconductor integrated circuits. ❹ Before the actual production of the integrated circuit chip, the inspection software is generally inspected to confirm that the design of the integrated circuit meets the process requirements and limitations that will be used to manufacture the wafer, including confirming the physical design of the integrated circuit. The layout is balanced with the design of the diagram, which is a very important step before actually manufacturing a circuit. With these confirmed procedures, the circuit characteristics created by the specified process are guaranteed. For example, the process requirements and limitations for manufacturing a wafer, and the method of checking whether the layout of the integrated circuit entity design conforms to the design of the pattern, are collectively referred to as "rules." In practice, these rules are called design rule check rules (DRC rules) and layout versus schematic rules (LVS rules). When designing the metal wires of the integrated circuit (IC) (especially when the power line is used), if the contact holes of the metal wires of different layers are arranged too narrowly, or the number of contact holes is insufficient, the burning phenomenon is likely to occur. Therefore, it is necessary to identify and designate the problematic design part of the problem during the Design Rule Check (DRC). 6 200941263 SUMMARY OF THE INVENTION According to the above problems, the present invention provides a method for verifying the layout design of an integrated circuit, comprising the steps of: selecting a circuit design layout for inspection, and judging the circuit design layout, located in different interlayer wires according to a judgment rule Whether the contact holes in the overlap are too long or the number of contact holes is insufficient. In one embodiment, the circuit design layout includes a wire on a first metal layer and a wire on a second metal layer, and the wires of the first metal layer and the wires of the second metal layer overlap each other at least in an overlapping region. And the wire of the first metal layer and the wire of the second metal layer are electrically connected by a plurality of contact holes, and it is determined whether the ratio of the total area of the contact hole and the area of the overlapping area in the overlapping area is less than a warning value, so as to determine In the circuit design layout, the arrangement of the vias at the overlap of the wires of different layers is too long, or the number of contact holes is insufficient. [Embodiment] Hereinafter, the flow of the present invention will be described in detail based on Fig. 1, which will be explained with reference to Figs. 2 and 3. First, in step S102, the setting rule is judged to determine whether the contact holes of the metal wires (for example, power lines) at different layers in the circuit design layout are too narrow, or the number of contact holes is insufficient to avoid The phenomenon of burning has occurred. Referring to FIG. 2 at the same time, the setting of the determination rule of the embodiment is assisted. As shown, a first metal layer 202 and a second metal layer 206 are located in different layers, and the first metal layer 202 is located in the second metal. Above layer 206. In the present embodiment, the first metal layer 202 includes a plurality of wires 204 extending substantially in the Y-axis direction, and the second metal layer 206 includes a plurality of wires 208 extending substantially in the X-axis direction 7 200941263, the first metal layer The wires 204, 208 of the second metal layer are electrically connected by a via 212. The width W! of the wire 204 of the first metal layer of this embodiment is greater than the width W2 of the wire 208 of the second metal layer. In order to avoid the arrangement of the contact holes of the metal wires of the different layers mentioned above, the arrangement of the vias is too long, or the number of contact holes is insufficient, and the problem of burnout is caused, the present embodiment performs a design rule check (DRC), for example, a Mentor Graphics Corp. The Calibre software provided by the company calculates the overlap region 210 of the wire 204 of the first metal layer and the wire 208 of the second metal layer. In the embodiment 10, the area of the overlap region 210 is defined as the width of the wire 204 of the first metal layer. W! Multiplied by the width of the wire 204 of the first metal layer (ie, WpWO. In addition, in this embodiment, the total area a of the contact hole 212 in the overlap region 210 can be calculated by the Calibre software. The judgment rule of this embodiment is the overlap region 210. The total area a of the contact holes 212 is divided by the -^τ<Ρ area of the overlap region 210 (whether WfWO is less than a warning value Ρ (i.e., whether W). The total area a of the contact holes 212 in the overlap region is divided by the overlap region 210. If the area ❹X is smaller than the warning value P, the contact hole 212 representing the junction of the wire 204 of the first metal layer and the wire 208 of the second metal layer is too narrow, or the number of the contact holes 212 is insufficient. 104. Perform design rule checking on the selected circuit design layout. In step S106, determine whether the contact holes of the wires of the first metal layer and the wires of the second metal layer are arranged too narrowly, or whether the number of contact holes is insufficient. In the present embodiment, the judgment is made in such a manner that the total area a of the contact holes in the overlap region is divided by the area of the overlap region (WfW!)* - <p is less than a warning value P (- 1/4) , that is, whether it is β2. If it is less than the alarm value 200941263, the process proceeds to step S108, and a warning signal is issued to highlight the area of the warning. At this time, step S110 may be performed to increase the number or area of the contact holes, for example, As shown in Fig. 3, the wire 204a of the first metal layer is extended downward, and/or the width of the wire 208a of a portion of the second metal layer is increased to increase the number of contact holes 212a therebetween. The present invention is in the design of an integrated circuit. When the metal wire of (1C) is used, it can be warned according to the above method whether the contact holes of the metal wires at different layers are too narrow, or the number of contact holes is insufficient to avoid burning. The embodiments provided above are intended to describe various technical features of the present invention, but may be included or applied to a broader range of technical aspects in accordance with the teachings of the present invention. It is noted that the embodiments are only used to disclose the process of the present invention. The specific method of the device, the composition, the manufacture and the use of the present invention is not intended to limit the invention, and any modification and refinement can be made without departing from the spirit and scope of the invention. The scope is defined by the scope of the patent application. ❹ 9 200941263 [Simplified Schematic] FIG. 1 is a flow chart showing a method for verifying the layout design of an integrated circuit according to an embodiment of the present invention. 2 is a plan view showing a circuit design layout of an embodiment of the present invention for assisting in explaining an inspection method for an integrated circuit layout design according to an embodiment of the present invention. FIG. 3 is a plan view showing a circuit design layout of an embodiment of the present invention to assist in explaining an exemplary method of increasing the number of contact holes in an embodiment of the present invention. [Description of main component symbols] 202 to the first metal layer; 204 to the first metal layer; 204a to the first metal layer; 206 to the second metal layer; 208 to the second metal layer; 208a~ Two metal layer wires; ❿ 210~ overlap region; 212~ contact hole; 212a~ contact hole.