200941017 九、發明說明 【發明所屬之技術領域】 本發明係關於··將複數個電池的狀態加以監視之電池 狀態監視電路、以及，具備了電池狀態監視電路之電池裝 置。 , 【先前技術】 φ 說明有關先前的電池裝置。第2圖爲將電池裝置加以 表示的方塊圖。 電池狀態監視電路60，係將電池7 1的狀態予以監視 。檢測電路6 1，係將電池7 1的過充電狀態以及過放電狀 態加以檢測。延遲電路62，係一從檢測電路6 1輸入訊號 ，則在特定的延遲時間經過後，將該訊號進行輸出。控制 電路64，係在特定的時刻，以遮斷充電路徑的方式來動作 。充電控制電晶體8 1，係藉由進行關閉（OFF )動作，來 φ 將從充電器（無圖示）到電池71之充電路徑，予以遮斷 。另外，控制電路64，係在特定的時刻，以遮斷放電路徑 的方式來動作。放電控制電晶體82係藉由進行關閉（OFF )’來將由電池71至負載（無圖示）之放電路徑予以遮 斷（例如，參照專利文獻1 )。 [專利文獻1]日本特開2007-195303號公報。 【發明內容】 [發明所欲解決的課題] -5 - 200941017 在此，電池裝置係在第2圖中爲具有1個，但是有時 具有複數個電池。此時，對於控制電路64，作爲電源而供 給的電壓，係成爲根據複數個電池的電壓之電源電壓VVD ，控制電路64係成爲：將根據該電源電壓VVD之高位準 (high level)訊號以及根據接地電壓VSS之低位準（l〇w level)訊號，輸出至充電控制電晶體81以及放電控制電 晶體82的閘極。 另外，充電控制電晶體8 1以及放電控制電晶體82的 耐壓，係根據被施加在閘極的電壓來進行電路設計。 因而，充電控制電晶體8 1以及放電控制電晶體82， 係因爲被施加在閘極的電壓變高，所以變得要使用高耐壓 用的元件。因而，充電控制電晶體8 1以及放電控制電晶 體82的製造成本變高，電池裝置的製造成本亦變高。 本發明，係鑑於如此的要點，提供：電池裝置的製造 成本變低之電池狀態監視電路以及該電池裝置。 [用以解決課題的手段] 本發明係爲了解決上述課題，提供一種電池狀態監視 電路，以具備：一種檢測電路，係將電池的充放電狀態加 以檢測，將表示其狀態的檢測訊號加以輸出、一種延遲電 路’係將檢測訊號予以輸入，在特定的延遲時間經過後， 將檢測訊號加以輸出、一種電壓調整器，係將根據複數個 電池的電壓而來之電源電壓予以輸入，將低於電源電壓之 定電壓予以輸出、與一種控制電路，係一有檢測訊號輸入 -6- 200941017 ，就將根據接地電壓之低位準（low level )訊號、和根據 前述電壓調整器所輸出的定電壓之高位準（high level ) 訊號，輸出至充放電控制用電晶體的閘極；來作爲其特徵 〇 另外，本發明，係提供具備了上述電池狀態監視電路 之電池裝置。 φ [發明的效果] 在本發明，係充電控制電晶體以及放電控制電晶體， 爲基於根據電壓調整器而來的輸出電壓之高位準（high level)訊號，來進行動作，該電壓調整器的輸出電壓係低 於根據複數個電池的電壓而來的電源電壓。因而，充電控 制電晶體以及放電控制電晶體，係因爲被施加在閘極的電 壓爲變低，所以可使用低耐壓用的元件。因此，充電控制 電晶體以及放電控制電晶體的製造成本變低，電池裝置的 φ 製造成本亦變低。 【實施方式】 以下，將本發明的實施形態，參照圖面來說明。 首先，說明有關電池裝置的構成。第1圖爲將電池裝 置加以表示的方塊圖。 電池裝置，係具備有：電池2卜24、電池狀態監視電 路10、充電控制NMOS電晶體31以及放電控制NMOS電 晶體32。另外，電池裝置，係具備有外部端子EB +以及外 -7- 200941017 部端子EB-。 電池狀態監視電路10，係具有：檢測電路11、延遲 電路12、電壓調整器13以及控制電路14。另外，電池狀 態監視電路1 〇，係具有：監視器端子V1 ~ν 5、控制端子 C Ο以及控制端子D Ο。 電池21-24爲串聯連接，電池21係連接於外部端子 ΕΒ+，電池24係連接於放電控制NMOS電晶體32。電池 21的+端子係被連接於監視器端子VI ’電池22的+端子係 連接於監視器端子V2，電池23的+端子係連接於監視器 端子V3，電池24的+端子係連接於監視器端子V4，電池 24的-端子係連接於監視器端子V5。充電控制NMOS電晶 體31，係設置在放電控制NMOS電晶體32與外部端子 ΕΒ-之間。充電控制NMOS電晶體31的閘極係連接於控 制端子CO、放電控制NMOS電晶體3.2的閘極係連接於控 制端子DO。 檢測電路11，係連接於監視器端子VI〜V5以及延遲 電路12。延遲電路12，係連接於監視器端子VI、監視器 端子V5以及控制電路14。電壓調整器13，係連接於監視 器端子VI、監視器端子V5以及控制電路14。控制電路 14，係連接於監視器端子V5、控制端子CO以及控制端子 DO。 在此，電池狀態監視電路1 0，係將電池2 1〜24的狀態 予以監視。檢測電路1 1，係將電池2 1 ~24的過充電狀態以 及過放電狀態加以檢測。延遲電路1 2，係一從檢測電路 -8 - 200941017 11輸入訊號，則在特定的延遲時間經過後，將該訊號進行 輸出。電壓調整器13，係將一定的輸出電壓予以輸出。控 制電路14，係在特定的時刻，以遮斷充電路徑的方式來動 作。充電控制NMOS電晶體31，係藉由進行關閉（OFF) 動作，來將從充電器（無圖示）到電池21〜2 4之充電路徑 . ，予以遮斷。另外，控制電路14，係在特定的時刻，以遮 • 斷放電路徑的方式來動作。放電控制NM0S電晶體32, φ 係藉由進行關閉（OFF )動作，來將從電池21〜24到負載 (無圖示）之放電路徑，予以遮斷。 另外，電壓調整器13的輸出電壓，係以電路設計至 未滿：充電控制NMOS電晶體31以及放電控制NM0S電 晶體32之耐壓電壓。 接著，說明有關電池裝置的動作。 [在充電器係將電池進行充電，電池成爲過充電狀態 之情況下]充電器係被連接於電池裝置，充電開始。電壓 φ 調整器13，係根據基於電池21 ~24的電壓而來之電源電壓 VDD，來將低於電源電壓VDD之一定的輸出電壓予以輸 出。 若電泄2 1〜24中之任1個電池係成爲過充電狀態，則 檢測電路11，係檢測該電池的過充電狀態而將表示其意旨 的過充電檢測訊號，輸出至延遲電路12。延遲電路12, 係在特定的延遲時間經過後，將過充電檢測訊號輸出至控 制電路14。於是，控制電路14,係將根據電壓調整器13 的輸出電壓而來之高位準（high level )訊號，輸出至放 200941017 電控制NMOS電晶體32的閘極，放電控制NMOS電晶體 32爲開啓（ON)。另外，控制電路14係將根據接地電壓 VSS而來的低位準（low level)訊號，輸出至充電控制 NMOS電晶體3 1的閘極，充電控制NMOS電晶體31爲關 閉（OFF)。若充電控制NMOS電晶體31爲關閉（OFF) ，則藉由寄生二極體（（parasitic diode))而放電電流 爲流動，但充電電流係變得不流動。因而，由充電器朝向 電池21 ~24的充電路徑係被遮斷，被禁止充電。 [在電池係放電於負載，電池成爲過放電狀態之情況 下]負載係被連接於電池裝置，開始放電。電壓調整器13 ，係基於根據電池2 1~24的電壓而來之電源電壓VDD，來 將低於電源電壓VDD之一定的輸出電壓進行輸出。 若電池2 1 ~24中之任1個電池係成爲過放電狀態，則 檢測電路1 1，係檢測該電池的過放電狀態而將表示其意旨 的過放電檢測訊號，輸出至延遲電路12。延遲電路12, 係在特定的延遲時間經過後，將過放電檢測訊號輸出至控 制電路14。於是，控制電路14係將高位準（high level) 訊號輸出至充電控制NMOS電晶體3 1的閘極，充電控制 NMOS電晶體31爲開啓（ON )。另外，控制電路14係將 低位準（low level)訊號輸出至放電控制NMOS電晶體 32的閘極，放電控制NMOS電晶體32爲關閉（OFF)。 若放電控制NMOS電晶體32爲關閉（OFF )，則藉由寄 生二極體而充電電流爲流動，但放電電流係變得不流動。 因而，由電池21~24朝向負載的放電路徑係被遮斷，被禁 -10- 200941017 止放電。 若如此般地進行，則充電控制NMOS電晶體3 1以及 放電控制NMOS電晶體32，其動作係不是根據基於電池 21〜24的電壓而來之電源電壓VDD，而是根據基於電壓調 整器13的輸出電壓而來之高位準（high level)訊號、以 . 及基於接地電壓VSS而來之低位準（low level)訊號。因 . 而，充電控制NMOS電晶體31以及放電控制NMOS電晶 φ 體32，係因爲被施加在閘極的電壓爲變低，所以耐壓即使 低亦變佳、即使不使用高耐壓用的元件亦變佳。因此，充 電控制NMOS電晶體3 1以及放電控制NMOS電晶體3 2的 製造成本變低，電池裝置的製造成本亦變低。 另外，控制電路14，因爲並非是供給電源電壓VDD 而是將壓器13的輸出電壓予以供給，作爲電源而供給的 電壓係變低，所以即使耐壓爲低亦變佳，即使不使用高耐 壓用的元件亦變佳，面積爲變小。另外，控制電路14，係 φ 因爲作爲電源而供給的電壓爲變低，所以消耗電力變少。 另外，被施加在充電控制NMOS電晶體31以及放電 控制NMOS電晶體32的閘極之電壓，係因爲是電壓調整 器13的輸出電壓，所以是一定。因而，充電控制NMOS 電晶體31以及放電控制NMOS電晶體32的開啓（ON) 阻抗係成爲一定。 另外，被施加在充電控制NMOS電晶體31以及放電 控制NMOS電晶體32的閘極之電壓，係因爲是電壓調整 器1 3的輸出電壓，所以未滿充電控制NMOS電晶體3 1以 -11 - 200941017 及放電控制NMOS電晶體32的耐壓電壓。因而，用以將 充電控制NMOS電晶體31及放電控制NMOS電晶體32的 耐壓予以保護之零件，係變爲在電池裝置中不需要，所以 電池裝置的製造成本爲變低。 另外，將充電路徑予以遮斷的元件以及將放電路徑予 以遮斷之元件，係爲設置在電池24與外部端子EB-之間 的充電控制NMO S電晶體3 1以及放電控制NMO S電晶體 32，但爲設置在電池21與外部端子EB +之間的充電控制 PMOS電晶體（無圖示）以及放電控制PMOS電晶體（無 圖示）亦佳。在此，適宜地將控制電路14設計爲：對於 充電控制NMOS電晶體3 1以及放電控制NMOS電晶體32 的閘極，施加有在電壓調整器13的輸出電壓與接地電壓 VSS之間的電壓、對於充電控制PMOS電晶體（無圖示） 以及放電控制PMOS電晶體（無圖示）之閘極，施加有電 源電壓VDD與電壓調整器13的輸出電壓之間的電壓。 另外，對於延遲電路12，作爲電源而供給的電壓，係 爲電源電壓VDD與接地電壓VSS之間的電壓，但其爲電 壓調整器13的輸出電壓與接地電壓VSS之間的電壓亦佳 ，而且爲電源電壓VDD與電壓調整器13的輸出電壓之間 的電壓亦佳。 於是，延遲電路12，係因爲作爲電源而被供給的電壓 爲變低，所以即使耐壓爲低亦變佳、即使不使用高耐壓用 的元件亦變佳、面積爲變小。另外，延遲電路12，係因爲 作爲電源而供給的電壓爲變低，所以消耗電力變少。 -12- 200941017 另外，電池裝置的電池數，係爲4個，但即使未滿4 個、爲5個以上亦佳。 另外，電池狀態監視電路10係1個半導體裝置，而 充電控制NMOS電晶體31及放電控制NMOS電晶體32爲 FET，但電池狀態監視電路10、充電控制NMOS電晶體 , 31以及放電控制NMOS電晶體32爲1個半導體裝置亦佳 〇 ❿ 【圖式簡單說明】 [第1圖]爲將電池裝置加以表示的方塊圖。 [第2圖]爲將先前的電池裝置加以表示的方塊圖。 【主要元件符號說明】 I 〇 :電池狀態監視電路 II :檢測電路 φ 12 :延遲電路 13 :電壓調整器 1 4 :控制電路 21〜24 :電池 31 :充電控制NMOS電晶體 32 :放電控制NMOS電晶體 EB+ :外部端子 EB-:外部端子 VI〜V5 :監視器端子 -13- 200941017 CO :控制端子 DO :控制端子 V D D :電源電壓 V S S :接地電壓[Technical Field] The present invention relates to a battery state monitoring circuit that monitors the state of a plurality of batteries, and a battery device including a battery state monitoring circuit. [Prior Art] φ Describes the previous battery unit. Fig. 2 is a block diagram showing a battery device. The battery state monitoring circuit 60 monitors the state of the battery 71. The detecting circuit 610 detects the overcharged state and the overdischarged state of the battery 71. The delay circuit 62 receives a signal from the detection circuit 61, and outputs the signal after a certain delay time elapses. The control circuit 64 operates to interrupt the charging path at a specific time. The charge control transistor 81 is turned off by a charging (OFF) operation from the charger (not shown) to the charging path of the battery 71. Further, the control circuit 64 operates to interrupt the discharge path at a specific timing. The discharge control transistor 82 blocks the discharge path from the battery 71 to the load (not shown) by turning off (OFF) (for example, see Patent Document 1). [Patent Document 1] Japanese Laid-Open Patent Publication No. 2007-195303. [Problem to be Solved by the Invention] -5 - 200941017 Here, the battery device has one battery in the second drawing, but may have a plurality of batteries. At this time, the voltage supplied as the power supply to the control circuit 64 is the power supply voltage VVD based on the voltage of the plurality of batteries, and the control circuit 64 is based on the high level signal of the power supply voltage VVD and The low level signal of the ground voltage VSS is output to the gates of the charge control transistor 81 and the discharge control transistor 82. Further, the withstand voltages of the charge control transistor 81 and the discharge control transistor 82 are designed in accordance with the voltage applied to the gate. Therefore, since the charge control transistor 81 and the discharge control transistor 82 become high in voltage applied to the gate, it is necessary to use an element for high withstand voltage. Therefore, the manufacturing cost of the charge control transistor 81 and the discharge control transistor 82 becomes high, and the manufacturing cost of the battery device also becomes high. The present invention provides, in view of such a point, a battery state monitoring circuit in which the manufacturing cost of a battery device is lowered, and the battery device. [Means for Solving the Problem] In order to solve the above problems, the present invention provides a battery state monitoring circuit including: a detection circuit that detects a state of charge and discharge of a battery, and outputs a detection signal indicating a state thereof; A delay circuit is configured to input a detection signal, and after a specific delay time elapses, output a detection signal, and a voltage regulator is input according to a voltage of a plurality of batteries, which is lower than the power supply. The voltage constant voltage is output, and a control circuit, which has a detection signal input -6-200941017, will be based on the low level signal of the ground voltage and the high level of the constant voltage output according to the aforementioned voltage regulator The high level signal is output to the gate of the charge and discharge control transistor. As a feature of the present invention, the present invention provides a battery device including the battery state monitoring circuit. φ [Effects of the Invention] In the present invention, a charge control transistor and a discharge control transistor are operated based on a high level signal of an output voltage according to a voltage regulator, the voltage regulator The output voltage is lower than the supply voltage from the voltage of a plurality of batteries. Therefore, in the charge control transistor and the discharge control transistor, since the voltage applied to the gate is low, an element for low withstand voltage can be used. Therefore, the manufacturing cost of the charge control transistor and the discharge control transistor becomes low, and the manufacturing cost of the φ of the battery device also becomes low. [Embodiment] Hereinafter, embodiments of the present invention will be described with reference to the drawings. First, the configuration of the battery device will be described. Figure 1 is a block diagram showing the battery unit. The battery device includes a battery 2, a battery state monitoring circuit 10, a charge control NMOS transistor 31, and a discharge control NMOS transistor 32. Further, the battery device is provided with an external terminal EB + and an external -7-200941017 terminal EB-. The battery state monitoring circuit 10 includes a detecting circuit 11, a delay circuit 12, a voltage regulator 13, and a control circuit 14. Further, the battery state monitoring circuit 1 includes monitor terminals V1 to ν 5, a control terminal C Ο, and a control terminal D Ο. The batteries 21-24 are connected in series, the battery 21 is connected to the external terminal ΕΒ+, and the battery 24 is connected to the discharge control NMOS transistor 32. The + terminal of the battery 21 is connected to the monitor terminal VI. The + terminal of the battery 22 is connected to the monitor terminal V2, the + terminal of the battery 23 is connected to the monitor terminal V3, and the + terminal of the battery 24 is connected to the monitor. The terminal V4 and the terminal of the battery 24 are connected to the monitor terminal V5. The charge control NMOS transistor 31 is provided between the discharge control NMOS transistor 32 and the external terminal ΕΒ-. The gate of the charge control NMOS transistor 31 is connected to the control terminal CO, and the gate of the discharge control NMOS transistor 3.2 is connected to the control terminal DO. The detection circuit 11 is connected to the monitor terminals VI to V5 and the delay circuit 12. The delay circuit 12 is connected to the monitor terminal VI, the monitor terminal V5, and the control circuit 14. The voltage regulator 13 is connected to the monitor terminal VI, the monitor terminal V5, and the control circuit 14. The control circuit 14 is connected to the monitor terminal V5, the control terminal CO, and the control terminal DO. Here, the battery state monitoring circuit 10 monitors the states of the batteries 2 1 to 24 . The detection circuit 1 1 detects the overcharged state of the batteries 2 1 to 24 and the overdischarged state. The delay circuit 12 is configured to input a signal from the detection circuit -8 - 200941017, and then output the signal after a certain delay time elapses. The voltage regulator 13 outputs a certain output voltage. The control circuit 14 operates to interrupt the charging path at a specific time. The charge control NMOS transistor 31 is blocked by a charge path from the charger (not shown) to the batteries 21 to 24 by performing an OFF operation. Further, the control circuit 14 operates to block the discharge path at a specific timing. The discharge control NM0S transistor 32, φ is turned off from the discharge paths of the batteries 21 to 24 to the load (not shown) by performing an OFF operation. Further, the output voltage of the voltage regulator 13 is designed to be under voltage: the charge control NMOS transistor 31 and the discharge control NM0S transistor 32 withstand voltage. Next, the operation of the battery device will be described. [When the charger charges the battery and the battery becomes overcharged] The charger is connected to the battery unit and charging starts. The voltage φ regulator 13 outputs a constant output voltage lower than the power supply voltage VDD based on the power supply voltage VDD based on the voltages of the batteries 21 to 24. When any one of the batteries 21 to 24 is in an overcharged state, the detection circuit 11 detects the overcharge state of the battery and outputs an overcharge detection signal indicating the purpose to the delay circuit 12. The delay circuit 12 outputs an overcharge detection signal to the control circuit 14 after a lapse of a specific delay time. Then, the control circuit 14 outputs a high level signal according to the output voltage of the voltage regulator 13 to the gate of the 200941017 electrically controlled NMOS transistor 32, and the discharge control NMOS transistor 32 is turned on ( ON). Further, the control circuit 14 outputs a low level signal according to the ground voltage VSS to the gate of the charge control NMOS transistor 31, and the charge control NMOS transistor 31 is turned off (OFF). When the charge control NMOS transistor 31 is turned off, the discharge current flows by the parasitic diode, but the charge current does not flow. Therefore, the charging path from the charger toward the batteries 21 to 24 is blocked, and charging is prohibited. [When the battery is discharged to the load and the battery is in an overdischarged state] The load is connected to the battery device and discharge starts. The voltage regulator 13 outputs a constant output voltage lower than the power supply voltage VDD based on the power supply voltage VDD from the voltages of the batteries 2 1 to 24 . When any one of the batteries 2 1 to 24 is in an overdischarged state, the detection circuit 1 1 detects the overdischarge state of the battery and outputs an overdischarge detection signal indicating the purpose to the delay circuit 12 . The delay circuit 12 outputs an overdischarge detection signal to the control circuit 14 after a lapse of a specific delay time. Thus, the control circuit 14 outputs a high level signal to the gate of the charge control NMOS transistor 3 1 , and the charge control NMOS transistor 31 is turned "ON". Further, the control circuit 14 outputs a low level signal to the gate of the discharge control NMOS transistor 32, and the discharge control NMOS transistor 32 is OFF. When the discharge control NMOS transistor 32 is off (OFF), the charging current flows by the parasitic diode, but the discharge current does not flow. Therefore, the discharge paths from the batteries 21 to 24 toward the load are blocked, and the discharge is prohibited by -10-200941017. When the above is performed, the charge control NMOS transistor 31 and the discharge control NMOS transistor 32 are operated not according to the power supply voltage VDD based on the voltages of the batteries 21 to 24, but are based on the voltage regulator 13 based on The high level signal from the output voltage, and the low level signal based on the ground voltage VSS. In the charge control NMOS transistor 31 and the discharge control NMOS transistor φ body 32, since the voltage applied to the gate is low, the withstand voltage is low even if the high withstand voltage is not used. The components are also getting better. Therefore, the manufacturing cost of the charge control NMOS transistor 31 and the discharge control NMOS transistor 3 2 becomes low, and the manufacturing cost of the battery device also becomes low. Further, since the control circuit 14 supplies the output voltage of the voltage regulator 13 instead of supplying the power supply voltage VDD, the voltage supplied as the power source is low, so that the withstand voltage is low, even if high resistance is not used. The components used for pressing are also better, and the area is smaller. Further, in the control circuit 14, since the voltage supplied as the power source becomes lower, the power consumption is reduced. Further, the voltage applied to the gates of the charge control NMOS transistor 31 and the discharge control NMOS transistor 32 is constant because it is the output voltage of the voltage regulator 13. Therefore, the ON (impedance) impedance of the charge control NMOS transistor 31 and the discharge control NMOS transistor 32 is constant. Further, the voltage applied to the gates of the charge control NMOS transistor 31 and the discharge control NMOS transistor 32 is due to the output voltage of the voltage regulator 13, so that the charge control NMOS transistor 3 1 is not full - 11 - 200941017 and the breakdown voltage of the discharge control NMOS transistor 32. Therefore, the parts for protecting the withstand voltage of the charge control NMOS transistor 31 and the discharge control NMOS transistor 32 are not required in the battery device, so that the manufacturing cost of the battery device is lowered. Further, an element that blocks the charging path and an element that blocks the discharge path are a charge control NMO S transistor 3 1 and a discharge control NMO S transistor 32 that are disposed between the battery 24 and the external terminal EB-. However, it is also preferable to charge control PMOS transistor (not shown) and discharge control PMOS transistor (not shown) provided between the battery 21 and the external terminal EB + . Here, the control circuit 14 is suitably designed such that the voltage between the output voltage of the voltage regulator 13 and the ground voltage VSS is applied to the gates of the charge control NMOS transistor 31 and the discharge control NMOS transistor 32, A voltage between the power supply voltage VDD and the output voltage of the voltage regulator 13 is applied to the gates of the charge control PMOS transistor (not shown) and the discharge control PMOS transistor (not shown). Further, in the delay circuit 12, the voltage supplied as the power source is a voltage between the power supply voltage VDD and the ground voltage VSS, but the voltage between the output voltage of the voltage regulator 13 and the ground voltage VSS is also good, and The voltage between the power supply voltage VDD and the output voltage of the voltage regulator 13 is also good. In the delay circuit 12, since the voltage supplied as the power source is low, the withstand voltage is low, and the element for high withstand voltage is not used, and the area is reduced. Further, in the delay circuit 12, since the voltage supplied as the power source is low, the power consumption is reduced. -12- 200941017 In addition, the number of batteries in the battery unit is four, but it is better if it is less than four and five or more. Further, the battery state monitoring circuit 10 is a semiconductor device, and the charge control NMOS transistor 31 and the discharge control NMOS transistor 32 are FETs, but the battery state monitoring circuit 10, the charge control NMOS transistor, 31, and the discharge control NMOS transistor. 32 is a semiconductor device. [A brief description of the drawings] [Fig. 1] is a block diagram showing a battery device. [Fig. 2] is a block diagram showing a conventional battery device. [Main component symbol description] I 〇: Battery state monitoring circuit II: Detection circuit φ 12 : Delay circuit 13 : Voltage regulator 1 4 : Control circuit 21 to 24 : Battery 31 : Charge control NMOS transistor 32 : Discharge control NMOS Crystal EB+: External terminal EB-: External terminal VI~V5: Monitor terminal-13- 200941017 CO: Control terminal DO: Control terminal VDD: Power supply voltage VSS: Ground voltage