200939441 yu，τηγ % 说明： 【發明所屬之技術領域】 本發明係有關於一種半莫 裝結構，尤指-種提高封裝及其製法暨封 靠度之半導趙封裝基板及其製法傳輸效率與電性接點可 【先前技術】 隨著電子產業的發達，現今的電子產品已趨向㈣短 出、=能多樣化的方向設計，半導體封裝 ❹出不同的封裝型態，傳統半導體裝置主要係在—封裝= (package substrate)或導線架 土 電性連接在該封裝其柘式逡 、’ 1 re cmd) 裝，銬而悝始、土 5導線杀上，接著以膠體進行封 性2 易造成較大電阻，使得封襄結構電 此外，於以膠體封裝時，流動之膠體容易破壞谭 線、..構，造成變形甚至於短路，導致製造良率降低。 :克服上述之缺陷，IBM公司在196。年早期引入覆 曰曰曰^(F11P Chip Package)技術。相較於打線技術，覆 日日技術之特徵在於採用-封裝基板來安置半導體晶片，並 =該封裝基板表面植置多數個成陣列排列之焊錫結構或 導電結合材料，與位於半導體晶片間作用面上之電極塾電 性及機械性連接。由於兩者間之電性連接並非透過一般焊 而使該種技術因不需使用導電路徑較長之金線，而可 提高電性功能，且電性連接部份較不易遭流動之膠體破 壞，俾可提昇製造良率。然半導體晶片電極塾位置，在配 110641 5 200939441 -口 +上蕙硌板或其他電子元彳 ' ·# rn f* Λπ μ ,, ± 干次疋该+導體晶片之電極 間再加上一介 日日片之功能時，將會於兩者 如第1Α至〗11圖所示。 乍為連接的橋樑。相關技術 請參閱第1Α至圖，係為羽4 + 士 % \Kmpir - ^ 4. 、為白知之封裝基板製法；如 =圖所不，首先提供-基板本體11，係且有相對之一 表面’且於該基板本體u [、有相對之一 12.接莫哲 乂 刀別形成第一金屬層 以，接者，如第1β圖所示， 亥基板本體11及該些苐一 〇萄層12形成至少一通孔13 ;如 第一金屬層12表面與該通孔】q Κ圖所示’於該些 tΛ ^ is之表面上形成導電声 “，且於該導電層U上形成第二金屬層15.:成= 所示，於該通孔13中填入塞 ，士第1D圖 於該第二金屬層15及 第1E圖所不， 莨1 ο及a塞孔材料〗6上 該阻層Π形成複數阻層開口 ^層17,且 層15;如第if圖所-、k 以外路部份第二金屬 中之第-金屬居κ ^ ’以虫刻方式移除該阻層開口 171 τ之第一金屬層15、導雷；】」也你 ❹除該阻戶17, ^ μ 金屬層12，接著移 U層17以形成線路層la l 該線路層la，lb、美軛太麟〗彳a命 弟Μ圖所不，於 佯镬層18，i 土 虹 塞孔材料丨6上形成絕緣 保凌層18，並於該絕緣保護層18 181,182，以顯露部份之線 :？數開孔 接墊此肩；如第1H圖所干丄' 俾以成為電性連 弟圖所不，於該電性連接墊 上分別形成結合材料19a，19b，以與其他電子元件如半 體晶片20及印刷電路板（圖未示）電性連接。 准此種之封裳基板於二表面之線路層h，ib皆設有 110641 6 200939441 · 路半20經多數線路傳輸至印刷 接塾服間的接合以構;，㈣；：/材t19a及電性連 何提高封裝件電性傳輸生點可罪度。因此，如 界之重要課題。 文卞與電性接點可靠度，已成為業 【發明内容】 鑑於上述習知技術 的供-種半導體封之缺失，本發明之-目的係在於提 件電性跡w ^板及其製法暨封裝結構，能提高封裝 牛電生傳輸效率與電性接點可靠度。 為達上边及其他目的，本發明揭露—種半導體美 二=:基板本體，係具有相對之第-表面及第：： 金屬二該第一及第二表面之通孔;第-及第二 金屬％，係分別對應設於該通孔兩端之第一及第 ί第：ί材料，係設於該些通孔内部並延伸至該第- 一、-%上，且於該第二金屬環上呈凸塊狀。 ” 構，復包括於該通孔内壁、第-及第二金屬 該焊接材料之間設有導電層；該通孔中位 楚」人面方向之烊接材料表面係高於、齊平或低於該 玉％上表面；該第一及第二金屬環係為銅㈣。 ;本發明之半導體封裝基板，復可包括第三金屬層，係 设於该通孔内壁、第—及第二金屬環等表面上與該焊接材 料之間’俾以形成導電通孔；且復可於該通孔内壁、第一 及第金屬％等表面上與該第三金屬層之間設有導電 110641 7 200939441 · j，琢垾接材料係為錫（Sn)·、鉛（Pb)、銀α幻、鋼（Cu)、 鋅（ζα、鉍（Bi)、鈀（pd)及金（Au)所組成群組之其中一 者，且該通孔中位於該第一表面方向之焊接材料表面係高 於、齊平或低於該第-金屬環上之第三金屬層表面。 本發明復提供一種半導體封裝基板製法，係包括提 供一基板本體，係具有相對之第一表面及第二表面，且於 該基板本體之第-及第二表面分別形成第—及第二金屬 層；於該基板本體、第-及第二金屬層中形成複數通孔； ❹於該第-、第二金屬層、及該些通孔内壁上形成導電層· =導電層上形成阻層’並形成複數阻層開口以對應顯曰露 μ二通孔及其兩端周圍之導電層；於該阻層開口中之 層上電錢形成第一焊接材料；移除該阻層及其所覆蓋之導 電層、第-及第二金屬層’以於該些通孔兩端之第一及第 —表面上分別形成第一及第二金屬環；以及於該第一 材料對應該第二金屬環處形成凸塊狀之第二焊接材料，且 使該第二焊接材料與第—烊接材料結合成焊接材料。 依上述製法，該通孔中位於該第一表面方向之焊接材 料表面係高於、齊平或低於該第一金屬環上 及第二金屬層係為銅（Cu)。 ’第一 又依前述製法’復包括於形成該第—焊接材料前 ::阻層開口中之導電層上電鍍形成第三金屬層，俾以形 ^電通孔’且該通孔中位於該第一表面方向之焊接材料 表面係南於、齊平或低於該第一金屬環上表面；該 料係為錫(Sn)、鉛⑽、銀(Ag)、銅(Cu)、鋅(Zn)、鉍⑻)、 110641 8 200939441 入1(AU)所組成群組之其中一者。 . 本發明再提供一種封裝結構，係包括··半導體封裝基 板，係於-具有相對第一表面及第二表面之基板本體設有 ，數:穿Θ第-及第二表面之通孔，於該些通孔兩端之第 -及第二表面上分別設有第__及第二金屬環，並於該通孔 内部具有焊接材料，該焊接材料並延伸至該第一及第二金 f環表面上，且於該第二金屬環上呈凸塊狀；以及半導體 f片/係具有一作用面，於該作用面具有複數電極塾，於 ❹j电極墊上設有複數焊料凸塊，使該半導體晶片以覆晶 式透過謂料凸塊對應電性連接該半導體封裝基 k孔中位於該第一表面方向之焊接材料。 上述結構中，該焊接材料係為錫、鉛⑽）、銀 群L之Γ中CO 7(Zn)、叙⑻）、叙（Pd)及金㈤）所組成 Li:: 該第一及第二金屬環係為銅(㈤；該 導體晶片之作用面之間形成有底充材料。 ❹構，由：封裝：咖 焊接材料，電i自半皆設有複數通孔及填充其令之 孔中之焊接材料· a曰片之電極塾可直接經該複數通 性傳輪效率H ^至印刷電路板（圖未示），俾以提高電 裳件之電性接點係由半導體晶片之 電極墊與該複數通 卞守篮明月之 點可靠度。 之炸接材料接合而成，俾以提高接 【實施方式】 以下係藉由特定的具體實例說明本發明之實施方 110641 9 200939441 ，’烈必队技藝之人士可由本說明書所揭示之内容輕易地 -獠解本發明之其他優點與功效。 [弟一貫施例] 請麥閱第2A至2G圖，係詳細說明本發明之半導體封 裝基板製法第一實施例之剖面示意圖。 如第2A圖所示，首先提供一基板本體21，係具有相 對之第表面2la及第二表面21b，且於該基板本體21 之第一及第二表面21a，21b分別形成第一金屬層221及第 ❹二金屬層222，該第一金屬層221及第二金屬層222係為 銅（Cu)。 如第2B圖所示，於該基板本體21、第一及第二金屬 層221，222中形成複數通孔23。 如第2C圖所示，於該第一及第二金屬層221 222上 及該通孔23内壁上形成導電層24。 於該導電層24上形成阻層25，並 以對應顯露該通孔23及其兩端外 如第2D圖所示， 形成複數阻層開口 2 51 ©周圍表面上之導電層2 如第2E圖所示，於該些阻層開口 251中之 上電鍍形成第一焊接材料271。 圖所示，移除該阻層 25及其覆蓋之導電層 以形成複數第一及第二200939441 yu,τηγ % Description: [Technical field of the invention] The present invention relates to a semi-molded structure, in particular to a semi-conductive package substrate for improving packaging, its manufacturing method and sealing degree, and the transmission efficiency thereof Electrical contacts can be [previous technology] With the development of the electronics industry, today's electronic products have become (4) short, = can be diversified in the direction of design, semiconductor packaging out of different packaging types, traditional semiconductor devices are mainly in - package = (package substrate) or lead frame earth-electric connection in the package of its 逡 ', ' 1 re cmd) installed, and then start, soil 5 wire to kill, and then colloidal sealing 2 is easy to cause The large resistance makes the sealing structure electrically. In addition, when it is encapsulated by colloid, the flowing colloid easily breaks the tan wire, the structure, causes deformation or even short circuit, resulting in a decrease in manufacturing yield. : Overcoming the above shortcomings, IBM is at 196. Introduced in the early years of the year, the F11P Chip Package technology was introduced. Compared with the wire bonding technology, the day-to-day technology is characterized in that a semiconductor substrate is mounted by using a package substrate, and a plurality of solder structures or conductive bonding materials arranged in an array are disposed on the surface of the package substrate, and an interaction surface between the semiconductor wafers is disposed. The electrodes on the top are electrically and mechanically connected. Since the electrical connection between the two is not through general welding, the technique can improve the electrical function because the gold wire having a long conductive path is not required, and the electrical connection portion is less susceptible to the colloidal damage of the flowing body.俾 can improve manufacturing yield. However, the position of the semiconductor wafer electrode is matched with 110641 5 200939441 - port + upper plate or other electronic element ' · # rn f * Λ π μ , ± dry 疋 between the electrodes of the + conductor wafer plus one day The function of the film will be as shown in Figure 1 to Figure 11. The bridge is connected. For related art, please refer to the first to the figure, which is the feather 4 + 士% \Kmpir - ^ 4. , is the package substrate manufacturing method of Baizhi; if the figure is not, firstly provide the substrate body 11, which has a relative surface 'And in the substrate body u [, there is a relative one. 12. Connect the Mozhe knife to form a first metal layer, then, as shown in the first β-graph, the substrate body 11 and the layers of the layer 12 forming at least one through hole 13; as shown in the surface of the first metal layer 12 and the through hole, forming a conductive sound on the surface of the conductive layer U, and forming a second metal on the conductive layer U The layer 15.: is shown in the figure, the plug is filled with the plug, and the 1D figure is on the second metal layer 15 and the first E-picture, and the 塞1 ο and a plug material 〗 6 Forming a plurality of resistive opening layers 17 and layer 15; removing the resist opening 171 in a pest-like manner as in the second portion of the second metal in the outer portion of FIG. The first metal layer 15 of τ, the mine guide;]" also removes the resistor 17, ^ μ metal layer 12, and then moves the U layer 17 to form the circuit layer la l the circuit layer la, lb, yoke 〗 彳a life Μ Μ 所 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , A plurality of apertured pads are used for the shoulder; as shown in FIG. 1H, the composite material 19a, 19b is formed on the electrical connection pads to form a bonding material 19a, 19b with other electronic components such as a half-body wafer. 20 and a printed circuit board (not shown) are electrically connected. The circuit layer h and ib of the two-surfaced substrate are provided with 110641 6 200939441. The road half 20 is transmitted to the printing interface between the majority of the lines; (4);: / t19a and electricity How to improve the electrical transmission of the package is guilty. Therefore, it is an important topic in the world.卞 卞 电 电 电 电 电 电 鉴于 鉴于 鉴于 鉴于 鉴于 鉴于 鉴于 鉴于 鉴于 鉴于 鉴于 鉴于 鉴于 鉴于 鉴于 鉴于 鉴于 鉴于 鉴于 鉴于 鉴于 鉴于 鉴于 鉴于 鉴于 鉴于 鉴于 鉴于 鉴于 鉴于 鉴于 鉴于 鉴于 鉴于 鉴于 鉴于 鉴于 鉴于 鉴于 鉴于 鉴于 鉴于The package structure can improve the transmission efficiency and electrical contact reliability of the package. In order to achieve the above and other purposes, the present invention discloses a semiconductor body II: a substrate body having opposite first and second surfaces: a through hole of the first and second surfaces; and a second and second metal %, corresponding to the first and the ίth: ί material disposed at the two ends of the through hole, are disposed inside the through holes and extend to the first -, -%, and the second metal ring It is convex in shape. a structure comprising: a conductive layer disposed between the inner wall of the through hole and the first and second metals; the surface of the through hole in the through hole is higher, flat or low The upper surface of the jade; the first and second metal rings are copper (four). The semiconductor package substrate of the present invention may further include a third metal layer disposed on the inner wall of the through hole, the surface of the first and second metal rings, and the like, to form a conductive via hole; Conductive 110641 7 200939441 · j may be disposed between the inner wall of the through hole, the surface of the first and third metal, and the third metal layer, and the bonding material is tin (Sn)·, lead (Pb), One of a group consisting of silver alpha, steel (Cu), zinc (ζα, bismuth (Bi), palladium (pd), and gold (Au), and the solder material in the first surface direction of the via hole The surface is higher, flatter or lower than the surface of the third metal layer on the first metal ring. The invention further provides a semiconductor package substrate manufacturing method, comprising providing a substrate body having a first surface and a second surface Forming a first and a second metal layer on the first and second surfaces of the substrate body; forming a plurality of through holes in the substrate body, the first and second metal layers; a metal layer, and a conductive layer formed on the inner wall of the through holes · a resist layer formed on the conductive layer Forming a plurality of resistive layer openings to correspond to the conductive layer around the two vias and the two ends thereof; forming a first solder material on the layer in the opening of the resist layer; removing the resist layer and covering the same The conductive layer, the first and second metal layers respectively form first and second metal rings on the first and first surfaces of the two ends of the through holes; and at the second metal ring corresponding to the first material Forming a second solder material in a bump shape, and combining the second solder material with the first solder material to form a solder material. According to the above manufacturing method, the surface of the solder material in the first surface direction of the through hole is higher than Flush or lower than the first metal ring and the second metal layer is copper (Cu). 'The first method according to the foregoing method' is included in the formation of the first soldering material: the conductive layer in the opening of the resist layer Forming a third metal layer on the upper surface, wherein the surface of the solder material in the direction of the first surface is south, flush or lower than the upper surface of the first metal ring; Tin (Sn), lead (10), silver (Ag), copper (Cu), zinc (Zn), bismuth (8), 1106 41 8 200939441 Enter one of the groups consisting of 1 (AU). The present invention further provides a package structure, comprising: a semiconductor package substrate, disposed on a substrate body having a first surface and a second surface, the number of through holes passing through the first and second surfaces, The first and second surfaces of the two ends of the through hole are respectively provided with a first __ and a second metal ring, and have a welding material inside the through hole, and the welding material extends to the first and second gold f a ring-shaped surface and a bump on the second metal ring; and the semiconductor f-sheet/system has an active surface having a plurality of electrode electrodes on the active surface, and a plurality of solder bumps on the electrode pad of the ❹j The semiconductor wafer is electrically connected to the solder material in the first surface direction of the hole of the semiconductor package base in a flip chip. In the above structure, the solder material is composed of tin, lead (10)), silver group L, CO 7 (Zn), Syria (8), Syria (Pd) and gold (f)): the first and second The metal ring is made of copper ((5); a bottom filling material is formed between the active surfaces of the conductor wafer. The structure is: package: coffee soldering material, the electric i is provided with a plurality of through holes and filling the holes therein The welding material·a electrode of the crucible can be directly passed through the complex pass efficiency H ^ to the printed circuit board (not shown), so as to improve the electrical contact of the electric component by the electrode pad of the semiconductor wafer And the reliability of the plurality of shovel shovel moons. The splicing materials are joined together to improve the connection. [Embodiment] The following is a specific example to illustrate the implementation of the present invention 110641 9 200939441, Those skilled in the art can easily understand the other advantages and effects of the present invention by the contents disclosed in the present specification. [Brief Example] Please refer to Figures 2A to 2G for detailed description of the method for manufacturing a semiconductor package substrate of the present invention. A schematic cross-sectional view of an embodiment. As shown in Figure 2A, first A substrate body 21 is provided with an opposite first surface 21a and a second surface 21b, and a first metal layer 221 and a second metal layer 222 are formed on the first and second surfaces 21a, 21b of the substrate body 21, respectively. The first metal layer 221 and the second metal layer 222 are made of copper (Cu). As shown in FIG. 2B, a plurality of through holes 23 are formed in the substrate body 21 and the first and second metal layers 221, 222. As shown in FIG. 2C, a conductive layer 24 is formed on the first and second metal layers 221 222 and the inner wall of the through hole 23. A resist layer 25 is formed on the conductive layer 24, and the through hole 23 is correspondingly exposed. As shown in FIG. 2D, the two ends are formed as a plurality of resistive openings 2 51. The conductive layer 2 on the peripheral surface is as shown in FIG. 2E, and the first solder material 271 is formed on the resistive opening 251. As shown in the figure, the resist layer 25 and its covered conductive layer are removed to form a plurality of first and second
如第2F 24、第一及第二金屬層221，222, 金屬環 221a，222a。For example, the 2F 24, the first and second metal layers 221, 222, and the metal rings 221a, 222a.
Π064] 如第2G至2G” 對應該第二金屬環； 10 200939441 > μ，且使該第二焊接材料272與第一焊接材料271結合 焊接材料27;該通孔23中位於該第一表面21a方向二 坏接材料表面27a，27b，27c係低於（如第2G圖所示）、齊 平（如第2G，圖所示）或高於該第一金屬環221a表面（如第 2G”圖所示）；該焊接材料27係為錫（％)、鉛（⑼）、銀 (Ag)、銅（Cu)、鋅（Zn)、鉍（Bi)、鈀（Pd)及金（Au)所組成 群組之其中一者。 本發明復揭露一種半導體封裝基板，係包括：基板本 ❹體2卜係具有相對之第一表面21a及第二表面21b,以及 複數貝穿该第一及第二表面21a 21b之通孔23;第一及 第一金屬環221a，222a，係分別對應設於該些通孔23兩 端之第一及第二表面2ia，21b上；以及焊接材料27，係 填充於該些通孔23内部並延伸至該第一及第二金屬環 221a’222a上，並於該第二金屬環222a上呈凸塊狀。 依上述結構’復包括導電層24設於該通孔23内壁、 第及第一金屬環221a，222a等表面上與該焊接材料27 1 <卜接材料27係為錫（sn)、錯（pb)、銀（Ag)、銅 (Cuj、鋅（Zn)、鉍（Bi)、鈀（pd)及金（Au)所組成群組之其 中一者；該通孔23中位於該第一表面21a方向之焊接材 料表面27a，27b，27c係低於（如第2G圖所示）、齊平（如第 2 G ’圖所，）或高於該第一金屬環2 21 a上表面（如第2 G，，圖 所示），。亥第一及第二金屬環221a，係為銅（Cu)。 [第二實施例] 咕參閱第3A至3C圖，係詳細說明本發明之半導體封 110641 11 200939441 $签极装汝苐二實施例之剖面示意圖。 如第3A圖所示，首先提供一係如 構，並於該阻声開口 φ + 弟2D圖所不之結 全屬声2β 2 導電層24上電錢形成第： 金屬層26’该第三金屬層26係為 ： 層26上電鑛形成第一焊接材料271。 ㈣弟二金屬 ?所示，移除該阻層25及其覆蓋之導電層 兩m及弟"金屬層肌222，以形成位於該通孔23 弟3C至3C圖所不，於該第一焊 對應該第二金屬環2223虚，报占Λ祕此 111 蜀衣以“處，形成凸塊狀之第二焊接材料 ，且使该第二焊接材料272與第一焊接材料271結合 成焊接材料27,且該通孔23中位於該第_表面2ia = 之焊接材料表面27a，27b，27c係低於（如第3C圖所示）、 齊=(如第3C’圖所示）或高於（如第3C，，圖所示）該第一金 屬環221a表面上該第三金制26之表面；該焊接材料 27 係為錫（Sn)、鉛（pb)、銀（Ag)、銅（Cu)、鋅（^)、鉍 (Βι)、鈀（Pd)及金（Au)所組成群組之其中一者。 本發明復揭露一種半導體封裝基板，係包括：基板本 體2卜係具有相對之第一表面21a及第二表面21b，以及 複數貫穿該第一及第二表面21 a, 21b之通孔23;第一及 第一金屬環221a，222a’係分別對應設於該些通孔23兩 端之第一及第二表面21a，21b上；第三金屬層26，係設 於該些第一、第二金屬環221a，222a上及該通孔23内壁， 12 110641 200939441 %通孔；以及谭接材料27 ’係設該第三金屬層 -26上’並於该第一金屬環222a表面上該第三金屬層26 上呈凸塊狀。 於該通孔23内壁、第一及第二金屬環221a，222a等 表面與第三金屬層26與之間復設有導電層24;該焊接材 料 27 係為錫（Sn)、錯（Pb)、銀（Ag)、鋼（cu)、鋅（2n)、 鉍（Bi)、鈀（Pd)及金（Au)所組成群組之其中—者；該通孔 23中位於該第一表面21a方向之烊接材’料/表面 27a’27b，27c係低於（如第3C圖所示）、齊平（如第况，圖 所示）或高於（如第3C”圖所示）第一金屬環221&表面上該 第三金屬層26之表面’·該些第—、第二金屬環2仏鳥 及第三金屬層26係為銅（Cu)。 [第三實施例] 請參閱第4圖，係詳細說明本發明之封裝結構之剖面 不意圖，提供-具有作用面，之半導體晶片Μ，於該 作用面20a具有複數電極& 2〇1，於該些電極塾2〇1 ©應設有複數烊料凸塊273，使該半導體晶片Μ以覆晶接 二 =過：焊料凸塊273對應電性連接該基板本體η 广 中之焊接材料27,且於該第一表面21a盘 :晶片20的作用面2〇a之間形成底充材料如該 表面仙之第二金屬環肋上形成之 料272則供電性連接至其他電子元件或電路板上^接材 基板 a，21b自权有複數通孔23及填充其中之 110641 13 200939441 p要材们/，電訊自半導體W 2()巧歸2 經該通孔23中之焊接材料27傳浐 接 't4a 寸“得輸至印刷電路板（圖未 不），俾以提高電性傳輸效率；再者，封裝件之電性接點 係由+導體晶片20之電極墊2〇1與填充該通孔23中之焊 接材料27接合而成，俾以提高接點可靠度。 上述實施例僅例示性說明本發明之原理及其功效，而 非用於限制本發明。任何熟習此項技藝之人士均可在 :本：明之精神及範嘴下’對上述實施例進行修飾與： 〇範圍所：本發明之核利保護範圍’應如後述之申請專利 【圖式簡單說明】 第1A至1Η圖係為習知之車道挪^立士 、目一 4 . 白^之牛導體封裝基板製作流程剖 視不意圖； 第2Α至2G®係為本發明之半導體封|基板之 一實施例之剖視示意圖； '弟 第2G至2G”®係為本發明之半導體封職板第—· ❹施例的通孔中焊接材料表面高度的剖視示意圖； " 第3Α至3C®係為本發明之半導體封|基板之製法 二實施例之剖視示意圖； '"第 第3C至3C”圖係為本發明之半導體封裝基板第 施例的通孔中焊接材料表面高度的剖視示f、圖；以及—貫 第4圖係為本發明之封襄結構之剖視示意圖。 【主要元件符號說明】 " la, lb 線路層 Π0641 14 26 27 焊接材料 27a, 27b，27c焊接材料表面 271 第一焊接材料 272 第二焊接材料 273 焊料凸塊 30 底充材料 200939441 10a,10b 11, 21 12, 221 13, 23 14, 24 15, 222 16 17, 25 171,251 ❹18 181,182 19a, 19b 20 20a 201 21a 21b ❹ 221a 222a 電性連接墊 基板本體 第一金屬層 通孑L 導電層 第二金屬層 基孔材料 阻層 阻層開口 絕緣保護層 開孔 結合材料 半導體晶片 作用面 電極墊 第一表面 第二表面 第一金屬環 第二金屬環 第三金屬層Π 064] as in the 2G to 2G ” corresponds to the second metal ring; 10 200939441 > μ, and the second solder material 272 is bonded to the first solder material 271 by the solder material 27; the through hole 23 is located on the first surface 21a direction two bad material surface 27a, 27b, 27c is lower (as shown in Figure 2G), flush (as shown in Figure 2G, shown) or higher than the surface of the first metal ring 221a (such as 2G) The solder material 27 is tin (%), lead ((9)), silver (Ag), copper (Cu), zinc (Zn), bismuth (Bi), palladium (Pd) and gold (Au). One of the grouped groups. The present invention discloses a semiconductor package substrate, comprising: a substrate body 2 having a first surface 21a and a second surface 21b opposite thereto, and a plurality of through holes 23 penetrating the first and second surfaces 21a 21b; The first and first metal rings 221a, 222a are respectively disposed on the first and second surfaces 2ia, 21b disposed at the two ends of the through holes 23; and the solder material 27 is filled in the through holes 23 and The first and second metal rings 221a' 222a are extended and have a convex shape on the second metal ring 222a. According to the above structure, the conductive layer 24 is provided on the inner wall of the through hole 23, the first metal ring 221a, 222a, and the like, and the solder material 27 1 < the bonding material 27 is tin (sn), wrong ( One of a group consisting of pb), silver (Ag), copper (Cuj, zinc (Zn), bismuth (Bi), palladium (pd), and gold (Au); the through hole 23 is located on the first surface The surface 27a, 27b, 27c of the solder material in the direction 21a is lower (as shown in Fig. 2G), flush (as in Fig. 2G'), or higher than the upper surface of the first metal ring 2 21 a (e.g. The second and second metal rings 221a are made of copper (Cu). [Second embodiment] Referring to Figures 3A to 3C, the semiconductor package of the present invention will be described in detail. 110641 11 200939441 A schematic cross-sectional view of the embodiment of the signature pole assembly. As shown in Fig. 3A, firstly, a series of structures is provided, and the sound insulation opening φ + 2D diagram is not the sound 2β 2 The electric layer 24 is formed on the conductive layer 24: the metal layer 26' is: the layer 26 is electroformed to form the first solder material 271. (4) The second metal layer is removed, and the resist layer 25 is removed. Covering the conductive layer two m and the younger "metal layer muscle 222, to form in the through hole 23 brother 3C to 3C map, in the first welding corresponding to the second metal ring 2223 virtual, report the secret of this 111 The second coating material is formed in a convex shape, and the second welding material 272 and the first welding material 271 are combined into a welding material 27, and the through hole 23 is located at the first surface 2ia = The surface of the solder material 27a, 27b, 27c is lower (as shown in Fig. 3C), Qi = (as shown in Fig. 3C') or higher (as shown in Fig. 3C, Fig. 3), the first metal ring 221a The surface of the third gold 26 is on the surface; the solder material 27 is tin (Sn), lead (pb), silver (Ag), copper (Cu), zinc (^), strontium (Βι), palladium (Pd) And a semiconductor package substrate, comprising: a substrate body 2 having opposite first and second surfaces 21a, 21b, and a plurality of a through hole 23 of the first and second surfaces 21 a, 21b; the first and first metal rings 221a, 222a' respectively correspond to the first and second tables disposed at the two ends of the through holes 23 21a, 21b; a third metal layer 26 is disposed on the first and second metal rings 221a, 222a and the inner wall of the through hole 23, 12 110641 200939441% through hole; and the tanned material 27' is provided The third metal layer -26 is on the surface of the first metal ring 222a and has a convex shape on the third metal layer 26. The inner wall of the through hole 23, the first and second metal rings 221a, 222a, etc. The third metal layer 26 is provided with a conductive layer 24; the solder material 27 is tin (Sn), wrong (Pb), silver (Ag), steel (cu), zinc (2n), bismuth (Bi) And among the groups consisting of palladium (Pd) and gold (Au); the material of the through hole 23 located in the direction of the first surface 21a is a material/surface 27a'27b, 27c is lower than (e.g. 3C), flush (as shown in the figure, as shown) or higher (as shown in Fig. 3C)) the surface of the third metal layer 221 & surface on the first metal ring 221 & The second metal ring 2 ostrich and the third metal layer 26 are copper (Cu). [THIRD EMBODIMENT] Referring to Fig. 4, a cross-sectional view of a package structure of the present invention is not described in detail, and a semiconductor wafer having an active surface is provided, and the active surface 20a has a plurality of electrodes & The plurality of solder bumps 273 are disposed on the electrodes 塾2〇1 © such that the semiconductor wafers are flip-chip bonded to each other. The solder bumps 273 are electrically connected to the substrate body η. And forming an underfill material between the active surface 2〇a of the first surface 21a: the wafer 20, such as the material 272 formed on the second metal ring rib of the surface, to be electrically connected to other electronic components or circuit boards. The upper substrate substrates a, 21b are self-owned with a plurality of through holes 23 and filled with 110641 13 200939441 p material /, the telecommunications from the semiconductor W 2 () 2 is passed through the solder material 27 in the through hole 23 Connect 't4a inch' to the printed circuit board (not shown) to improve the electrical transmission efficiency; further, the electrical contact of the package is made up of the electrode pad 2〇1 of the +conductor wafer 20 and fill the The solder material 27 in the through hole 23 is joined to improve the reliability of the contact. The present invention is merely illustrative of the principles and effects thereof, and is not intended to limit the invention. Any person skilled in the art can modify the above embodiments with the following: The "nuclear protection scope of the present invention" should be as described in the following patent application [Simple description of the drawings] The 1A to 1Η drawings are the conventional lanes of the mobile phone No. 2, and the first one. 4. The production process of the white conductor package substrate The cross-sectional view is not intended; the second to 2G® is a schematic cross-sectional view of one embodiment of the semiconductor package | substrate of the present invention; 'di 2G to 2G' is the semiconductor sealing plate of the present invention - A cross-sectional view of the surface height of the solder material in the through hole of the example; " 3rd to 3C® is a schematic cross-sectional view of the second embodiment of the method for manufacturing the semiconductor package|substrate of the present invention; '" 3C to 3C" FIG. 4 is a cross-sectional view showing the height of the surface of the solder material in the through hole of the embodiment of the semiconductor package substrate of the present invention; and FIG. 4 is a cross-sectional view showing the sealing structure of the present invention. Description] " la, lb circuit layer Π0641 14 26 27 Welding material 27a, 27b, 27c Welding material surface 271 First soldering material 272 Second soldering material 273 Solder bump 30 Underfill material 200939441 10a, 10b 11, 21 12, 221 13, 23 14, 24 15, 222 16 17, 25 171,251 ❹18 181,182 19a, 19b 20 20a 201 21a 21b ❹ 221a 222a Electrical connection pad substrate body first metal layer through 孑L conductive layer second metal layer base hole material barrier layer open layer insulation protective layer Hole bonding material semiconductor wafer active surface electrode pad first surface second surface first metal ring second metal ring third metal layer